MODELLING OF SHORT CHANNEL EFFECT OF SUBMICRON MOS DEVICE

A PROJECT REPORT Submitted by

Sohini Mondal Rajasree Hazra Shaswati Sardar Ratna Rajak Soham Maiti

in partial fulfillment for the award of the degree of

B.TECH
IN Electronics & Communication Engineering

INSTITUTE OF SCIENCE & TECHNOLOGY (Approved by AICTE & Affiliated to West Bengal University of Technology)
UNDER THE GUIDANCE OF

Mr. SITANSHU CHOUDHURY

ASST. PROFESSOR Department of Electronics & Communication Engineering INSTITUTE OF SCIENCE & TECHNOLOGY

THIS PROJECT IS DEDICATED TO OUR RESPECTED PARENTS

ABSTRACT
With the advent of semiconductor technology in VLSI era, the channel length of a Metal oxide semiconductor has drastically gone down. Drain Induced Barrier Lowering is one of the short channel effect which degrades the performance of a MOSFET with its down scaling. To understand this effect the study of the nature of surface potential and energy is very important. In this project an analytical model for threshold voltage of shortchannel MOSFETs is presented. For such devices, the depletion regions due to source/drain junctions occupy a large portion of the channel, and hence are very important for accurate modeling. The proposed threshold voltage model is based on a realistic physically-based model for the depletion layer depth along the channel that takes into account its variation due to the source and drain junctions. With this, the unrealistic assumption of a constant depletion layer depth has been removed, resulting in an accurate prediction of the threshold voltage. The proposed model can predict the drain induced barrier lowering (DIBL) effect and hence, the threshold voltage roll-off characteristics quite accurately. The model predictions are verified against the simulator MATLAB and P-Spice.

CONTENTS
CHAPTER 1: INTRODUCTION
1.1 MOTIVATION OF THE THESIS 1.2 ANALYTICAL MODEL 1.3 ORGANISATION OF THE THESIS 1-6 2 3 6

CHAPTER 2: PHYSICS OF DRAIN INDUCED BARRIER LOWERING 7-15

2.1 GENERAL CONCEPT OF DRAIN INDUCED BARRIER LOWERING 2.2 DRAIN INDUCED BARRIER LOWERING AND PUNCH THROUGH 2.3 SURFACE SCATTERING 2.4 VELOCITY SATURATION 2.5 THE MODIFICATION OF THE THRESHOLD VOLTAGE DUE TO SHORT-CHANNEL EFFECTS 7 9 10 11 11

CHAPTER 3: NUMERICAL ANALYSIS

3.1 NUMERICAL ANALYSIS OF THE PROJECT

16-18 16 19-27

CHAPTER 4: MATLAB PROGRAMS

4.1 MAT-LAB PROGRAM FOR VERIFICATION OF THRESHOLD 19 VOLTAGE WITH CHANNEL LENGTH 4.2 MAT-LAB PROGRAM FOR VERIFICATION OF THRESHOLD 23 VOLTAGE WITH CHANNEL LENGTH 4.3 MATLAB PROGRAM FOR VARIATION OF THRESHOLD 27 VOLTAGE REDUCTION WITH CHANNEL LENGTH

CHAPTER 5 : CONCLUSION, RESEARCH/FURTHER WORK

5.1 CONCLUSION 31 31 32 33

5.2 RESEARCH/FURTHER WORK

5.3 APPENDIX A 5.4 REFERENCES

Chapter 1:

Introduction:
Demand for larger scale integration of MOS circuits on a single chip urged of miniaturization of MOS devices. As the channel length shrinks, many short channel effects were observed mainly reduction of threshold voltage, increased off-state leakage current and Drain-induced barrier lowering. Charge sharing model have been used to model the short-channel effects(SCEs). The charge sharing model assumptions of constant surface potential and no divergence of electric field lines in the gate oxide are invalid for high drain and substrate biases. On the other hand, two-dimensional analysis has accurately predicts the values of threshold voltage of short channel MOSFETs and breakdown voltage. We have derived the analytical relations for surface potential, threshold voltage and longitudinal field. Without any assumption, we have proposed a model for short channel factor which shows the dependence on the channel width and drain voltage. We have compared our results with various reported results. The effect of charge carrier density is to raise the threshold voltage of submicron devices operating at any drain voltage. It is observed from our analysis that short-channel effect is more dominant in the sub-micron devices with thinner gate oxide. Our study also predicts that DIBL effect in short channel device is more effective in presence of charge carrier density. It is also observed that the short channel factor shows a weak dependence on the substrate doping due to the inclusion of carrier charge density in the model. 1

1.1 Motivation:
The barrier lowering results in a shift of threshold voltage as a function of the drain voltage for short channel device because the depletion widths at source and drain junction becomes comparable to the channel length. The depletion region near the source and drain approach each other thus decreasing the potential barrier.With increase in the drain bias further result in lowering of barrier, which in turn causes substantial leakage current to flow. Detailed study of this variation of barrier potential is needed to understand the variation of surface potential along the channel for different drain biases. This effect is found by solving 2-D Poissons equation . The channel length shrinks, the lateral field due to the penetration of edge effect into the channel region becomes very important . Charge sharing model ,assuming a trapezoidal depleted channel region start penetrating from two ends. Ratnakumar and Meindl have solved threshold voltage model with boundary condition that assume constant surface potential . Study of threshold voltage reduction due to different parameter like drain to source voltage ,surface potential, channel length and accepter concentration.

1.2 Analytical model:

An electric field is created in the depletion region by the separation of positive and negative space charge densities. The figure given bellow shows the volume charge density distribution in the p-n junction assuming uniform doping and assuming an abrupt junction approximation. We will assume that the space charge region abruptly ends in the n region at X=Xn, and abruptly ends in the p region at X= Xp. The electric field is determined from Poisson's equation for a one dimensional analysis is where (x) is the electric potential, E(x) is the electric field, p(x) is the volume charge density, and F, is the permittivity of the semiconductor. The charge densities are = -e Na and = -e Nd The electric field in the p region is E.=

where is a constant of integration. The electric field is assumed to be zero in the neutral p region for x < -x, since the currents are zero in thermal equilibrium. As there are no surface charge densities within the p-n junction structure. the electric field is a continuous function. The constant of integration is determined by setting E = 0 at x = -x,. The electric field in the p region is then given by E = = In the n region, the electric field is determined from E = The constant C2 is determined by setting the E-field is assumed to be zero E = Again = . This equation states that the number of negative charges per unit area in the p region is equal to the number of positive charges per unit area in the n region. The potential in the junction is found by integrating the electric field. In the p region then, we have

or = where C1 is again a constant of integration. The potential difference through the p-n junction is the important parameter, rather than the absolute potential, so we may arbitrarily set the potential equal to zero at x = -Xp. The constant of integration is The potential in the p region can now be written as = The potential in these region is determined by integrating the electric field in the n region

Then = integration. =

where

is another constant of

Fig: 2 Electronic potential through space charge of uniformly doped p-n junction.

1.3 Organization of this Thesis:

The dissertation is divided into five chapters and its outline is described as given fundamental concepts are discussed over here. a) Chapter 1: Introduction deals with Motivation for the work , fundamental concepts are discussed over here. b) Chapter 2: Theory Here the concept of Drain Induced Barrier Lowering model is discussed. The model details the role of various MOS parameter like Junction Width, zero biased threshold voltage bulk depletion width, oxide interface charge, work function. c) The Numerical methods are discussed in Chapter 3 d) Results of simulation studies are given in Chapter 4 e) Chapter 5: Ends with Conclusions

CHAPTER 2

2.1 Physics of Drain induced Barrier Lowering

The drain induced barrier lowering (DIBL) effect is one of the more important affects in short channel MOSFET devices. The barrier lowering effect is observed by a shift of threshold voltage as a function of drain voltage of short channel device. In short channel MOSFET, it is well known that the depletion width at source and drain junction become comparable to the channel length. The effect of decreasing channel length caused the depletion region width surround the source and drain diffusion to approach each other. Depending on the drain bias, the electric field at the drain can penetrate to the source region of the device caused the decreasing of potential barrier at source. As a result, the device can conduct significant drain current due to an increase of carrier injected from the source. This mechanism is responsible for the strong dependence of sub threshold current on the drain bias. Moreover the sub threshold current will change the threshold voltage as the drain bias is varied. Empirical observation that the threshold voltage decreases linearly with increasing drain voltage maybe express as follows: This project is to experimentally demonstrate the relationship between the DIBL effect and the channel length reduction for short channel.

The threshold voltage shift (DIBL) varied linearly with the drain voltage at drain terminal and the DIBL parameter varied with the channel length.

A MOSFET device is considered to be short when the channel length is

the same order of magnitude as the depletion-layer widths (XdD, XdS) of the source and drain junction. As the channel length L is reduced to increase both the operation speed and the number of components per chip, the so-called short-channel effects arise. The short-channel effects are attributed to two physical phenomena: i) the limitation imposed on electron drift characteristics in the channel, ii). the modification of the threshold voltage due to the shortening channel length. In particular five different short-channel effects can be distinguished: a. Drain-induced barrier lowering and punch through b. Surface scattering c. Velocity saturation d. Impact ionization e. Hot electrons

2.2 Drain-induced barrier lowering and punch through:

The expressions for the drain and source junction widths are: XdD = And XdS = where VSB and VDB are source-to-body and drain-to-body voltages. When the depletion regions surrounding the drain extends to the source, so that the two depletion layer merge (i.e., when XdD + XdS = L), punch trough occurs. Punch through can be minimized with thinner oxides, larger substrate doping, shallower junctions, and obviously with longer channels. The current flow in the channel depends on creating and sustaining an inversion layer on the surface. If the gate bias voltage is not sufficient to invert the surface (VGS<VT0), the carriers (electrons) in the channel face a potential barrier that blocks the flow. Increasing the gate voltage reduces this potential barrier and, eventually, allows the flow of carriers under the influence of the channel electric field. In small-geometry MOSFETs, the potential barrier is controlled by both the gate-to-source voltage VGS and the drain-to-source voltage VDS. If the drain voltage is increased, the potential barrier in the channel decreases, leading to drain-induced barrier lowering (DIBL). The reduction of the potential barrier eventually allows electron flow between the source and the drain, even if the gate-to-source voltage is lower than the threshold voltage. The channel current that flows under this conditions (VGS<VT0) is called the sub-threshold current.

2.3 Surface scattering

As the channel length becomes smaller due to the lateral extension of the depletion layer into the channel region, the longitudinal electric field component ey increases, and the surface mobility becomes fielddependent. Since the carrier transport in a MOSFET is confined within the narrow inversion layer, and the surface scattering (that is the collisions suffered by the electrons that are accelerated toward the interface by ex) causes reduction of the mobility, the electrons move with great difficulty parallel to the interface, so that the average surface mobility, even for small values of ey, is about half as much as that of the bulk mobility.

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2.4 Velocity saturation:

The performance short-channel devices is also affected by velocity saturation, which reduces the Trans conductance in the saturation mode. At low ey, the electron drift velocity vde in the channel varies linearly with the electric field intensity. However, as ey increases above 104 V/cm, the drift velocity tends to increase more slowly, and approaches a saturation value of vde(sat)=107 cm/s around ey =105 V/cm at 300 K. Note that the drain current is limited by velocity saturation instead of pinchoff. This occurs in short channel devices when the dimensions are scaled without lowering the bias voltages. Using vde(sat), the maximum gain possible for a MOSFET can be defined as gm=WCoxVde(sat)

2.5 The modification of the threshold voltage due to ShortChannel Effects:

The equation giving the threshold voltage at zero-bias + is accurate in describing large MOS transistors, but it collapses when applied to small-geometry MOSFETs. In fact that equation assumes that the bulk depletion charge is only due to the electric field created by the gate voltage, while the depletion charge near n+ source and drain region is actually induced by p-n junction band bending. Therefore, the amount of bulk charge the gate voltage supports is overestimated, leading to a larger VT than the actual value.

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The electric flux lines generated by the charge on the MOS capacitor gate electrode terminate on the induced mobile carriers in the depletion region just under the gate. For short-channel MOSFETs, on the other hand, some of the field lines originating from the source and the drain electrodes terminate on charges in the channel region. Thus, less gate voltage is required to cause inversion. This implies that the fraction of the bulk depletion charge originating from the p-n junction depletion and hence requiring no gate voltage, must be subtracted from the V expression.

Fig : 4 Geometry of the gate-induced bulk depletion region The figure shows the simplified geometry of the gate-induced bulk depletion region and the p-n junction depletion regions in a short channel MOS transistor.

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Note that the bulk depletion region is assumed to have and asymmetric trapezoidal shape, instead of a rectangular shape, to represent accurately the gate-induced charge. The drain depletion region is expected to be larger than the source depletion region because the positive drain-to-source voltage reversed-biases the drain substrate junction. We recognize that a significant portion of the total depletion region charge under the gate is actually due to the source and drain junction depletion, rather than the bulk depletion induced by the gate voltage. Since the bulk depletion charge in the short channel device is smaller than expected, the threshold voltage expression must be modified to account for this reduction: VTO(Short Channel) = VTO - VTO where VT0 is the zero-bias threshold voltage calculated using the conventional long-channel formula and VTO is the threshold voltage shift (reduction) due to the short-channel effect. The reduction term actually represents the amount of charge differential between a rectangular depletion region and a trapezoidal depletion region.

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Let LS and LD represent the lateral extent of the depletion regions associated with the source junction and the drain junction, respectively. Then, the bulk depletion region charge contained within the trapezoidal region To calculate LS and LD, we will use the simplified geometry shown in the figure.

Here, XdS and XdD represent the depth of the pn-junction depletion regions associated with the source and the drain, respectively. The edges of the source and drain diffusion regions are represented by quarter-circular arcs, each with a radius equal to the junction depth, xj. The vertical extent of the bulk depletion region into the substrate is represented by xdm. The junction depletion region depths can be approximated by XdD = and XdS =

14

with the junction built-in voltage

From figure, we find the following relationship between DLD and the depletion region depths.

Solving for LD we obtain: =-1

Similarly, the length LS can also be found as follows: = -1

Now, the amount of the threshold voltage reduction DVT0 due to shortchannel effects can be found as: . . .[(
-1) + -1]

The threshold voltage shift term is proportional to xj/L. As a result, this term becomes more prominent for MOS transistors with shorter channel lengths, and it approaches zero for long channel MOSFETs where L >> xj.

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Chapter 3 Numerical analysis :

We consider an n-channel MOS process with the following parameters: substrate doping density NA=1016 cm-3 poly-silicon gate doping density ND (gate) = 2 1020 cm-3 , gate oxide thickness tox= 50 nm, oxide-interface fixed charge density Nox=4*1010 cm-2 , and source and drain diffusion doping density ND= 1017 cm-3 . In addition, we assume that the channel region is implanted with p-type impurities (impurity concentration NI= 2 1011 cm-2 ) to adjust the threshold voltage. Moreover, the junction depth of the source and drain diffusion regions is xj=1.0 mm Plotting the variation of the threshold voltage VT as a function of the channel length. Now, we can calculate the work function difference between the gate and the channel: GC = GC(Substrate)- F(gare)
=

-0.35V 0.55V= -0.90 V.

The depletion region charge density at VSB=0 is found as follows: ln = 0.026.ln{(1.45*1010)/(2*1015)} = -0.3077 =

= - 4.82 10-8 C/cm2

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The oxide-interface charge is: Qox= q Nox= 1.6*10-19*4*1010 = 6.4 10-9 C/cm2 The gate oxide capacitance per unit area is calculated using the dielectric constant of the silicon dioxide and the oxide thickness tox: F/ we can combine all components and calculate the threshold voltage

-( ) = (- 4.82 10-8) / (7.03 *10-8) = -0.6856 = 0.090 -( ) = 0.40 V

We find the long-channel zero-bias threshold voltage for the process described above as + = 0.40 +{(1.6*1010)* 1011} = 0.855 V

Next, the amount of the threshold voltage reduction due to shortchannel effects must be calculated. The source and drain junction built-in voltage is 0.026 ln = 0.76 v

The depths of source and drain junction depletion regions is found as XdS = = 0 .026.ln{(2*1020)/(1016)}/(1.45*1010)2 =0.9147

17

XdS = Xds = =

= 0.314 mm =

Now, the threshold voltage shift

can be calculated as a function of

the gate length L and of the drain-to-source voltage VDS

.[(

-1) +

-1]

=1/(7.03*10-8)* (2(1.6*10-19)*11.7*8.85*10-14*2*10-15*2*0.3077)*1/10-6[1+(2*8.03*10-5 (0+VDS)-1] + {1+(2*0.76*10-6)/106 } = 0.2873+0.5875+1+16.06*10-9*(VDS+0.91)-1 = ( 0.343/ L[m] ) * (-0.724 + ( 1 + 2 xdD) The threshold voltage of this short-channel MOS transistor is calculated as VT0 = 0.855V - VTO

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Chapter 4 The Mat lab simulating program, Results, Command: 4.1 Mat lab Program for verification of threshold voltage with Channel Length

close all, clear all; % arrays for the different values of Vth @ Vds=1V,Vds=3V, Vds=5V. vector_vt1=[ ]; vector_vt3=[ ]; vector_vt5=[ ]; % arrays for the different values of L @ Vds=1V,Vds=3V, Vds=5V. vector_l1=[ ]; vector_l3=[ ]; vector_l5=[ ]; % for Vds=1 V vds=1; for l=0.5:0.1:6 rad2=sqrt(0.13*(0.76+vds)); rad1=sqrt(1+(2*rad2)); deltavt=(0.343/l)*(rad1-0.724); vt=0.855-deltavt; vector_l1=[vector_l1,l]; vector_vt1=[vector_vt1,vt]; end %for Vds=3 V vds=3; for l=0.5:0.1:6 rad2=sqrt(0.13*(0.76+vds)); rad1=sqrt(1+(2*rad2));

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deltavt=(0.343/l)*(rad1-0.724); vt=0.855-deltavt; vector_l3=[vector_l3,l]; vector_vt3=[vector_vt3,vt]; end %for Vds=5 V vds=5; for l=0.5:0.1:6 rad2=sqrt(0.13*(0.76+vds)); rad1=sqrt(1+(2*rad2)); deltavt=(0.343/l)*(rad1-0.724); vt=0.855-deltavt; vector_l5=[vector_l5,l]; vector_vt5=[vector_vt5,vt]; end % graps of Vth vs. L @ Vds=1V,Vds=3V, Vds=5V. plot(vector_l1,vector_vt1,':',vector_l3,vector_vt3,'.',vector_l5,vector_vt5,'.'), %comments on the plot xlabel('L: Channel length [um]'), ylabel('Vth: Threshold voltage [V]'), title('(Vth vs. L) @ Vds=1V [-----] Vds=3V [_._._] Vds=5V [.....]');

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Fig : 6 Variation of threshold voltage with Channel Length

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Data sheet forVth =1 v Channel length (m) 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.7 1.8 1.9 2.0 2.1 2.2 2.6 2.8 3.0 3.3 3.6 3.9 4.2 4.6 5.0 5.4 5.7 6.0

Channel length=6 (m) Threshold voltage

For Vds =1v 0.2181 0.3242 0.400 0.4589 0.5011 0.5365 0.5655 0.5896 0.61 0.6275 0.6427 0.6677 0.6781 0.6874 0.6958 0.7033 0.7102 0.7325 0.7413 0.7488 0.7585 0.7665 0.7733 0.7792 0.7858 0.7913 0.796 0.7991 0.80

For Vds =3v 0.2893 0.3836 0.4509 0.5014 0.5407 0.5721 0.5979 0.6193 0.6374 0.653 0.6664 0.6886 0.6979 0.7061 0.7136 0.7203 0.7264 0.7462 0.754 0.7607 0.7693 0.7764 0.7825 0.7877 0.7935 0.7984 0.8026 0.8054 0.8079

For Vds =5v 0.3921 0.4692 0.5243 0.5657 0.5978 0.6235 0.6446 0.6621 0.677 0.6897 0.7007 0.17188 0.7264 0.7332 0.7393 0.7448 0.7498 0.766 0.7723 0.7778 0.7849 0.7907 0.7957 0.7999 0.8047 0.8087 0.8121 0.8144 0.8164

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4.2 Mat-lab Program for verification of threshold voltage with Channel Length
close all, clear all; % arrays for the different values of Vth @ Vds=1V,Vds=3V, Vds=5V. vector_vt1=[ ]; vector_vt3=[ ]; vector_vt5=[ ]; % arrays for the different values of L @ Vds=1V,Vds=3V, Vds=5V. vector_l1=[ ]; vector_l3=[ ]; vector_l5=[ ]; % for Vds=1 V vds=1; for l=0.5:0.1:6 rad2=sqrt(0.65*(0.91+vds)); rad1=sqrt(1+(2*rad2)); deltavt=(0.1437/l)*(rad1-0.4125); vt=0.2235-deltavt; vector_l1=[vector_l1,l]; vector_vt1=[vector_vt1,vt]; end %for Vds=3 V vds=3; for l=0.5:0.1:6 rad2=sqrt(0.65*(0.91+vds)); rad1=sqrt(1+(2*rad2)); deltavt=(0.1437/l)*(rad1-0.4125); vt=0.2235-deltavt; vector_l3=[vector_l3,l]; vector_vt3=[vector_vt3,vt]; end

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%for Vds=5 V vds=5; for l=0.5:0.1:6 rad2=sqrt(0.65*(0.91+vds)); rad1=sqrt(1+(2*rad2)); deltavt=(0.1437/l)*(rad1-0.4125); vt=0.2235-deltavt; vector_l5=[vector_l5,l]; vector_vt5=[vector_vt5,vt]; end % graps of Vth vs. L @ Vds=1V,Vds=3V, Vds=5V. plot(vector_l1,vector_vt1,':',vector_l3,vector_vt3,'.',vector_l5,vector_vt5,'.'), grid %comments on the plot xlabel('L: Channel length [um]'), ylabel('Vth: Threshold voltage [V]'), title('(Vth vs. L) @ Vds=1V [-----] Vds=3V [_._._] Vds=5V [.....]');

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Fig : 6 Variation of threshold voltage with Channel Length Appling drain voltage applied to the device ,the barrier height is lowered even more, resulting further decrease of threshold voltage. It explains increasing of substrate current with drain voltage in short channel MOSFET. It explain substrate characteristics of long and short channel devices at different drain bias voltage. For long channel devices , the substrate current is independent of drain voltage .For short channel devices however there is a potential shift of the curve to a lower threshold voltage for high drain bias condition. At even shorter channel length the substrate slope starts to degrade as the surface potential is more controlled by the gate. Eventually the device reaches the punchthrough condition when the gate totally loses control of the channel and high drain current persists independent of gate voltage.

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Data sheet for Channel length (m) 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.7 1.8 1.9 2.0 2.1 2.2 2.6 2.8 3.0 3.3 3.6 3.9 4.2 4.6 5.0 5.4 5.7 6.0

Vth =0.2 v

Channel length =6 (m)

Threshold voltage For Vds =1v For Vds =3v For Vds =5v -0.2954 -0.2089 -0.1472 -0.1008 -0.06479 -0.03596 -0.01238 0.00728 0.02391 0.03817 0.05052 0.07087 0.07935 0.08694 0.09377 0.09995 0.1056 0.1237 0.1308 0.137 0.1449 0.1514 0.157 0.1617 0.1671 0.1716 0.1755 0.178 0.1803 -0.2461 -0.1679 -0.1119 -0.07002 -0.03741 -0.01131 0.02782 0.04287 0.05578 0.06696 0.07674 0.08537 0.09305 0.09991 0.1061 0.1117 0.1168 0.1332 0.1396 0.1452 0.1523 0.1583 0.1633 0.1676 0.1725 0.1765 0.18 0.1823 0.1844 -0.17430 -0.108 -0.06067 -0.02515 0.002475 0.02458 0.04266 0.05773 0.07048 0.08141 0.09089 0.09917 0.1065 0.113 0.118 0.124 0.1288 0.1331 0.147 0.1525 0.1572 0.1632 0.1682 0.1725 0.1761 0.1803 0.1837 0.1867 0.1903

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4.3 Mat lab Program for variation of threshold voltage reduction with Channel Length
%variation of threshold volt with channel length clc; clear all; close all; L=0:0.1:3; eox=3.9*8.85*10^-14;% dielectric constant of sio2 esi=11.7*8.85*10^-14; tox=450*10^-8; cox=eox/tox; e=1.6*10^-19;% electronic charge vt=0.0259; % kT/q Na1=3*10^16; Na2=10^15; Na3=10^16; ni=1.5*10^10; rj=0.5*10^-6;% diffusion junction depth fp1=vt*log(Na1/ni);% Fermi potential fp2=vt*log(Na2/ni); fp3=vt*log(Na3/ni); xdt1=sqrt((4*esi*fp1)/(e*Na1));% Junction depth xdt2=sqrt((4*esi*fp2)/(e*Na2)); xdt3=sqrt((4*esi*fp3)/(e*Na3)); dvt1=-(e*Na1*xdt1/cox)*(rj./L)*(sqrt(1+(2*xdt1/rj))-1);% voltage shift dvt2=-(e*Na2*xdt2/cox)*(rj./L)*(sqrt(1+(2*xdt2/rj))-1); dvt3=-(e*Na3*xdt3/cox)*(rj./L)*(sqrt(1+(2*xdt3/rj))-1); subplot(311) plot(L,dvt1); title('L vs. dvt1...') grid; subplot(312) plot(L,dvt2); title('L vs. dvt2...') grid;
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threshold

ylabel('Thresold volt reduction --->'); subplot(313) plot(L,dvt3); title('L vs. dvt3...') grid; %title('Plotting of channel length vs. reduction of thresold volt...') xlabel('channel length (in micron)--------->'); %variation of thresold volt with channel length

Fig : 7 Variation of threshold voltage reduction with Channel Length

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Data sheet For Channel length (in micron) Vs Threshold voltage reduction: Chanel length 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2 2.2 2.4 2.6 2.8 3.0 For 1 For 2 For 3

-4.252*10-5 -2.126*10-5 -1.417*10-5 -1.063*10-5 -8.503*10-6 -7.086*10-6 -6.074*10-6 -5.314*10-6 -4.724*10-6 -4.252*10-6 -3.865*10-6 -3.543*10-6 -3.271*10-6 -3.037*10-6 -2.834*10-6 -2.657*10-6 -2.501*10-6 -2.126*10-6 -1.933*10-6 -1.771*10-6 -1.635*10-6 -1.518*10-6 -1.417*10-6

-1.585*10-5 -7.924*10-6 -5.282*10-6 -3.962*10-6 -3.169*10-6 -2.641*10-6 -2.264*10-6 -1.981*10-6 -1.761*10-6 -1.585*10-6 -1.441*10-6 -1.321*10-6 -1.291*10-6 -1.132*10-6 -1.056*10-6 -9.904*10-7 -9.322*10-7 -8.341*10-7 -7.546*10-7 -6.89*10-7 -6.095*10-7 -5.66*10-7 -5.282*10-7

-3.172*10-5 -1.563*10-6 -1.042*10-6 -7.817*10-6 -6.253*10-6 -5.211*10-6 -4.467*10-6 -3.908*10-6 -3.474*10-6 -3.127*10-6 -2.842*10-6 -2.606*10-6 -2.233*10-6 -2.084*10-6 -1.954*10-6 -1.839*10-6 -1.737*10-6 -1.646*10-6 -1.563*10-6 -1.421*10-6 -1.203*10-6 -1.117*10-6 -1.042*10-6

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It is seen that, for short channels and large Vsb , the dependence of the effective threshold on Vsb diminishes. This correspondences to the fact that the lower base of the trapezoidal diminishes in length. The bottom of the trapezoidal is then practically cutoff from the rest of the substrate , and thus the control of the substrate on the charge inside the trapezoidal is small. Decreasing L tends to increases the DIBL, decreasing tox tends to decrease it. This is because then the gate is closer to the channel and is thus better able to keep control of the depletion region charge.

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CHAPTER 5

5.1Conclusions
The analytical threshold voltage model, presented in this project, is based on a model for depletion layer depth along the channel that takes into account its variations due to the source and drain junctions. By doing so, the sharing of the gate control on VT by the source/drain has properly been incorporated. In fact, the origin of threshold voltage reduction with reduced channel length, reduced substrate doping, and/or increased drain bias is primarily due to the non-negligible influence of the same on the overall channel depletion layer depth under the gate; particularly for short-channel MOSFETs. From the comparisons of the results with MATLAB, it can be concluded that the proposed analytical approach has the accuracy of near 2D numerical results.

5.2 RESEARCH AND FUTURE WORKSIn future another programs can be done in MATLAB or spice simulation can be done to get the Spice Simulations for ID VGS.In near future many research works regarding these topics can be done.

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APPENDIX-A

List of Abbreviation:
2-D : Two Dimensional DIBL : Drain Induced Barrier Lowering VLSI : Very Large Scale Integrated Circuit CMOS : Complementary Metal Oxide Semiconductor MOSFET : Metal Oxide Semiconductor Field Effect Transistor

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5.4 References
AJAY KUMAR SINGH An Analytical Model of Short Channel Effects in Sub-Micron MOS Devices Ritesh Gupta, Mridula Gupta, R.S. Gupta Generalized guide for MOSFET miniaturization . K.N Ratnakumar and J.D MeindlShort channel MOSFET threshold voltage model. J.D.Marshall Performance limits of silicon enhancement/depletion MOSFET integrated circuit, Stanford University, CA,Tech pp 46-47. Xing Zhou, Khee Yong Lim - A general approach to compact threshold Voltage formulation based on 2-D numerical simulation and experimental correlation for development Vivek K. De and James D. Meindl An analytical Threshold voltage and sub-threshold current model for short channel MOSFET . Kai Chen and Chenming Hu - Performance and Vdd scaling in deep sub micrometer CMOS Resve Saleh, Michael Benoit and Pete McCrorie - Power distribution planning Sung-Mo, Yusuf CMOS digital integrated circuits deep.sub-micron VLSI technology

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