Soft Macro Vs Hard macro? Soft macro Vs Hard macro?

Soft macro and Hard macro are categorized as IP's while being optimized for powe r, area and performance. When buying IP and evaluation study is usually made to weigh advantages and disa dvantages of one type of macro over the other like hardware compatibility issues like the different I/O standards within the design, and compatibility to reuse methodology followed by design houses. Soft macros? Soft macros are used in SOC implementations. Soft macros are in synthesizable RT L form, are more flexible than Hard macros in terms of reconfigurability. Soft m acros are not specific to any manufacturing process and have the disadvantage of being unpredictable in terms of timing, area, performance, or power. Soft macros carry greater IP protection risks because RTL source code is more po rtable and therefore, less easily protected than either a netlist or physical la yout data. Soft macros are editable and can contain standard cells, hard macros, or other soft macros. Hard macro? Hard macos are targeted for specific IC manufacturing technology. They are block level designs which are optimized for power or area or timing and silicon tested. While accomplishing physical design it is possible to only access pins of hard m acros unlike soft macros which allows us to manipulate the RTL. Hard macro is a block that is generated in a methodology other than place and ro ute ( i.e. using full custom design methodology) and is imported into the physic al design database (eg. Volcano in Magma) as a GDS2 file. Hardmacros are nothing but analog fullcustom blocks surrounded by some digital l ogic. Used in applications where we require less area ,power and speed In Simple terms, Hard Macros are fixed in size. Eg. Memories -->Hard macros are generally in the form of IPs (or we termed it as IPs !)..... -->Important is those sre block level designs which are silicon tested and prove d.... -->they might have been optimized for power or area or timing. -->In physical design you can access pins of hard macros unlike soft macos which allows us to manipulate in different way. -->you have frredom to move, rotate, flip but you can't touch inside anything in side macos -->very common example of hard maco is memory...it can be any design which carri es dedicated single functionality (in general) -->be aware of features and characteristics of hard macro before you use it in y our design... other than power, timing and area you also should know pin propert ies like sync pin etc -->LEF file format allows easy usage of macos in different tools http://asic-soc.blogspot.com hard core is nothing but memories like rams ....they are all ready design in you r lib.but u didnt change any connects.just u r using that macro only Hard macros are also called as IP that is intellectual property which we purchas e from different vendors like mentorgraphics and so on Note: Firm macros are in netlist format and are optimized for performance,area and pow

er using a specific technology node. Firm macros are more flexible and portable than hard macros. Firm macros are mode predictable in terms of performance and area when comparing with soft macros.

ASIC-SoC-VLSI Design: Power Gating ASIC-SoC-VLSI Design All about VLSI Digital Design

Home About Me Links STA Verilog HDL This Blog Linked From Here The Web This Blog Linked From Here The Web Power Gating Power Gating is effective for reducing leakage power [3]. Power gating is the technique wherein circuit blocks that are not in use are temporarily turned off to reduce the overall leakage power of the chip. This temporary shutdown time can also call as "low power mode" or "inactive mode". When circuit blocks are required for operation once again they are activated to "active mode". These two modes are switched at the appropriate time and in the suitable manner to maximize power performance while minimizing impact to performance. Thus goal of power gating is to minimize leakage power by temporarily cutting power off to selective blocks that are not required in that mode. Power gating affects design architecture more compared to the clock gating. It increases time delays as power gated modes have to be safely entered and exited. The possible amount of leakage power saving in such low power mode and the energy dissipation to enter and exit such mode introduces some architectural trade-offs. Shutting down the blocks can be accomplished either by software or hardware. Driver software can schedule the power down operations. Hardware timers can be utilized. A dedicated power management controller is the other option. An externally switched power supply is very basic form of power gating to achieve long term leakage power reduction. To shutoff the block for small interval of time internal power gating is suitable. CMOS switches that provide power to the circuitry are controlled by power gating controllers. Output of the power gated block discharge slowly. Hence output voltage levels spend more time

in threshold voltage level. This can lead to larger short circuit current. Power gating uses low-leakage PMOS transistors as header switches to shut off power supplies to parts of a design in standby or sleep mode. NMOS footer switches can also be used as sleep transistors. Inserting the sleep transistors splits the chip's power network into a permanent power network connected to the power supply and a virtual power network that drives the cells and can be turned off. The quality of this complex power network is critical to the success of a power-gating design. Two of the most critical parameters are the IR-drop and the penalties in silicon area and routing resources. Power gating can be implemented using cell- or cluster-based (or fine grain) approaches or a distributed coarse-grained approach. Power-gating parameters Power gating implementation has additional considerations than the normal timing closure implementation. The following parameters need to be considered and their values carefully chosen for a successful implementation of this methodology [1] [2]. Power gate size: The power gate size must be selected to handle the amount of switching current at any given time. The gate must be bigger such that there is no measurable voltage (IR) drop due to the gate. Generally we use 3X the switching capacitance for the gate size as a rule of thumb. Designers can also choose between header (P-MOS) or footer (N-MOS) gate. Usually footer gates tend to be smaller in area for the same switching current. Dynamic power analysis tools can accurately measure the switching current and also predict the size for the power gate. Gate control slew rate: In power gating, this is an important parameter that determines the power gating efficiency. When the slew rate is large, it takes more time to switch off and switch-on the circuit and hence can affect the power gating efficiency. Slew rate is controlled through buffering the gate control signal. Simultaneous switching capacitance: This important constraint refers to the amount of circuit that can be switched simultaneously without affecting the power network integrity. If a large amount of the circuit is switched simultaneously, the resulting "rush current" can compromise the power network integrity. The circuit needs to be switched in stages in order to prevent this. Power gate leakage: Since power gates are made of active transistors, leakage is an important consideration to maximize power savings.

Fine-grain power gating Adding a sleep transistor to every cell that is to be turned off imposes a large area penalty, and individually gating the power of every cluster of cells creates timing issues introduced by inter-cluster voltage variation that are difficult to resolve. Fine-grain power gating encapsulates the switching transistor as a part of the standard cell logic. Switching transistors are designed by either library IP vendor or standard cell designer. Usually these cell designs conform to the normal standard cell rules and can easily be handled by EDA tools for implementation. The size of the gate control is designed with the worst case consideration that this circuit will switch during every clock cycle resulting in a huge area impact. Some of the recent designs implement the fine-grain power gating selectively, but only for the low Vt cells. If the technology allows multiple Vt libraries, the use of low Vt devices is minimum in the design (20%), so that the area impact can be reduced. When using power gates on the low Vt cells the output must be isolated if the next stage is a high Vt cell. Otherwise it can cause the neighboring high Vt cell to have leakage when output goes to an unknown state due to power gating. Gate control slew rate constraint is achieved by having a buffer distribution tree for the control signals. The buffers must be chosen from a set of always on buffers (buffers without the gate control signal) designed with high Vt cells. The inherent difference between when a cell switches off with respect to another, minimizes the rush current during switch-on and switch-off. Usually the gating transistor is designed as a high vt device. Coarse-grain power gating offers further flexibility by optimizing the power gating cells where there is low switching activity. Leakage optimization has to be done at the coarse grain level, swapping the low leakage cell for the high leakage one. Fine-grain power gating is an elegant methodology resulting in up to 10X leakage reduction. This type of power reduction makes it an appealing technique if the power reduction requirement is not satisfied by multiple Vt optimization alone. Coarse-grain power gating The coarse-grained approach implements the grid style sleep transistors which drives cells locally through shared virtual power networks. This approach is less sensitive to PVT variation, introduces less IR-drop variation, and imposes a smaller area overhead than the cell- or cluster-based implementations. In coarse-grain power gating, the power-gating transistor is a part of the power distribution network rather than the standard cell.

There are two ways of implementing a coarse-grain structure: 1) Ring-based 2) column-based Ring-based methodology: The power gates are placed around the perimeter of the module that is being switched-off as a ring. Special corner cells are used to turn the power signals around the corners. Column-based methodology: The power gates are inserted within the module with the cells abutted to each other in the form of columns. The global power is the higher layers of metal, while the switched power is in the lower layers. Gate sizing depends on the overall switching current of the module at any given time. Since only a fraction of circuits switch at any point of time, power gate sizes are smaller as compared to the fine-grain switches. Dynamic power simulation using worst case vectors can determine the worst case switching for the module and hence the size. IR drop can also be factored into the analysis. Simultaneous switching capacitance is a major consideration in coarse-grain power gating implementation. In order to limit simultaneous switching daisy chaining the gate control buffers, special counters are used to selectively turn on blocks of switches. Isolation Cells Isolation cells are used to prevent short circuit current. As the name indicates these cells isolate power gated block from the normally on block. Isolation cells are specially designed for low short circuit current when input is at threshold voltage level. Isolation control signals are provided by power gating controller. Isolation of the signals of a switchable module is essential to preserve design integrity. Usually a simple OR or AND logic can function as an output isolation device. Multiple state retention schemes are available in practice to preserve the state before a module shuts down. The simplest technique is to scan out the register values into a memory before shutting down a module. When the module wakes up, the values are scanned back from the memory.

Retention Registers When power gating is used, the system needs some form of state retention, such as scanning out data to a RAM, then scanning it back in when the system is reawakened. For critical applications, the memory states must be maintained within the cell, a condition that requires a retention flop to store bits in a table. That makes it possible to restore the bits very quickly during wakeup. Retention registers are special low leakage flip-flops used to hold the data of main register of the power gated block. Thus internal state of the block during power down mode can be retained and loaded back to it when the block is reactivated. Retention registers are always powered up. The retention strategy is design dependent. During the power gating data can be retained and transferred back to block when power gating is withdrawn. Power gating

controller controls the retention mechanism such as when to save the current contents of the power gating block and when to restore it back. References [1] Practical Power Network Synthesis For Power-Gating Designs, http://www.eetimes.com/news/design/showArticle.jhtml?articleID=199903073&pgno=1, 11/01/2008 [2] Anand Iyer, Demystify power gating and stop leakage cold, Cadence Design Systems, Inc. http://www.powermanagementdesignline.com/howto/181500691;jsessionid=NNNDVN1KQOFC UQSNDLPCKHSCJUNN2JVN?pgno=1, 11/01/2008 [3] De-Shiuan Chiou, Shih-Hsin Chen, Chingwei Yeh, "Timing driven power gating", Proceedings of the 43rd annual conference on Design automation,ACM Special Interest Group on Design Automation, pp.121 - 124, 2006

You might also like: Power Gating Clock Gating Low Power Design Techniques Leakage Power Trends LinkWithin Tags: Low Power Techniques, Power Gating Reactions: 3 comments: padamAugust 19, 2010 1:27 PM Good artice to begin with before jumping into power gating. Doesnt get too much into the detail but explains the basics! ReplyDelete AnonymousJune 13, 2011 12:06 AM nice one, thank u... ReplyDelete AnonymousJanuary 8, 2012 3:49 PM add something ur own rather than copy pest from wikipedia... ReplyDelete Add comment Load more... Your Comments... Links to this post Create a Link Newer Post Older Post Home Subscribe to: Post Comments (Atom) Search This Blog powered by Popular Posts Clock Gating Clock tree consume more than 50 % of dynamic power. The components of this power are: 1) Power consumed by combinatorial log... Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis The major design challenges of ASIC design consist of microscopic issues and macroscopic issues [1]. The microscopic issues are ultra-high s...

Backend (Physical Design) Interview Questions and Answers Below are the sequence of questions asked for a physical design engineer. In which field are you interested? Answer to this question... Embedded System for Automatic Washing Machine using Microchip PIC18F Series Microcontroller The design uses the PIC18F series microcontroller. All the control functionalities of the system are built around this. Upgradeability is th... Power Planning There are two types of power planning and management. They are core cell power management and I/O cell power management . In former one VDD... Read More... DSP (22) Low Power Techniques (16) Verification (16) MATLAB (15) Timing Analysis (14) ASIC (12) Static Timing Analysis (STA) (11) Verilog (11) DSP filters (10) FPGA (10) Physical Design (10) Digital design (9) HDL (9) Synthesis (9) Verilog HDL (9) CMOS (8) Asynchronous FIFO (7) 3-D ICs (6) Basic gates using MUX (6) Digital filters (6) PIC Microcontroller (6) low power (6) PIC 16F877A (5) interview (5) Leakage Power (4) VLSI (4) Design For Test-DFT (3) Multi Vt (3) Power Planning (3) Reconfigurable Computing (3) Clock Tree Synthesis (CTS) (2) Design For Test (DFT) (2) Floorplanning (2) Libraries (2) Placement (2) SPICE (2) SRAM cell design (2) SoC Design (2) SoC Integration (2) Synopsys (2) System on Chip (2) Transition delay (2) layout (2) 7 Segment Display (1) AMBA AHB (1) AMBA APB (1) AMBA AXI (1)

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