Elementary Logic Gates

Name Symbol Truth Table Logic Equation

C. E. Stroud

Inverter (NOT Gate) A Z

AND Gate A B
A B 0 1 0 1 Z 0 0 0 1

OR Gate Z A B
A 0 0 1 1 B 0 1 0 1

Z
Z 0 1 1 1

A 0 1

Z 1 0

0 0 1 1

Z = A = A

Z = A B = AB
Combinational Logic Design (1/06)

Z=A+B
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Other Elementary Logic Gates

NAND Gate
A B (NOT AND) Z

Name Symbol Truth Table

NOR Gate
A B (NOT OR) Z

A B
A 0 0 1 1 B 0 1 0 1 Z 1 1 1 0

A B
A 0 0 1 1 B 0 1 0 1 1 0 0 0

Z
Z

Z = (A B) = AB Logic Equation Z = (A + B) = A+B

C. E. Stroud Combinational Logic Design (1/06) 2

Using Truth Tables to Prove Theorems

DeMorgans Theorems
T8a: (X+Y) = XY
a NOR gate is equivalent to an AND gate with inverted inputs X 0 0 1 1 Y 0 1 0 1 Z 1 0 0 0

T8b: (XY) = X+Y

a NAND gate is equivalent to an OR gate with inverted inputs X 0 0 1 1 Y 0 1 0 1 Z 1 1 1 0

X Y NOR X Y
C. E. Stroud

Y Z NOR

X Y

NAND X alternate Y logic symbols

Y Z NAND
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Combinational Logic Design (1/06)

Other Logic Gates

Name Symbol Truth Table Buffer A Z Exclusive-OR Gate Exclusive-NOR Gate aka XOR Gate aka XNOR or NXOR Gate A A Z Z B B
A A 0 1 Z 0 1 0 0 1 1 B 0 1 0 1 Z 0 1 1 0 A 0 0 1 1 B 0 1 0 1 Z 1 0 0 1

Logic Z =A Equation
C. E. Stroud

Z = AB = AB + AB Z = AB = A B + AB also denoted Z = A B
Combinational Logic Design (1/06) 4

Interesting Properties of Exclusive-OR

Controlled inverter
X0=X X1=X

XOR with one input inverted = XNOR

XY=XY=(XY)

XNOR with one input inverted = XOR

(XY)=(XY)=XY

Constant output
XX=0 XX=1
C. E. Stroud Combinational Logic Design (1/06) 5

Exclusive-OR Implementations
Z=AB+AB XOR & XNOR not considered elementary logic gates by many designers B A 4 gates
(AB) (B(AB)) B Z=((A(AB))(B(AB))) (A(AB))

AB

5 gates
B AB (A+B)

A Z

3 gates

= A AB B AB = A AB + B AB = A(A+B) + B(A+B) = AA+AB+AB+BB=AB+AB

C. E. Stroud

AB B Z=((A+B)+AB) = A+B+AB = (A+B)AB = (A+B)(A+B) = AA+AB+AB+BB = 0+AB+AB+0 = AB+AB

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Combinational Logic Design (1/06)

Functionally Complete Set of Gates

If any digital circuit can be built from a set of gates, that set is said to be functionally complete Functionally complete sets of gates:
AND, OR, & NOT NAND NOR Multiplexers

To show a set of gates is functionally complete, we must show that you can construct AND, OR and NOT functions
C. E. Stroud Combinational Logic Design (1/06) 7

Functionally Complete Set of Gates

A Z=A

The NAND gate is functionally complete

We can build any digital logic circuit out of all NAND gates

A B A B

Same holds true for the NOR Z=AB gate and the multiplexer The XOR & XNOR are not functionally complete
Z=A+B using DeMorgans Theorem

C. E. Stroud

Combinational Logic Design (1/06)

Gate-level Representations
SOP expressions
AND-OR
With inverters for complemented literals Z=ABC+ABC+ABC+ABC

A B C 8 gates A B C
9

aka 2-level AND-OR logic representation

POS expressions
OR-AND
With inverters for complemented literals Z=(A+B+C)(A+B+C) (A+B+C)(A+B+C)

aka 2-level OR-AND logic representation

C. E. Stroud

Combinational Logic Design (1/06)

Gate Level Representation

from Boolean equation Z = (((AB)C)+D)= ((AB)C)+D
A A B C D D
10

(AB) ((AB)C) Z

C. E. Stroud

Combinational Logic Design (1/06)

Circuit Analysis
Going from gate-level to
truth table
Apply 0s & 1s to inputs to get outputs
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Z 0 1 1 0 0 1 0 1

Boolean equation
Move equations to output Z=(A+B)C+ABC=AC+BC+ABC A B C
B A C
C. E. Stroud

A+B

(A+B)C

Z
ABC
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Combinational Logic Design (1/06)

Circuit Analysis
We can implement different circuits for same logic function that are functionally equivalent (produce the correct output response for all input values) Which implementation is the best?
Depends on design goals and criteria

Area analysis
Number of gates, G (most commonly used) Number of gate inputs and outputs, GIO (more accurate)
Bigger gates take up more area

Performance analysis (worst case path from inputs to outputs)

Number of gates in worst case path from input to output, Gdel More accurate delay measurement per gate
Propagation delay = intrinsic (internal) delay + extrinsic (external) delay Relative prop delay, Pdel = # inputs to gate (intrinsic) + # loads (extrinsic)
C. E. Stroud Combinational Logic Design (1/06) 12

Circuit Analysis Example

From previous example: Z=(A+B)C+ABC
# gates: G = 7 # gate I/O: GIO = 19 Gate delay: Gdel = 4
worst case path: BZ
2A 2B 2C B A+B 1+1 2+1 A 1+1 C 1+1 (A+B)C

2+1 3+1

2+0 ABC

Prop delay: Pdel = 12

worst case path: BZ

C. E. Stroud

Combinational Logic Design (1/06)

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Circuit Optimization
Obviously we want smallest, fastest circuit Some Basic Goals:
Minimizing # product terms minimizes # of AND gates and # inputs to OR gate in a 2-level SOP (AND-OR) representation Minimizing # literals in each product term minimizes # inputs to its AND gate

We can use postulates & theorems, but

It would be nice to find a more reliable procedure
C. E. Stroud Combinational Logic Design (1/06) 14