Lab Manual FPGA Based System Design

Submitted To Submitted By Reg. No Class : : : :

Engr. Hassan Murtaza Muhammad Imran Anwar

504-FET/BSEE/F06 BSEE4/7-A

Department of Electronic Engineering Faculty of Engineering and Technology International Islamic University, Islamabad

LAB 1 Introduction to Xilinx Behavioral Simulation(Mux 2:1)

In this experiment we make the mux2:1 and see behavioral simulation results on Xilinx ISE simulator.

Code
module mux2to1(i0, i1, sel, out); input i0; input i1; input sel; output out; reg out; always @ (i0 or i1 or sel) begin if(sel) out=i1; else out=i0; end endmodule

RTL Schematic

Xilinx ISE Simulator Generate Expected Simulation Results

Simulate Behavioral Model

LAB 2 Post Route Simulation Using ISE Simulator(Mux4:1)

In this experiment we make the mux4:1 and see post route simulation results on Xilinx ISE simulator.

Code
module mux4to1(i0, i1, i2, i3, s1, s0, out); input i0; input i1; input i2; input i3; input s1; input s0; output out; assign out = (~s1 & ~s0 & i0)| (~s1 & s0 & i1) | (s1 & ~s0 & i2) | (s1 & s0 & i3) ; endmodule

RTL Schematic

Post Route Simulation

LAB 3 Post Route Simulation Using Model Sim(Mux2:1)

In this experiment we make a mux2:1 and see post route simulation results on Modelsim.

Code
module mux4to1(i0, i1, i2, i3, s1, s0, out); input i0; input i1; input i2; input i3; input s1; input s0; output out; assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ; endmodule

RTL Schematic

LAB 4 Implementation of Combinational circuit on Spartan 2 FPGA Board(Mux 2:1)

In this experiment we make a mux2:1 and implement it on Spartan 2 FPGA Board.

Code
module mux2to1(i0, i1, sel, out); input i0; input i1; input sel; output out; assign out = sel ? i1 : i0 ; endmodule

RTL

Implementation on Spartan 2 Board

In user constraints we assign the pin package as follow. NET "i0" LOC = "M10" ; NET "i1" LOC = "R11" ; NET "out" LOC = "N14" ; NET "sel" LOC = "P11" ; We implement it on XSA-200 Board and use its S0 of seven segment for showing result, pin 1 of dip switch as select and pin 2 and 3 of dip switch as i0 and i1.

LAB 5 Implementation of Sequential circuit and CLK handling in FPGA

In this experiment we convert 50M Hz clk to 1 Hz and use it for 4 bit hexadecimal counter.

Code
TOP MODULE
module top(out,clk,rst); wire dividedClk,bufferedCLK; wire [3:0]counterOut; input clk,rst; output [6:0]out; BUFG bg(.O(bufferedCLK),.I(dividedClk)); counter28b clkDivider (.out(dividedClk),.clk(clk),.rst(rst));

counter4b counter(.out(counterOut),.clk(bufferedCLK),.rst(rst)); decoder dec (.out(out),.in(counterOut)); endmodule

CLOCK DIVIDER MODULE

module counter28b(out,clk,rst); input clk; output out; reg [27:0] counter; reg out; input rst; always@(posedge clk or negedge rst) begin if (!rst) begin out <= 0; counter <=0; end else if(counter == 28'h17D783F) begin out <= !out; counter <= 0; end else counter <= counter + 1; end

COUNTER MODULE
module counter4b(out,clk,rst); output [3:0] out; input clk,rst; reg [3:0] out; always@(posedge clk or negedge rst) begin if (!rst) out <= 0; else if(out == 4'hF) out <= 0; else out <= out + 1; end endmodule

DECODER MODULE (ROM)

module decoder(out,in); output [6:0]out; input [3:0] in; reg [6:0] out; always@(in) begin case(in) 4'h0: out <= 7'b111_0111; 4'h1: out <= 7'b001_0010; 4'h2: out <= 7'b101_1101; 4'h3: out <= 7'b101_1011; 4'h4: out <= 7'b011_1010; 4'h5: out <= 7'b110_1011; 4'h6: out <= 7'b110_1111; 4'h7: out <= 7'b101_0010; 4'h8: out <= 7'b111_1111; 4'h9: out <= 7'b111_1010; 4'hA: out <= 7'b111_1110; 4'hB: out <= 7'b111_1111; 4'hC: out <= 7'b110_0101; 4'hD: out <= 7'b111_0111; 4'hE: out <= 7'b110_1101; 4'hF: out <= 7'b110_1100; default: out <= 7'bxxx_xxxx; endcase end

RTL SCHEMATIC

Implementation on Spartan 2 Board

In user constraints we assign the pin package as follow. NET "clk" LOC = "R8" ; NET "out[0]" LOC = "N14" ; NET "out[1]" LOC = "D14" ; NET "out[2]" LOC = "N16" ; NET "out[3]" LOC = "M16" ; NET "out[4]" LOC = "F15" ; NET "out[5]" LOC = "J16" ; NET "out[6]" LOC = "G16" ; NET "rst" LOC = "P11" ; We implement it on XSA-200 Board and use its seven segment for displaying digits and characters, pin 1 of dip switch as reset and R8 pin of FPGA for clock..

LAB 6 Implement a circuit on FPGA using a IP Core Generator

In this Experiment we use the adder subtractor V7.0 core and make a 4 bit adder, which is displaying result in hexadecimal on seven segment display.

Code
Coregen Module
module coregen_mod(a, b, out); input [3:0] a; input [3:0] b; output [6:0] out; wire [3:0] sum; coregen add(.A(a),.B(b),.S(sum)); decoder d1(.out(out),.in(sum)); endmodule

Decoder
module decoder(out,in); output [6:0]out; input [3:0] in; reg [6:0] out; always@(in) begin case(in) 4'h0: out <= 7'b111_0111; 4'h1: out <= 7'b001_0010; 4'h2: out <= 7'b101_1101; 4'h3: out <= 7'b101_1011; 4'h4: out <= 7'b011_1010; 4'h5: out <= 7'b110_1011; 4'h6: out <= 7'b110_1111; 4'h7: out <= 7'b101_0010; 4'h8: out <= 7'b111_1111; 4'h9: out <= 7'b111_1010; 4'hA: out <= 7'b111_1110; 4'hB: out <= 7'b111_1111; 4'hC: out <= 7'b110_0101; 4'hD: out <= 7'b111_0111; 4'hE: out <= 7'b110_1101; 4'hF: out <= 7'b110_1100; default: out <= 7'bxxx_xxxx; endcase end endmodule

Adder Subtractor V7.0 (IP coregent and architecture wizard)

RTL

Implementation on Spartan 2 Board

In user constraints we assign the pin package as follow. NET "a[0]" LOC = "A5" ; NET "a[1]" LOC = "A9" ; NET "a[2]" LOC = "B9" ; NET "a[3]" LOC = "T7" ; NET "b[0]" LOC = "T9" ; NET "b[1]" LOC = "R9" ; NET "b[2]" LOC = "P9" ; NET "b[3]" LOC = "F14" ; NET "out[0]" LOC = "P7" ; NET "out[1]" LOC = "N7" ; NET "out[2]" LOC = "R7" ; NET "out[3]" LOC = "P8" ;

NET "out[4]" LOC = "R6" ; NET "out[5]" LOC = "T14" ; NET "out[6]" LOC = "M7" ; We implement it on XStend Board V3.0 and use seven segment 2 for displaying digits and characters. 4 right sides switches is used as A0,A1,A2 and A3 and 4 left switches is used as B0,B1,B2 and B3.

LAB 7 Implementation of Sequential circuit on Virtex 2 Pro Board

In this experiment we convert 50M Hz clk to 1 M Hz and use it for 4 bit hexadecimal counter and display the output on four LEDs.

Code
TOP MODULE
module top(counterOut,clk,rst); wire dividedClk,bufferedCLK; output [3:0]counterOut; input clk,rst; BUFG bg(.O(bufferedCLK),.I(dividedClk)); counter28b clkDivider (.out(dividedClk),.clk(clk),.rst(rst)); counter4b counter(.out(counterOut),.clk(bufferedCLK),.rst(rst)); endmodule

CLK DIVIDER MODULE

module counter28b(out,clk,rst); input clk; output out; reg [27:0] counter; reg out; input rst; always@(posedge clk or negedge rst) begin if (!rst) begin out <= 0; counter <=0; end else if(counter == 28'h17D783F) begin out <= !out; counter <= 0; end else counter <= counter + 1; end endmodule

COUNTER MODULE
module counter4b(out,clk,rst); output [3:0] out; input clk,rst; reg [3:0] out; always@(posedge clk or negedge rst) begin if (!rst) out <= 0; else if(out == 4'hF) out <= 0; else out <= out + 1; end endmodule

RTL

Implementation on Virtex 2 Pro Board

In user constraints we assign the pin package as follow. NET "clk" LOC = "AJ15" ; NET "counterOut[0]" LOC = "AC4" NET "counterOut[1]" LOC = "AC3" NET "counterOut[2]" LOC = "AA6" NET "counterOut[3]" LOC = "AA5" NET "rst" LOC = "AC11" ;

; ; ; ;

We implement it on Virtex 2 Pro Board and use four LEDs for displaying results.

LAB 8
Keyboard Interfacing with FPGA
Top Module
module top_keyboard(out,kbrd_clk,kbrd_data,rst); input kbrd_clk,kbrd_data,rst; output [3:0]out; wire [7:0] data; deserialize des(.in(kbrd_data),.clk(kbrd_clk),.out(data),.rst(rst)); decoder dec(.out(out),.in(data)); endmodule

Deserialize Module
module deserialize(in,clk,out,ready,rst); input in,clk,rst; output [7:0] out; output ready; reg start_bit,r0,r1,r2,r3,r4,r5,r6,r7,parity,stop; reg [3:0]counter; reg ready; reg [7:0] out; always@(negedge clk or negedge rst) begin if(!rst) begin start_bit <= 0; r0<= 0; r1<= 0; r2<= 0; r3<= 0; r4<= 0; r5<= 0; r6<= 0; r7<= 0; parity<= 0; stop<= 0; end else begin

stop <= in; parity <= stop; r7 <= parity; r6 <= r7; r5 <= r6; r4 <= r5; r3 <= r4; r2 <= r3; r1 <= r2; r0 <= r1; //start_bit <= r0; end end always@(negedge clk or negedge rst) begin if(!rst) begin counter <= 0; ready <= 0; end else if(counter == 4'd10) begin counter <= 0; ready <= 1; end else begin counter <= counter + 1; ready <= 0; end end always@(posedge clk) begin if(ready) out <= {r7,r6,r5,r4,r3,r2,r1,r0}; else out <= out; end endmodule

Decoder Module
module decoder(out,in); output [3:0] out; input [7:0]in; reg [3:0] out; always@(in) begin case(in) 8'h16: out <= 4'd1; 8'h1E: out <= 4'd2; 8'h26: out <= 4'd3; 8'h25: out <= 4'd4; 8'h2E: out <= 4'd5;

8'h36: out <= 4'd6; 8'h3D: out <= 4'd7; 8'h3E: out <= 4'd8; 8'h46: out <= 4'd9; 8'h45: out <= 4'd0; default : out<= 4'd0; endcase end endmodule

RTL

Implementation on Virtex 2 Pro Board

NET "kbrd_clk" LOC = "AG2" ; NET "kbrd_data" LOC = "AG1" ; NET "out[0]" LOC = "AC4" ; NET "out[1]" LOC = "AC3" ; NET "out[2]" LOC = "AA6" ; NET "out[3]" LOC = "AA5" ; NET "rst" LOC = "AC11" ;

We implement it on Virtex 2 Pro Board and use four LEDs for displaying results.