HowdoesScanWork?

PreparedbyMahmutYilmaz

ScanChainOperationforStuckatTest
DesignUnderTest(DUT) ScanOut

CombinationalLogic

CombinationalLogic

ScanEnable ScanIn Hereisanexampledesignundertest(DUT).Ihaveshownasinglescanchain(inredcolor)inthecircuit,withScanInandScanOutports. AssumethatallscanflipflopsarecontrolledbytheScanEnablesignal.

CombinationalLogic

PrimaryInputs(PI)

PrimaryOutputs(PO)

CombinationalLogic

HowdoesScanWork?

PreparedbyMahmutYilmaz

DesignUnderTest(DUT)

ScanOut

X CombinationalLogic CombinationalLogic PrimaryInputs(PI)

X CombinationalLogic

X CombinationalLogic PrimaryOutputs(PO)

ScanEnable=1 ScanIn 100101011 Thefirstthingweshoulddoistoputthescanflipflopsintoscanmode.WedothisbyusingtheScanEnablesignal.Inthiscase,forcingScan Enableto1enablesthescanmode. Notethatinitiallyallthescanflopsatunknownstate(X).Forindustrialcircuits,therearearchitecturalwaystoinitializeallflipflopstoknown statesifneeded.However,forthisparticularcase,assumethatallscanflopswereinitiallyatunknownstateX. Wewanttoscaninthefollowingvector:100101011

HowdoesScanWork?

PreparedbyMahmutYilmaz

DesignUnderTest(DUT)

ScanOut

1 CombinationalLogic CombinationalLogic PrimaryInputs(PI)

X CombinationalLogic

X CombinationalLogic PrimaryOutputs(PO)

ScanEnable=1 ScanIn 100101 Andwestartscanninginthetestvectorwewanttoapply.Inthefigureabove,youseethatthefirst3bitsarescannedin.Weshiftinasinglebit ateachclockcycle.Usually,thescanshiftfrequencyisveryslow,muchlowerthanthefunctionalfrequencyofthecircuit.Thisfrequencyis currentlyabout100MHzformostASICcircuits.AMDuses400MHzshiftfrequency,whichisaprettyhighvalueforthatpurpose.Ofcourse,the higherthetestfrequency,theshorterthetesttime.

HowdoesScanWork?

PreparedbyMahmutYilmaz

DesignUnderTest(DUT)

ScanOut

0 CombinationalLogic CombinationalLogic PrimaryInputs(PI)

1 CombinationalLogic

1 CombinationalLogic PrimaryOutputs(PO)

ScanEnable=0 ScanIn Atthispoint,wehaveshiftedinthecompletetestvector'100101011'.Wearedonewithshiftingin.WewilldisablescanmodebyforcingScan Enableto0. Notethattheshiftedintestvectoriscurrentlyappliedtothecombinationallogicpiecesthataredrivenbyscanflipflops.Itmeansthat2nd, 3rd,and4thcombinationallogicblocksarealreadyforcedtestinputs.

HowdoesScanWork?

PreparedbyMahmutYilmaz

DesignUnderTest(DUT) 0 1 CombinationalLogic 0 PrimaryInputs(PI) 0 0 1 0 0 ScanEnable=0 ScanIn 0 0 CombinationalLogic 0 1 CombinationalLogic 1 1 CombinationalLogic 0

ScanOut

1 0 1 1 1

PrimaryOutputs(PO)

Thenextstepistoforceprimaryinput(PI)valuesandmeasuretheprimaryoutput(PO)values:force_PIandmeasure_PO. Notethatfromthepreviousstep,theshiftedintestvectorwasalreadyappliedtothecombinationallogicpiecesthataredrivenbyscanflip flops.Itmeansthat2nd,3rd,and4thcombinationallogicblockswerealreadyforcedtestinputs.Now,thesecombinationallogicblockshave generatedtheiroutputs. SinceweforcedvaluestoPI,the1stcombinationalblockalsohasitsoutputsready.Furthermore,theoutputsofthe4thcombinationalblockcan nowbeobservedfromPOs.Wewillgettheoutputvaluesofcombinationalblock4bymeasuringPOs. Fortherestofthecombinationalblocks(1,2,and3),weneedtopushtheoutputvaluesintoscanflipflopsandthenshiftthesevaluesout. 5

HowdoesScanWork?

PreparedbyMahmutYilmaz

DesignUnderTest(DUT) 0 1 CombinationalLogic 0 PrimaryInputs(PI) 0 0 1 0 0 ScanEnable=0 ScanIn 0 0 CombinationalLogic 0 0 CombinationalLogic 1 1 CombinationalLogic 0

ScanOut

1 0 1 1 1

PrimaryOutputs(PO)

Inordertopushtheoutputvaluesofcombinationalblocks1,2,and3intoscanflipflops,wehavetotogglethesystemclock.Oncewetogglethe systemclock,allDflipflops(scanflipflops)willcapturethevaluesattheirDinput. Inthefigureabove,thecaptureeventisshown.

HowdoesScanWork?

PreparedbyMahmutYilmaz

DesignUnderTest(DUT)

ScanOut

0 CombinationalLogic CombinationalLogic PrimaryInputs(PI)

0 CombinationalLogic

1 CombinationalLogic PrimaryOutputs(PO)

ScanEnable=1 ScanIn 111100111 Now,wearereadytoshiftoutthecapturedcombinationallogicresponses.However,whiledoingthat,wewillalsoshiftinthenexttestvector. Thenexttestvectoris'111100111'. NotethatwehavesetScanEnablesignalbackto1toenableshifting.

HowdoesScanWork?

PreparedbyMahmutYilmaz

DesignUnderTest(DUT)

ScanOut 0111

1 CombinationalLogic CombinationalLogic PrimaryInputs(PI)

1 CombinationalLogic

1 CombinationalLogic PrimaryOutputs(PO)

ScanEnable=1 ScanIn 11110 Hereisasnapshotoftheshiftoperation.Asyoucansee,wehaveshiftedout4bitsoftheprevioustestresponse,andatthesametimeshifted in4bitsofthenewtestvectorinput.Thenewtestvectorbitsareshowninboldredinthefigureabove.

HowdoesScanWork?

PreparedbyMahmutYilmaz

DesignUnderTest(DUT)

ScanOut 011000111

1 CombinationalLogic CombinationalLogic PrimaryInputs(PI)

1 CombinationalLogic

1 CombinationalLogic PrimaryOutputs(PO)

ScanEnable=1 ScanIn Atthispoint,wehavecompletelyscannedout(shiftedout)thetestresponsefortheprevioustestvector,andalsoscannedin(shiftedin)the newtestvectorinput. Theprocesscontinuesinthiswayuntilallthetestvectorsareapplied. Note: On page 5, I mentioned force_PI and measure_PO. Actually, for industrial circuits, force_PI and measure_PO is not done. This is because primary inputs and outputs are connected to very slow pads, and these pads are not tested by structural test. You may realize that in this case the 1st and 4th combinational blocks cannot be tested: 1st block cannot be tested because we cannot apply inputs to it (force_PI). 4th block cannot be tested because we cannot check its output (measure_PO). This is usually not a problem because the circuits are surrounded by wrapper scan flipflops. This means that there is actually no logic before the first level of scan flipflops or after the last level of scan flipflops. So,thecompleteDUTiscoveredbyscanflipflops.

HowdoesScanWork?

PreparedbyMahmutYilmaz

ScanChainOperationforDelayTest
Scanoperationfordelaytestisverysimilartostuckattest.Themaindifferenceisthatdelaytestneedstwoinputsinsteadofone.Thefirstinput isalwaysthescannedinvector.Thesecondinputcanbegeneratedintwodifferentways.Eachwayhasitsownname:(1)LaunchonCapture (LOC)orbroadsidedelaytest,(2)Launchonshift(LOS)orskewedloaddelaytest.NowIwillshowhoweachofthesemethodsworks...

(1)LaunchonCapture(Broadside)
DesignUnderTest(DUT) 0 1 CombinationalLogic 0 PrimaryInputs(PI) 0 0 1 0 0 ScanEnable=0 ScanIn This is the same figure that is shown on page 5. Assume that all the process until this point is the same as stuckat test. You scannedin the test vector, forced the PIs, and they created some output responses for combinational blocks. This is step 1. You have already applied your first vector for the delay test. Guess what is the second vector? The second vector will the output responses of the combinational blocks. Each block willgeneratethe2ndtestvectorforthenextstage.Sincethereisnostagebeforethe1stone,youneedapplyforce_PIonemoretime. 0 0 CombinationalLogic 0 1 CombinationalLogic 1 1 CombinationalLogic PrimaryOutputs(PO) ScanOut

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HowdoesScanWork?

PreparedbyMahmutYilmaz

DesignUnderTest(DUT) 1 0 1 1 CombinationalLogic 1 0 PrimaryInputs(PI) 0 0 1 0 1 1 0 0 1 0 ScanEnable=0 ScanIn 0 0 CombinationalLogic 0 1 CombinationalLogic 1 1 CombinationalLogic 0

ScanOut

1 0 1 1 1

PrimaryOutputs(PO)

Of course, in order to push the output responses of combinational blocks into scan flipflops, we need to toggle system clock. Once we toggle thesystemclock(andapplythesecondPIforce),wewillgeneratethesecondtestvectorforthedelaytest,andeachcombinationalcircuitinput will see an input state transition. The transition on scan flipflop outputs (which are inputs to the next stage combinational block) will be as follows(startingfromtheclosesttoscaninflop):100101110>010010111 Thesecond inputvector willgenerate outputresponsesjustlike thefirstone. And,you needto capture theseresponsesjustlike wedidbefore, by toggling the system clock. However, now there is a difference: You have to toggle the system clock at the real operating frequency: This means that the period between the first clock toggle and second clock toggle should be equal to functional clock period. In this way, you will capturethedelaytestresponsesatthefunctionalfrequency.

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HowdoesScanWork?

PreparedbyMahmutYilmaz

HereisatimingdiagramoftheLOCprocess(source:MentorGraphicsScanandATPGProcessGuide,August2006):

As you can see above, we shift the test vector using a slow clock frequency. Then, we set scan enable to 0 and disable scan mode. In the next step, we toggle the clock first time to launch a transition in combinational blocks. After that, we toggle the clock again (at the functional frequency) to capture the final responses of the combinational blocks. The launch & capture events happen at functional frequency. Finally, we shiftedoutthecapturedresponsesusingtheslowclockfrequency.

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HowdoesScanWork?

PreparedbyMahmutYilmaz

(2)LaunchonShift(SkewedLoad)
DesignUnderTest(DUT) 0 1 CombinationalLogic 0 PrimaryInputs(PI) 0 0 1 0 0 ScanEnable=1 ScanIn This is the same figure that is shown on page 5 and 10. So, we start as usual: Assume that all the process until this point is the same as stuckat test. You scannedin the test vector, forced the PIs, and they created some output responses for combinational blocks. For LOS, we don't care about these initial output responses. This is step 1. You have already applied your first vector for the delay test. Since there is no stage before the 1st one, you need apply force_PI one more time. Note that Scan Enable signal is still at active value 1. This is because we have not yet done withshifting.Weneedtoshiftonemoretimetocreatethesecondtestvectorforthedelaytest. 0 0 CombinationalLogic 0 1 CombinationalLogic 1 1 CombinationalLogic PrimaryOutputs(PO) ScanOut

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 DesignUnderTest(DUT) 1 0 1 1 CombinationalLogic 1 0 PrimaryInputs(PI) 0 0 1 0 1 1 0 0 1 0 ScanEnable=1 ScanIn 0 0 0 CombinationalLogic

HowdoesScanWork?

PreparedbyMahmutYilmaz

ScanOut

1 CombinationalLogic

1 CombinationalLogic PrimaryOutputs(PO)

Notethatasmentionedinthepreviouspage,thefirstvectorofthedelaytestis(startingfromtheclosesttoscaninflop):100101110 Thesecondtestvectorisgeneratedbyshiftingonemoretime,andinsertingonemorebitfromScanIn,2ndvectoris:010010101 Justafteryoushiftthelastbit(andlaunchedatransitionbyapplyingthesecondvector),youhavetoforceScanEnableto0,andalsotogglethe system clock at the functional frequency. The last toggle of the system clock will capture the delaytest responses. Finally, you will scanout the responsesasusual.

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HowdoesScanWork?

PreparedbyMahmutYilmaz

HereisatimingdiagramoftheLOSprocess(source:MentorGraphicsScanandATPGProcessGuide,August2006):

As you can see above, weshift the test vector using a slow clock frequency until the last bit. The last shifted bit creates the Launch event. Then, before we toggle the system clock to capture responses, we set scan enable to 0 and disable scan mode. This has to happen very fast since Launch & Capture event happen at high frequency. In the next step, we toggle the clock again to capture the final responses of the combinationalblocks.Finally,weshiftedoutthecapturedresponsesusingtheslowclockfrequency. You can see that we need to have a very fast Scan Enable signal in order to use LOS. Scan Enable should be able to switch from 1 to 0 within a very short time. This is usually a difficult process because Scan Enable is not designed to operate at high frequencies. Due to this reason, many industrial designsuseLOC insteadofLOS.(Thereare somedesignsthat useLOS.ThereareworkaroundstofastScan Enablesignalrequirement, butIwillnotgointodetailsfornow.)

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