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Published in IET Power Electronics Received on 24th April 2012 Revised on 22nd September 2012 Accepted on 30th September 2012 doi: 10.1049/iet-pel.2012.0191

ISSN 1755-4535

Single-stage single-switch power factor correction converter based on discontinuous capacitor voltage mode buck and flyback converters
Alireza Ramezan Ghanbari, Ehsan Adib, Hosein Farzanehfard
Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran E-mail: a.ramezanghanbari@ec.iut.ac.ir

Abstract: A new single-switch, single-stage power factor correction (PFC) converter based on discontinuous capacitor voltage mode (DCVM) is presented in this study. The conventional single-stage PFC converters have high voltage across their bulk capacitor which imposes high voltage stress on the switch and also the bulk capacitor voltage stress increases at light load condition. The most important advantage of the proposed topology is that the voltage across the bulk capacitor is low and the input current is continuous. Furthermore, this topology does not have high voltage stress across the bulk capacitor at light loads. The proposed topology is derived from a DCVM buck converter integrated with a yback converter. The proposed PFC topology contains low number of passive components and employs only one switch, resulting in reduced complexity and cost. The presented simulation and experimental results of the proposed converter justify the theoretical analysis.

Introduction

In order to meet standards such as IEEE 519 [1] and IEC 61000-3-2 [2], power factor correction (PFC) converters are vastly applied in industry. PFC converter topology consists of two stages which require two independent power stages and controllers. The input stage is an ACDC input current shaper converter and the output stage is a DCDC converter. A bulk capacitor is applied between the stages as a low-frequency energy storage element to buffer the input power. The main disadvantage of this type of PFC is complicated topology and control, especially for low-power applications which results in increased size and weight. A single-stage topology combines two stages into one and usually requires only one switch and one simple controller. The main purpose of these single-stage PFC topologies is to provide the output load with high-quality output voltage regulation and simultaneously meet the international harmonics regulations [1, 2]. In recent years, many new PFC converters are presented [320]. A common topology to generate a single-stage converter is to combine a boost converter with a DCDC converter by sharing their switch [6]. The output voltage of the boost stage should be designed high enough to prevent any input AC current distortion. However, this causes high voltage across the bulk capacitor and consequently high voltage stress on the switch. Furthermore, usually single-stage PFC topologies suffer from high voltage stress across the bulk capacitor at the light loads [7, 8]. There are several papers on single-stage converters concentrating on reducing the high voltage across the bulk capacitor [912], but they increase complexity. In these papers, the optimal design and also circuit techniques to reduce the bulk
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capacitor voltage stress especially at light loads are discussed. In [13, 14], duality principle is used to design a single-stage single-switch (S4) PFC converter. As a result, the bulk capacitor is replaced with an inductor to buffer the input power and provide electrical isolation. This inductor is utilised as the yback transformer resulting in a large yback transformer which increases the converter volume and also the converter conduction losses. In [15], discontinuous inductor current mode (DICM) buck and yback converters are integrated, to reduce the bulk capacitor voltage stress. However, in this converter the input current is zero at zero voltage crossings. In this paper, a single-stage single-switches PFC converter is introduced by combining discontinuous capacitor voltage mode (DCVM) buck converter (which is dual form of DICM boost converter) and a yback converter. The proposed converter does not suffer from high voltage across its bulk capacitor even at light loads. Also, this converter is simple with low number of passive components. This paper is organised as follows. The proposed topology is introduced and the converter principles are explained in Section 2. Detailed converter operating modes are discussed in Section 3. The proposed PFC converter is analysed in Section 4. Design considerations are discussed in Section 5. In Section 6, the experimental results are presented. The conclusions drawn from this paper are presented in Section 7.

Principles of the proposed topology

Combining the two stages in single-stage PFC is possible only if the PFC stage has inherent PFC properties. This means that at constant duty cycle D and constant switching
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frequency fs, the input impedance of the PFC is basically resistive and constant. So, the input current of the converter with inherent PFC stage follows the form of the input voltage without requiring any converter control. DICM and DCVM are operating modes in which inherent PFC specications are obtained [16]. In DICM operation, the inductor current is reduced periodically to zero, and in DCVM operation the voltage across the capacitor is reduced periodically to zero. Thus, they do not store energy in a switching cycle and the input impedance can be considered as a constant resistance [17]. Single-stage PFC converters are developed by combing a DICM inherent PFC stage with a DCDC converter. This would create a high voltage across the bulk capacitor and consequently high voltage stress on the switch. In a PFC, based on a boost converter for the input stage, operating in DICM would have discontinuous input current which requires an input lter. In addition, the peak current in the switch is larger in DICM operation when compared with continuous inductor current mode. In the DCVM buck converter which is the dual topology of a boost converter operating in DICM, the voltage across the bulk capacitor is lower than the peak of input voltage and besides, the input current is continuous. On account of the above-mentioned reasons, a converter with continuous input current, and inherent PFC properties, is suitable for a single-stage PFC converter [18]. As the buck converter operating in DCVM provides continuous input current and inherent PFC properties, this converter is attractive as a PFC stage [19, 20]. In this paper, a S4 PFC topology is introduced which employs a DCVM buck converter integrated with a yback converter as a DCDC regulator stage. The proposed topology has eliminated the high voltage across the bulk capacitor and reduced the size of yback transformer signicantly. The proposed DCVM buckyback converter is shown in Fig. 1. In this circuit, the bulk capacitor is used to buffer the input power. To charge and discharge Cd, and provide DCVM operation, D2 and coupled inductor L2 are used. When the switch is on, the voltage across the transformer primary is positive and thus, the voltage across L2 is positive and Cd discharges through D2. When the switch is off, the voltage across L2 is negative, and D2 is reversed biased, and thus, Cd is being charged. The input voltage is rectied sinusoidal voltage and in a switching cycle is considered constant, since the line frequency is signicantly lower than the switching frequency. The converter operates at steady-state condition. The voltage across CB is constant in an input line cycle. During a switching period, the currents through inductors L1 and L3 are constant. Cd is small and is charged with constant input current (I1) which ows through L1. The output semi-stage ( yback), is operating in continuous conduction mode. The input capacitor, Cd, is operating in DCVM, so the voltage across this capacitor reduces to zero during every switching cycle. In other words, it is assumed that the input capacitor Cd is fully discharged at the beginning of each switching cycle. The operating modes and essential waveforms are shown in Figs. 2 and 3, respectively. Based on different operating intervals, the following modes of operation are dened. Mode 1 (t0t1): Prior to this mode, Cd is fully discharged. At t0, the switch is turned off and the output diode (D5) conducts. Input capacitor Cd begins to charge to its maximum voltage. Therefore VCd ,M = I1 t t0 Cd 1 I1 t Cd off (1) (2)

VCd ,M =

where I1 is the current through L1, toff is the switch-off time and VCd, M is the maximum voltage of Cd in this switching cycle. Also according to the assumptions Po = Pin (3)

where Po is the output power and Pin is the input power. For a single phase source, Pin is dened as 1 Pin = Vpk Ipk 2 (4)

Converter operation

where Vpk and Ipk are the line peak voltage and current respectively. Also the current of input inductor, L1, is considered constant during a switching cycle. The peak value of I1 is equal to the peak of input current I1 p = Ip k (5)

In this section, the theoretical operation of the proposed S 4 PFC converter is described. The operation is analysed during a switching period. Following assumptions are considered to simplify the converter analysis: All passive and active components are ideal. This means that switching and conduction losses are ignored.

Using (4) and (5), the current of input inductor is determined: I1p = 2Po V pk (6)

Fig. 1 Proposed topology

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Fig. 2 Operating modes of the proposed topology

a Mode 1 b Mode 2 c Mode 3

From (2) and (6), the maximum voltage of input capacitor Cd in terms of input voltage peak and output power is VCd ,Max = 2Po t Vpk Cd off (7)

DC voltage conversion ratio

In this mode, D3 is on and L3 current ows through it and charges CB. In this mode D4 is off. Also the energy stored in the yback transformer core is delivered to the output. Mode 2 (t1t2): At t1, the switch is turned on and the output diode D5 turns off. At the input stage, Cd starts to discharge with current I3I1 where I3 is L3 current. At the end of this mode, Cd is fully discharged. Duration of this mode can be obtained as follows
t2 t1 0

The DC voltage conversion ratio, M, is obtained in this section. The average voltage across L1, over one switching cycle, is zero at steady-state condition. Thus, the average voltage across Cd is equal to the input voltage Vin = (1 D + D )VCd ,M 2 (11)

where D is the switch duty cycle, and D is duration of capacitor Cd discharging mode. Also, VCd,M is the maximum voltage of the capacitor Cd in the related switching cycle. According to volt-second balance of inductor L3 VCd ,2&3 + n2 VCB VCB D = VCB (1 D) VCd ,2&3 = VCB 1 n2 D D (12) (13)

I3 I1 dt =
VCd ,M

Cd dv

(8)

Thus ton = t2 t1 = Cd VCd ,M I1 I3 (9)

The converter maximum switching frequency is fM = 1 1 = TM ton + toff (10)

where n2 is the turns ratio of L2 to primary winding of the yback transformer. Also, VCd,2&3, is the average voltage of Cd during the second and third modes VCd ,2&3 = VCd ,M D 2D (14)

Also diode D4 is conducting and the magnetising inductance of yback transformer is being charged. Mode 3 (t2Ts): In this mode the switch is still on. At t2, D1 begins to conduct and for the rest of this mode, the voltage across Cd remains zero.
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Therefore from (11), (13) and (14) VCB D = Vin 1 n2 D (1 D + D ) (15)

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winding of yback transformer. Consequently, the conversion ratio of input to output voltage can be written as follows Vo n1 DD =M = Vin (1 D) 1 n2 D (1 D + D ) (17)

For proper operation of the proposed topology, voltage of CB should be positive which causes a limitation for selection of n2 and D. Fig. 4 shows the variation of conversion ratio of input voltage to VCB as a function of D and n2 when D is a constant.

Design considerations

In this section, a converter with 20 V output voltage, 50 W output power and 110 V RMS input voltage is designed. Unity value is selected for n1 and n2. In order to guarantee operating in DCVM, D = 0.8D should be chosen. The conversion ratio should be 0.18 so the duty cycle is obtained as D = 0.32 according to (17). 1. DCVM capacitor Cd: Capacitor Cd value is limited by the condition of operating in DCVM. From (11) VCd ,M = Also from (2) Cd = I1 t VCd ,M off (19) 2Vin (1 D + D ) (18)

Substituting (18) into (19), the following equation is obtained

Fig. 3 Important waveforms of the proposed converter

Cd = Also using voltsecond balance of yback converter magnetising inductance Vo n1 D = VCB (1 D) (16)

I1 toff (1 D + D ) 2Vin

(20)

For reliable operation in DCVM condition, Cd should be smaller than the boundary value condition where D = D. Thus Cd = I1 toff 2Vin (21)

where n1 is the turns ratio of secondary winding to primary

where I1 and Vin are the instantaneous values and thus their

Fig. 4 VCB/Vin against D

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ratio is constant and can be calculated according to the output power. Equation (21) shows the maximum value of capacitor Cd. Therefore Cd should be chosen less than this value for reliable operation in DCVM. 2. Flyback transformer: Important parameters of yback transformer are turns ratio and the transformer magnetising inductance Lm. According to the bulk capacitor voltage and output power, Lm can be designed similar to any yback converter. 3. Inductor L2: Fig. 4 shows the variation of VCB to input voltage (conversion ratio) as a function of D and n2 when D is constant. It can be observed that this conversion ratio is acceptable when n2 is equal to 1 or 2. However, larger values of n2 can cause instability in the converter. 4. Inductors L1 and L3: As discussed before, the inductors L1 and L3 currents are assumed constant during a switching period. When the switch S is OFF, a resonant circuit consisting of input voltage source, inductor L1 and capacitor Cd is formed. The mentioned assumption is accurate when this resonance period Tr1 is much larger than the switch S1 off time, (1D)TS Tr1 = 2p L1 Cd (1 D)TS (22) less than 10%. In this condition, the yback converter operating duty cycle is almost constant which results in inherent PFC characteristic of DCVM buck converter.

Equation (22) gives lower limit for inductance L1. Its inductance should be negligible in line frequency when comparing with average input resistance L1 TL (23) Rin Equation (23) gives an upper limitation for inductance L1. Rin is the average input resistance, where Rin =
2 Vin,rms P0

(24)

When the switch is on, a resonant circuit is formed consisting of the input voltage source, the inductors L1, L2, L3 and capacitor Cd and in the output CB that is in parallel with the rest of circuit. As mentioned above, the voltage across CB is assumed constant and thus, the voltage across L2 is constant. Therefore the assumption of constant current for L3 is accurate when the resonance period Tr2 is much larger than the switch on time DTS Tr2 = 2p Le Cd DTS (25)

where Le is the parallel combination of L1 and L3 inductances. In practice, it is desired to select L1 and L3 as small as possible. However, this increases the input current ripple and reduces the power factor. So there is a tradeoff between size and conditions set by (22) and (25). PSpice simulation can be employed to reach more proper values for these inductors. Fig. 5 shows the simulation results for L3 = 200 H and L3 = 600 H. As it can be observed from Fig. 5, DCVM operation of Cd is ruined by larger inductance of L3, and cause higher input current distortion. Other circuit parameters are V1 = 110 Vrms, VO = 20 Vdc, RO = 8 , D = 0.32, L1 = 5 mH and Cd = 33 nf. 5. Control: Similar to any other DC/DC converter, a fast feedback control loop can be employed to keep the output voltage constant. Controller (e.g. SG3525A) samples the output voltage and provides regulation by duty cycle variation. 6. Bulk capacitor CB: The bulk capacitor is designed to meet the holdup time or its desired voltage ripple which is usually
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Fig. 5 Simulation waveforms

a With L2 = 600 H, voltage of Cd b With L2 = 600 H, input current c With L2 = 200 H, voltage of Cd d With L2 = 200 H, input current IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 146152 doi: 10.1049/iet-pel.2012.0191

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Fig. 6 Experimental result of AC input (top waveform) current and (bottom waveform) voltage of input
Vertical scale is 100 V/div or 0.5 A/div, and the time scale is 5 ms/div

Fig. 8 Experimental result of bulk capacitor voltage ripple

Vertical scale is 5 V/div, and the time scale is 5 ms/div

Experimental results

The circuit is implemented in order to verify the operation and accuracy of the proposed topology. The circuit parameters are: Cd = 33 nF/630 Vdc polyester capacitor, CB = 1000 F/ 200 V and CO = 1000 F/100 V electrolyte capacitors, Lm = 60 H, n1 = 1, n2 = 1, L1 = 5 mH, L3 = 200 H, IRFP460 MOSFET, MUR460 ultra-fast diode, SG3525A as controller, the load resistance is 8 for 20 V/50 W DC output and the operating frequency is 50 kHz. The line current and voltage without ltering are shown in Fig. 6. As it is expected, the input current is continuous sinusoidal and without zero crossing in comparison to [15]. Also, the measured power factor is 0.997 and circuit does not require any input lter. Fig. 7a shows the voltage waveform of DCVM capacitor Cd in the range of line frequency. Fig. 7b shows this voltage in the range of switching frequency which justies the theoretical waveform presented in Fig. 3. As it can be observed, the input capacitor operates under DCVM condition and thus the converter has inherent PFC properties. Fig. 8 shows the ripple voltage across the bulk capacitor, so this capacitor is a power buffer between the input stage and the output stage. Fig. 9 shows the switch voltage stress in the range of line frequency. As expected, it is proportional to Cd voltage and the maximum voltage stress is about 260 V. Fig. 10a shows the experimental

Fig. 9 Experimental result of switch voltage stress in the range of line frequency
Vertical scale is 100 V/div, and the time scale is 2.5 ms/div

results of bulk capacitor voltage against output power. The bulk capacitor voltage is low and changes only from 68 to 40 V once the load changes in a wide range. As a result, low cost available electrolytic capacitors can be used. As it can be observed, VCB is not high at light loads and does not suffer from drawback of converters in [7, 8]. Fig. 10b

Fig. 7 Experimental result of Cd capacitor voltage

a In the range of line frequency, the vertical scale is 100 V/div, and the time scale is 2.5 ms/div b In the range of switching frequency, the vertical scale is 50 V/div, and the time scale is 10 s/div IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 146152 doi: 10.1049/iet-pel.2012.0191 151

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IEC 61000-3-2 standards. The proposed converter does not experience high voltage across the bulk capacitor and this voltage is low even at light load condition.

References

Fig. 10 Experimental result

a VCB against Pout b PF against Pout

shows the experimental result of power factor against output power which is very high and exhibits small variation.

Conclusions

In this paper, a new single-stage single-switch PFC converter is presented. The proposed converter is a combination of DCVM buck converter and a yback converter. The proposed converter is analysed and design considerations are discussed. Experimental results obtained from a 50 W prototype converter at a switching frequency of 50 kHz are presented which justies the performance of the proposed topology. Experimental results show that the input current is continuous without zero crossing. Also, the converter power factor is 0.997 and THD is bellow IEEE 519 and

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