Documente Academic
Documente Profesional
Documente Cultură
© 2000 Silicon Storage Technology, Inc.The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc.
396-03 2/00 1 These specifications are subject to change without notice.
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
The SST39LF/VF080 and SST39LF/VF016 also have with Sector-Erase command (30H) and sector address
the Auto Low Power mode which puts the device in a (SA) in the last bus cycle. The Block-Erase operation is
near standby mode after data has been accessed with a initiated by executing a six-byte-command sequence
valid Read operation. This reduces the IDD active read with Block-Erase command (50H) and block address
current from typically 15 mA to typically 4 µA. The Auto (BA) in the last bus cycle. The sector or block address is
Low Power mode reduces the typical IDD active read latched on the falling edge of the sixth WE# pulse, while
current to the range of 1 mA/MHz of read cycle time. The the command (30H or 50H) is latched on the rising edge
device exits the Auto Low Power mode with any address of the sixth WE# pulse. The internal Erase operation
transition or control signal transition used to initiate begins after the sixth WE# pulse. The End-of-Erase
another Read cycle, with no access time penalty. operation can be determined using either Data# Polling
or Toggle Bit methods. See Figures 8 and 9 for timing
Read waveforms. Any commands issued during the Sector- or
The Read operation of the SST39LF/VF080 and Block-Erase operation are ignored.
SST39LF/VF016 is controlled by CE# and OE#, both have
to be low for the system to obtain data from the outputs. Chip-Erase Operation
CE# is used for device selection. When CE# is high, the The SST39LF/VF080 and SST39LF/VF016 provide a
chip is deselected and only standby power is consumed. Chip-Erase operation, which allows the user to erase the
OE# is the output control and is used to gate data from the entire memory array to the “1” state. This is useful when
output pins. The data bus is in high impedance state when the entire device must be quickly erased.
either CE# or OE# is high. Refer to the Read cycle timing The Chip-Erase operation is initiated by executing a six
diagram for further details (Figure 2). byte command sequence with Chip-Erase command
(10H) at address 5555H in the last byte sequence. The
Byte-Program Operation Erase operation begins with the rising edge of the sixth
The SST39LF/VF080 and SST39LF/VF016 are pro- WE# or CE#, whichever occurs first. During the Erase
grammed on a byte-by-byte basis. The Program operation operation, the only valid read is Toggle Bit or Data#
consists of three steps. The first step is the three-byte load Polling. See Table 4 for the command sequence, Figure
sequence for Software Data Protection. The second step 7 for timing diagram, and Figure 18 for the flowchart. Any
is to load byte address and byte data. During the Byte- commands issued during the Chip-Erase operation are
Program operation, the addresses are latched on the ignored.
falling edge of either CE# or WE#, whichever occurs last.
The data is latched on the rising edge of either CE# or Write Operation Status Detection
WE#, whichever occurs first. The third step is the internal The SST39LF/VF080 and SST39LF/VF016 provide two
Program operation which is initiated after the rising edge software means to detect the completion of a write (Pro-
of the fourth WE# or CE#, whichever occurs first. The gram or Erase) cycle, in order to optimize the system Write
Program operation, once initiated, will be completed within cycle time. The software detection includes two status
20 µs. See Figures 3 and 4 for WE# and CE# controlled bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-
Program operation timing diagrams and Figure 15 for of-Write detection mode is enabled after the rising edge of
flowcharts. During the Program operation, the only valid WE#, which initiates the internal Program or Erase opera-
reads are Data# Polling and Toggle Bit. During the internal tion.
Program operation, the host is free to perform additional
tasks. Any commands issued during the internal Program The actual completion of the nonvolatile write is asyn-
operation are ignored. chronous with the system; therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the
Sector/Block-Erase Operation completion of the Write cycle. If this occurs, the system
The Sector- (or Block-) Erase operation allows the sys- may possibly get an erroneous result, i.e., valid data may
tem to erase the device on a sector-by-sector (or block- appear to conflict with either DQ7 or DQ6. In order to
by-block) basis. The SST39LF/VF080 and SST39LF/ prevent spurious rejection, if an erroneous result occurs,
VF016 offer both Sector-Erase and Block-Erase mode. the software routine should include a loop to read the
The sector architecture is based on uniform sector size accessed location an additional two (2) times. If both
of 4 KByte. The Block-Erase mode is based on uniform reads are valid, then the device has completed the Write
block size of 64 KByte. The Sector-Erase operation is cycle, otherwise the rejection is valid.
initiated by executing a six-byte-command sequence
EEPROM
X-Decoder Cell Array
Memory
Address Buffer & Latches
Address
Y-Decoder
CE#
OE# Control Logic I/O Buffers and Data Latches
WE#
DQ7 - DQ0
396 ILL B1.1
13
14
15
16
AC CONDITIONS OF TEST
Input Rise/Fall Time ......... 5 ns
Output Load ..................... CL = 30 pF for SST39LF080/016
........................................ CL = 100 pF for SST39VF080/016
See Figures 13 and 14
TABLE 10: CAPACITANCE (Ta = 25 °C, f=1 Mhz, other pins open)
Parameter Description Test Condition Maximum 11
CI/O(1) I/O Pin Capacitance VI/O = 0V 12 pF
CIN(1) Input Capacitance VIN = 0V 6 pF 12
Note: (1) This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
396 PGM T11.0
Note: (1) This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
AC CHARACTERISTICS
TABLE 12: READ CYCLE TIMING PARAMETERS
VDD = 3.0-3.6V FOR SST39LF080/016 AND 2.7-3.6V FOR SST39VF080/016
SST39LF080/016-55 SST39VF080/016-70 SST39VF080/016-90
Symbol Parameter Min Max Min Max Min Max Units
TRC Read Cycle Time 55 70 90 ns
TCE Chip Enable Access Time 55 70 90 ns
TAA Address Access Time 55 70 90 ns
TOE Output Enable Access Time 30 35 45 ns
TCLZ(1) CE# Low to Active Output 0 0 0 ns
TOLZ(1) OE# Low to Active Output 0 0 0 ns
TCHZ(1) CE# High to High-Z Output 15 20 30 ns
TOHZ(1) OE# High to High-Z Output 15 20 30 ns
TOH(1) Output Hold from Address 0 0 0 ns
Change
396 PGM T13.2
Note: (1) This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
TRC TAA
1
ADDRESS AMS-0
2
TCE
CE#
TOE
3
OE#
TCHZ
TCLZ
TOH
HIGH-Z
5
DQ7-0 HIGH-Z
DATA VALID DATA VALID
7
FIGURE 2: READ CYCLE TIMING DIAGRAM
OE# 12
TCH
CE# 13
TCS
DQ7-0 AA 55 A0 DATA 14
SW0 SW1 SW2 BYTE
(ADDR/DATA) 396 ILL F03.1 15
Note: AMS = Most significant address
AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.
16
FIGURE 3: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
TBP
OE#
TCH
WE#
TCS
DQ7-0 AA 55 A0 DATA
ADDRESS AMS-0
TCE
CE#
TOEH TOES
OE#
TOE
WE#
ADDRESS AMS-0
1
TCE
2
CE#
TOE TOES
TOEH
3
OE#
WE#
4
DQ6
5
TWO READ CYCLES
WITH SAME OUTPUTS
396 ILL F06.1
6
Note: AMS = Most significant address
AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016.
7
TSCE
9
SIX-BYTE CODE FOR CHIP-ERASE
CE# 11
OE#
12
TWP
WE#
13
DQ7-0
AA 55 80 AA 55 10 14
SW0 SW1 SW2 SW3 SW4 SW5 396 ILL F08.1
Note: The device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
15
interchangeable as long as minimum timings are met. (See Table 13)
CE#
OE#
TWP
WE#
DQ7-0
AA 55 80 AA 55 50
Note: The device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 13)
CE#
OE#
TWP
WE#
DQ7-0
AA 55 80 AA 55 30
Note: The device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 13)
2
CE#
3
OE#
TWP TIDA 4
WE#
TWPH
TAA
5
DQ7-0
AA 55 90 BF Device ID
9
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY 10
ADDRESS A14-0 5555 2AAA 5555
11
CE#
12
OE#
TWP TIDA 13
WE#
TWPH 14
TAA
DQ7-0
AA 55 98
DQ7-0 AA 55 F0
TIDA
CE#
OE#
TWP
WE#
T WHP
VIHT
1
INPUT VIT REFERENCE POINTS VOT OUTPUT
VILT 2
396 ILL F14.1
3
«
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Inputs rise and fall times (10% 90%) are <5 ns.
Note: VIT–VINPUT Test 4
VOT–VOUTPUT Test
VIHT–VINPUT HIGH Test
VILT–VINPUT LOW Test
5
FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS
6
7
TO TESTER
8
TO DUT
CL 9
396 ILL F15.1
10
FIGURE 14: A TEST LOAD EXAMPLE
11
12
13
14
15
16
Start
Load data: AA
Address: 5555
Load data: 55
Address: 2AAA
Load data: A0
Address: 5555
Load Byte
Address/Byte
Data
Program
Completed
1
Internal Timer Toggle Bit Data# Polling
Program/Erase
2
Program/Erase Program/Erase
Initiated Initiated Initiated
3
11
12
13
FIGURE 16: WAIT OPTIONS
14
15
16
3
Load data: 55 Load data: 55 Load data: 55
Address: 2AAA Address: 2AAA Address: 2AAA 4
8
Load data: 55 Load data: 55 Load data: 55
Address: 2AAA Address: 2AAA Address: 2AAA
9
11
13
Chip erased Sector erased Block erased
to FFH to FFH to FFH
14
396 ILL F19.0
15
FIGURE 18: ERASE COMMAND SEQUENCE
16
Package Modifier
I = 40 pins
Numeric = Die modifier
Package Type
E = TSOP (10mm x 20mm)
Temperature Range
C = Commercial = 0° to 70°C
I = Industrial = -40° to 85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
55 = 55 ns
70 = 70 ns
90 = 90 ns
Device Density
080 = 8 Megabit
016 = 16 Megabit
Voltage
L = 3.0-3.6V
V = 2.7-3.6V
Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
PIN # 1 IDENTIFIER
1.05
0.95 1
.50
BSC
2
.270
.170 3
10.10
9.90
5
18.50 0.15
0.05
18.30
6
0.70
0.50
7
20.20
19.80
Note: 1. Complies with JEDEC publication 95 MO-142 CD dimensions, although some dimensions may be more stringent.
8
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm. 40.TSOP-EI-ILL.3
11
12
13
14
15
16
Revised 3-11-99
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873
© 2000 Silicon Storage Technology, Inc. 396-03 2/00
24