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All TSK3000A instructions are binary code compatible. Each instruction comprises a 32-bit word divided into an Opcode, which specifies the instruction type, and one or more operands, which further specify the operation of the instruction.
Instruction Format
Each of the TSK3000A's instructions is aligned on a word boundary and is 32 bits (single word) in length. There are three general instruction formats: I-Type this type of instruction includes an immediate value in the instruction word. I-type instructions include arithmetic operations such as ADDI, logical operations such as XORI, branch operations, and load and store operations. J-Type this type of instruction is used where a 26-bit immediate field is required. J-type instructions are only used for absolute jump instructions (J and JAL). R-Type this type of instruction specifies all arguments and results as registers. It includes a 5-bit immediate field used to specify the amount of shift for instructions such as SLL, SRA and SRL. A secondary opcode field is used to distinguish the instruction's operation when part of an instruction class. R-type instructions include arithmetic operations such as SUB, logical operations such as XOR as well as any other instructions that only use register operands. Any other instructions (those more complex or less frequently used) are constructed by using a combination of these three. Figure 1 illustrates the three general formats that instructions can have.
Table 1 summarizes and describes the fields used in the encoding of instructions.
Table 1. Instruction field descriptions.
Description
5-bit index generally representing a 32-bit Source register 5-bit index generally representing a 32-bit Source register 5-bit index generally representing a 32-bit Destination register 5-bit instruction-specific immediate value specifies amount of shift with respect to shift instructions 16-bit sign- or zero-extended immediate value used for: logical operands address byte offsets (load/store instructions) arithmetic signed operands PC relative displacement (branch instructions)
rB
rC
IMM5
IMM16
IMM26
26-bit immediate value. Use as an index, it is subsequently shifted left by 2 bits to provide the low-order 28 bits of the target address for a jump instruction
OpCode-2
6-bit secondary opcode used to specify the function of the instruction when part of an instruction class determined by the primary opcode field (for R-type instructions only)
LW MFC0 MFHI MFLO MTC0 MTHI MTLO MULT MULTU NOR OR ORI RFE SB SH SLL SLLV SLT SLTI SLTIU SLTU SRA SRAV SRL SRLV SUB, SUBU SW SYSCALL XOR XORI The following is a list of all generic instructions (pseudo instructions or macros) defined and supported by the Assembler for the TSK3000A. These instructions translate into one or more separate assembly language instructions (from the core set) in order to fulfil their task. Again, click on a link to access detailed information about that instruction. ABS ADD ADDI ADDIU ADDU AND ANDI B BAL BEQ BEQZ BGE BGEU
BGT BGTU BLE BLEU BLT BLTU BNE BNEZ BREAK DIV DIVU J JAL JALR JR LA LB LBU LH LHU LI LW MOVE MULT MULTU NEG NEGU NOP NOR NOT OR ORI ROL ROR SB SEQ SGE SGEU SGT SGTU SH SLA SLAV SLE SLEU SLL SLLV SLT
SLTI SLTIU SLTU SNE SRA SRAV SRL SRLV SUB SUBU SW XOR XORI
See Also
TSK3000A