Survey on Performance Efficient Soft Processor for 2- D Embedded Graphics Generator

A. Panwar1, Dr. Aravind H.S.2

1 2

Student RIET, Bangalore Professor RIET, Bangalore

Abstract: Field programmable gate arrays (FPGAs) are quick solutions to create hardware circuits and with the increasing in capacity in FPGA configurable logic and decreasing FPGA costs, it has enabled designers to more readily incorporate FPGAs in their designs. This paper provides a literature survey on designing a graphics processing unit based on FPGA. I. INTRODUCTION

II.

PROPOSED SYSTEM

Figure1, shows the architecture of a typical Navigation system, where a dedicated Processor acquires current location through a GPS receiver[1], interpolates it on a Map and is displayed to the user. Design of such a system will require Navigation Data Input Source, a platform for the graphics generation and Soft processor core for executing the user application. Data input source, a platform for the graphics generation and Soft processor core for executing the user application.

Graphics is derived from the word graph which is visual presentation using x and y axis on some surface to inform or illustrate. Information created in digital word is seen on a digital screen, the output on any such digital device is termed as graphics. Embedded system is built for specific requirement and performs pre-defined tasks, such systems are provided with limited number of user interface and one such interface is through visual representation. With the increase in availability of low cost LCDs it has become an important means of interaction between the operator / user and the product. Such systems are essentially provided with some embedded graphics processor or core to generate and control graphics. The Global Positioning System (GPS) has made navigation systems practical for a number of land-vehicle navigation applications such as autonomous navigation systems, Fleet tracking, and Map matching etc. This paper proposes a soft processor for generation of embedded graphics. Section II introduces the basic block diagram of such system and its interface with GPS. A literature survey on the important criterion of design is presented in Section III. Section IV presents some conclusion.

Figure 1: Typical Navigation System

This paper focuses the survey on following three core areas: 1. Navigation 2. Graphics Generation Platform 3. Soft processor core III. 1. Navigation The most basic function of a land-vehicle navigation system is to accurately identify the location of a vehicle with respect to the coordinate system. In LITERATURE SURVEY

many existing land-vehicle navigation systems, this is achieved typically by an on-board computer that continuously collects data from multiple sensors that are mounted inside the vehicle [1]. The computer uses the sensor data to compute the vehicles location by interpolating, applying various fixes and representing this location to the vehicles driver by means of an electronic user interface. These positioning sensors may include: GPS receiver, Gyroscope, Electronic compass, and Tap into the vehicles odometer
Figure 2: Block Diagram with Additional Sensors Input

Figure 2 shows the Navigational System with additional sensors input. 2. Graphics Generation Platform The time critical application has been challenged for years to maintain cost effectiveness while introducing new visually appealing functionality such as data fusion, synthetic vision, and maps [7]. COTS graphics processing units (GPUs) are one solution to the above problem. GPUs provide the high-performance requirements, but these devices were not originally designed for time critical application wherein the device is exposed to high temperature, power constraints, long lifecycle support, and various certification requirements. Because of the complexity and criticality of GPUs in time critical applications, it is believed that COTS GPUs require special attention [8]. The original markets for COTS GPU development have typically been portable and automotive industries. There has been plenty new architectures release at a remarkable rate to keep pace with the completion. But, all these designs are not readily supported in following years.

A simple functional schematic diagram representing the operation of a land vehicle navigation system is shown in Figure2. Although the purpose of GPS is to provide its users with the ability to compute their location in three-dimensional space, in general, a land-vehicle navigation system cannot continuously position a vehicle using a GPS receiver alone[2], and other navigation aids are necessary [3] [4] [5]. Tall buildings, dense foliage, or terrain that stands between a GPS receiver and a GPS satellite will block the satellites signal. Thus, in urban or heavily foliated environments a GPS receiver may be unable to provide a position fix for indefinitely long periods of time. Even if GPS position fixes are available, however, they contain errors and are accurate to 100 m (95% of the time) [6]. However, due to selective availability (SA) [1] the signals from GPS satellite are intentionally degraded and only limited users are allowed to access to signals without SA. Solution to such situation is to include some combination of sensors, eg. Low-cost gyroscopes, compasses, an odometer, inclinometers, and/or accelerometers which can accurately measure changes in the vehicles position over a short time periods and can used alone when GPS signals are unavailable.

Advantages of using FPGA for Graphic Application are: Graphical Functionality Environmental Considerations Life Cycle Constraints

a) Graphical Functionality As application are becoming more complex and they have to interface the operator to more advanced sensors and computational capabilities over the past decade, the requirement to display more advanced graphics has also increased. The pure amount of information available to the operator today requires careful attention to human factors issues in order to maximize situational awareness. Few examples are: Display with Panoramic View Display with Synthetic Vision on Primary Flight Display Display with Engine Gauge on Multifunctional Display

Figure 3: Number of Released GPUs

Figure 3 [2], shows that in the past sixteen years, over 500 GPUs have been released by Nvidia and ATI [9][10]. Because of this nearly continual product release cycle, each device is only available for a very limited time sometimes only six to nine months, which certainly does not support the years or decades of lifecycle support required in time critical applications. These COTs GPUs also offer much more functionality than is required by time critical application, which is usually interested in just a small subset of a graphics rendering software. In the portable and automotive markets, the primary trend is towards GPU cores that are integrated into a custom System on a Chip (SOC). SOCs are extremely cost efficient when the product volumes are very high, which is not usually the case for time critical application. In addition, some of the performance requirements in time critical application for demanding applications such as synthetic vision may be too intensive for the GPU cores that were designed for cell phone and other low resolution applications. In time critical application graphics processing requirement lies somewhere between high-end GPUs and the low-end SOC GPU cores. If the graphics processing are hosted in a field programmable gate array (FPGA) it provides advantage in terms higher performance, longer life cycle and cost.

b) Environmental Considerations Subjecting commercial-grade parts in industrialgrade applications can result in lower reliability of the component and decrease in performance & throughput. With the improvement in technology many programmable chips such as a FPGA is now available in industrial and space grade operational environment. This offers a considerable advantage in terms of reliability and performance compared to a commercial grade COTs GPU. c) Life Cycle Constraints Time critical application equipment is expected to be in service for 10 to 15 years whereas consumer goods are in market for few months. Therefore, when time critical application equipment cannot be heavily based upon consumer technology, the life cycle support becomes tremendous challenge. In addition, the design and certification of time critical application equipment can be a costly endeavor, so

there is additional motivation to design products that can survive many years of production. The longer that the individual components are available, the less reinvestment required for that product. 3. Soft Processor Core Microprocessors on field-programmable gate array (FPGA) chips are becoming an increasingly popular software implementation platform, due to their coexistence on-chip with custom logic. Such coexistence can reduce parts costs and board sizes, and can improve system performance due to reduced communication times between processor and FPGA. A hard-core processor is laid out on the chip next to the FPGAs configurable logic fabric [11]. In contrast, a soft-core processor is synthesized onto the FPGAs fabric, just like any other circuit. Compared to hard-core microprocessors on some FPGA devices, soft-core processors have the advantages of utilizing standard mass-produced and hence lower-cost FPGA parts and of enabling custom number of microprocessors per FPGA (subject to size constraints) over 100 soft-core processors can fit on modern high-end FPGAs. However, soft-core processors have the disadvantages of reduced processor performance, higher power consumption, and larger size [12]. While any microprocessor soft-core could conceivably be mapped to an FPGA, FPGA vendors have in the past years introduced soft core processors specifically targeted for FPGA implementation. Such FPGA soft-cores have instruction sets, arithmetic-logic units, register files, and other features specifically tailored to efficiently use FPGA resources, or perhaps more accurately, to avoid inefficient use of FPGA resources that may occur when synthesizing general soft-core processor to an FPGA. The performance overhead of such soft-core Processors on FPGAs compared to general soft core processors on ASICs (application-specific integrated circuits) can thus be significantly less than the overheads when comparing FPGA versus ASIC implementations of general circuits [12].A feature of FPGA soft-core processors are that of core configuration by the user (the application developer) through the setting of parameters. Parameterized soft

cores represent a different problem from that of developing custom data path units and accompanying custom instructions, as done in application-specific instruction-set processors(ASIPs) like the ASIC-oriented ASIPs or FPGA oriented ASIPs, due to the on/off (or limited number of) values of the parameters [12]. Some of principal products available are: Altera Nios/ NiosII, LatticeMico32 Xilinx Micro Blaze

They offer memory and logic elements with several Intellectual Property (IP) peripherals for the rapid development of System on-Programmable-Chip (SoPC) [13]. Selection Criterion:i. Performance and Power

Two potentially critical system factors include the desired functionality and operational performance as well as the power required to implement the desired system functionality. There will typically be a delta between the power consumption and level of performance for fixed function processor implementations and potentially more flexible FPGA-based soft processor cores. ii. Design and Development Tools

The features and ease of use of the tool suite should be considered along with the tool design flow. Effective tool evaluation and analysis is important. The following factors can have significant effect on design cycle efficiency [15]: Ease of use and feature set Design tool flow Development environment tool maturity Compatibility between major software releases Available training and quality of tool tutorials Debug and verification capabilities

iii.

Operating System Considerations

Another important design factor is the ability to utilize popular operating systems (OSs). Most embedded designs on 32-bit processors include an OS to reduce the design time of the software by providing an abstraction interface level to the software. Most operating systems include the OS and any lower-level software required to connect the OS to the hardware. This collection of software elements is commonly referred to as aboard support package (BSP) (Figure 4). The BSP can include items such as the processor boot code and interrupt service routines for peripherals.

tied to consumer applications, they are usually available for at least 10-15 years instead of sometimes less than a year for discrete GPUs. Furthermore, if the FPGA device does go obsolete, the GPU design could be retargeted to an alternate FPGA with relatively little effort. 3. Soft Processor Core A popular soft core processor example is Altera's NIOS II that has a load-store RISC architecture, in which many architectural parameters can be customized at design time. The user can decide between 16 or 32 bits of width in data path, register file sizes; as well as cache size and custom instructions for the performing of user-defined operation in the speeding-up customized hardware. Those functionalities are supported by the builder development tools and using the Nios II Integrated Development Environment (IDE) is possible to build, run, and debug software of several platforms. Altera also introduces a SOPC builder [14], for the rapidly creation and easily evaluation of embedded systems. The integration off-the-shelf intellectual property (IP) as well as reusable custom components is realized in a friendly way, diminishing the required time to set up a SoC and enabling to construct and designs in hours instead of weeks [13].
Monitor System Interconnect Fabric

Figure 4: Soft Processor Core Platform

IV.

CONCLUSION
Navigation System

Literature survey on Performance efficient soft processor for 2D graphics generator is conducted and following conclusion is derived: 1. Navigation Use of Dead Reckoning systems (DRS) along with a GPS receiver provides an improved performance in the application. DRS are capable of generation information in absence of GPS signals and can be used for Navigational aid. 2. Graphics Generation Platform An FPGA-based GPU provides tremendous lifecycle, certification, and flexibility advantages for critical applications. Because FPGAs are not closely

SRAM

Figure 5: Detailed Block Diagram

Clock

Monitor

DAC

A detailed block diagram is shown in Figure 5 wherein the multisensory Navigational input data is received by FPGA based Graphics Processing Unit and the custom application is supported on a soft processor core. Various other modules such as Memory interface and display interface are the part of FPGA. Reference
[1] Introduction to GPS by Ahmed El Rabbany. [2] The Challenges of Graphics Processing in the Avionics Industry by Marcus Dutton and DavidKeezer. [3] D. A. Divis, GLONASS emerges; Change in ISNS game plan, GPS World, vol. 7, no. 5, p. 12, May 1996. [4] B. W. Parkinson, J. Spilker, Jr., P. Enge, and P. Axelrad,Eds., Global Positioning System: Theory and Applications, vol.2. Washington, DC: American Institute of Aeronautics and Astronautics, 1996. [5] R. L. French, The evolution of automobile navigation systemsin Japan, in Proc. 49th Annu. Meeting Institute of Navigation,June 1993, pp. 6974. [6] Land-Vehicle Navigation Using GPS by Eric Abbott and David Powell. [7] Marcus Dutton, David Keezer, The Challenges of Graphics Processing in the Avionics Industry. [8] Certification Authorities Software Team, Use of COTS Graphical Processors (CGP) in Airborne Display Systems, Position Paper 29, Feb 2007. [9] Comparison of ATI graphics processing units,[Online]. Available: http://en.wikipedia.org/wiki/List_of_ATI_cards. [10] Comparison of NVIDIA graphics processingunits, [Online]. Available: http://en.wikipedia.org/wiki/List_of_NVIDIA_Graphics_Proces sing_Units [11]PetarBorisovMinev, ValentinaStoianovaKukenska, Implementation of Soft Core Processor in FPGAs. [12] Sheldon, D., R. Kumar, F. Vahid, R. Lysecky, D.Tullsen, Application-Specific Customization Of Parameterized FPGA Soft-Core Processors, International Conference on ComputerAided Design, ICCAD, San Jose, November 2006. [13] Caldern, H., C. Elena, S. Vassiliadis, Soft CoreProcessors and Embedded Processing: a survey and analysis, Proceedings of Pro RISC, pp. 483-488, Veldhoven, The Netherlands, November2005. [14] SOPC builder Handbook, http://www.Altera.com. [15] Cofer, R.C., B. Harding, FPGA Soft Processor Design Considerations, Programmable Logic Design Line, October 12, 2005. [16] Cyclone III Device Handbook, http://www.Altera.com. [17] Quartus II Version 7.1 Handbook, http://www.Altera.com. [18] NIOS II Processor reference handbook, http://www.Altera.com.