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Two-Switch Dual-Buck Grid-Connected Inverter With Hysteresis Current Control

Zhilei Yao and Lan Xiao, Member, IEEE
AbstractRenewable energy sources, such as solar energy and fuel cells, are desirable due to their pollution-free properties. In order to utilize the present infrastructure of the utility grid for power transmission and distribution, grid-connected inverters are required for distributed generation systems, which should have high reliability. However, a shoot-through problem, which is a major deterrent to the reliability of the inverters, exists in the conventional bridge-type voltage-source inverters. In order to solve the aforementioned problem, this paper proposes a two-switch dual-buck grid-connected inverter. The freewheeling current ows through the independent diodes instead of the body diodes of the switches, so reverse-recovery loss of the diodes can be reduced. Half of the power devices operate in high frequency; the others switch at grid period with zero-current switching. Moreover, uniploar modulation is used. The operating principle, design guidelines and example, and stability analysis are provided. The proposed inverter can be simplied to a current amplier with hysteresis current control, so it is globally stable. Simulation and experimental results verify the theoretical analysis and satisfy IEEE Std. 929-2000. A comparison of a full-bridge inverter and the proposed inverter shows that the proposed inverter is more attractive in high-reliability applications. Index TermsFull-bridge, half-bridge, hysteresis current control, inverters, zero-current switching.

I. INTRODUCTION

N RECENT years, serious concerns have been raised over fossil fuel electricity generation, because it pollutes our environment and depletes the energy supply. As a result, renewable energy sources, such as solar energy and fuel cells, have been gaining greater attention. These types of sources produce dc power while the present power grid accepts ac power. Therefore, grid-connected inverters [1][11] are required for distributed generation systems, which should have high reliability. However, a shoot-through problem exists in a conventional bridge-type voltage-source inverter. In order to overcome the

Manuscript received October 30, 2009; revised March 11, 2011, July 6, 2011, and October 30, 2011; accepted December 5, 2011. Date of current version April 3, 2012. This work was supported in part by the Qing Lan Project, by the National High Technology Research and Development Program of China (863 Program) under Grant 2011AA11A249, by the National Basic Research Program of China (973 Program) under Grant 2007CB210303, and by the National Nature Science Foundation of China under Grant 51107108. Recommended for publication by Associate Editor T. Shimizu. Z. Yao is with the Jiangsu Key Laboratory of New Energy Generation and Power Conversion, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China, and also with the School of Electrical Engineering, Yancheng Institute of Technology, Yancheng Jiangsu 224051, China (e-mail: nhyzl@163.com). L. Xiao is with the Jiangsu Key Laboratory of New Energy Generation and Power Conversion, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China (e-mail: xiaolan@nuaa.edu.cn). Digital Object Identier 10.1109/TPEL.2011.2179318

problem, a Z-source inverter [12], [13] has been proposed. The shoot-through problem does not exist in the Z-source inverter. Moreover, the Z-source inverter can boost the input voltage, so the input-voltage utilization rate is high. However, the Z-source inverter needs two input inductors and two input capacitors to boost up the input voltage. In addition, the inrush current and resonance between the Z-capacitors and Z-inductors at startup may destroy the power devices and since the input capacitor voltage must be controlled, overall control is more complex than with conventional inverters. The shoot-through problem does not exist in the dualbuck half-bridge inverter (DBHBI) [14], [15], but the inputvoltage utilization rate in the DBHBI is just half that in the full-bridge inverter. When the output voltage is 220 Vrm s , the voltage stresses of the switches should be higher than 800 V, which are difcult to select. In addition, the DBHBI needs two input divided capacitors. To solve these issues, a dual-buck full-bridge inverter (DBFBI) was proposed in [16]. The input-voltage utilization rate in the DBFBI is the same as that in full-bridge inverter. There are no input divided capacitors in the DBFBI. Nevertheless, the number of inductors in the DBFBI is four. Moreover, the voltage waveform before the output lter is bipolar in both DBHBI and DBFBI, so weight and volume of the output lter is larger than that with unipolar modulation. In order to solve the aforementioned problems, this paper proposes a two-switch dual-buck grid-connected inverter. The shoot-through problem does not exist in the proposed inverter. The proposed inverter has the same input-voltage utilization rate as a full-bridge inverter. Unipolar modulation is used, thus weight and volume of the output lter can be reduced compared with bipolar modulation. Only one diode and one switch operate in high frequency at each half line cycle. Moreover, the freewheeling current ows through the independent freewheeling diodes instead of the body diodes of the switches, so reverse-recovery loss of the diodes can be reduced. Hysteresis current control [16][23] offers an unsurpassed transient response in comparison with other current controllers. Furthermore, it is easy to implement and has robust current performance against load and source parameter changes. Therefore, it is very suitable for nonbiased current control, by which the lter inductors, switches, and diodes operate at each half line cycle. The operating principle is described in the next section. Design guidelines and an example are presented in Section III. The stability of the proposed inverter is analyzed in Section IV. The simulation results are provided in Section V. The experimental results from a 1-kW two-switch dual-buck grid-connected

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Fig. 1.

Two-switch dual-buck grid-connected inverter.

inverter conrm the theoretical analysis in Section VI. Comparison between full-bridge inverter and the proposed inverter is provided in Section VII. Finally, the concluding remarks are given in Section VIII. II. OPERATING PRINCIPLE Fig. 1 presents the two-switch dual-buck grid-connected inverter, where Lg is the grid-side lter inductor, L1 and L2 are the inverter-side lter inductors, uo is the output voltage at the inverter side, ugrid f is the feedback voltage of the grid voltage ugrid , Rd is the damping resistor, and iLf 1 and iLf 2 are the feedback currents of the currents through L1 and L2 , respectively. Fig. 2 shows the key waveforms of the proposed gridconnected inverter, where h is the hysteresis band in the control circuit, ig is the grid current, and uds1 uds4 are the voltages across the drain and source of S1 S4 , respectively. There are two switching modes at each half line cycle, and a set of corresponding equivalent circuits is shown in Fig. 3 to aid in understanding each mode. To commence the analysis, assumptions are made as follows. 1) All the diodes are ideal, except for D3 and D4 , which are equivalent to ideal diodes and junction capacitors connected in parallel. The junction capacitors of D3 and D4 are CD3 and CD4 , respectively. The subscripts of CD3 and CD4 represent D3 and D4 , respectively. 2) All the switches are ideal, except for S3 and S4 , which are equivalent to ideal MOSFETs paralleled with output capacitors. The output capacitors of S3 and S4 are CS3 and CS4 , respectively. The subscripts of CS3 and CS4 represent S3 and S4 , respectively. 3) CS3 = CS4 = CS and CD3 = CD4 = CD . 4) All the inductors and capacitors are ideal. 5) The voltage ugrid and the reference current iref are constant in one switching cycle.
Fig. 2. Key waveforms of the proposed grid-connected inverter.

Fig. 3. Equivalent circuits of the proposed grid-connected inverter at ire f > 0. (a) Mode 1. (b) Mode 2.

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6) The input voltage Uin is larger than the peak value of uo (Uop ). 7) L1 = L2 = L. 8) The proposed inverter operates in continuous current mode (CCM). A. iref > 0 From Figs. 1 and 2, S1 and S4 are OFF at this half line cycle, so the current through L1 (iL 1 ) equals to zero, and thus the voltage across L1 is equal to zero. In addition, S3 and D3 are ON at this half line cycle, so the voltage across D1 (ud1 ) is equivalent to zero and uds1 is equal to Uin . S2 is controlled to operate in high frequency. 1) Mode 1 [iLf2 < iref ] [see Fig. 3(a)]: S2 is gated ON. The voltage across D2 (ud2 ) equals to Uin . The current through L2 (iL 2 ) increases linearly. In this mode LdiL 2 Lg dig = Uin ugrid . (1) dt dt 2) Mode 2 [iLf2 > iref + h] [see Fig. 3(b)]: S2 is gated OFF and D2 is forward biased, so uds2 is equal to Uin . The current iL 2 decreases linearly. In this mode LdiL 2 Lg dig = ugrid . (2) dt dt As the average voltage across the inductor is equal to zero in steady state in one switching cycle, (3) can be deduced from (1) and (2) Lg dig LdiL 2 + = d1 (Uin ugrid ) (1 d1 )ugrid = 0 (3) dt dt where d1 is the duty ratio of S2 . From (3), the relationship of ugrid to Uin in steady state can be obtained as ugrid = d1 Uin . (4)

Fig. 3(a) or 3(b), (5) and (6) as shown at the bottom of this page, where T is the grid period. B. iref < 0 The operating principle at this half line cycle is similar to that at iref > 0. III. DESIGN GUIDELINES AND EXAMPLE The design guidelines and example will be designed taking into account the following parameters: 1) input voltage Uin : 360 V; 2) grid voltage ugrid : 220 V/ 50 Hz; and 3) output power Po : 1 kW. A. Switching Frequency Range The turn-on time ton and turn-off time to can be obtained from (1) and (2) by replacing ugrid +Lg dig /dt with uo , respectively ton = to = L |iL 2 | Uin |uo | L |iL 2 | |u o | (7) (8)

where |iL 2 | is the absolute value of the ripple current of iL 2 in one switching cycle. Therefore, the switching frequency fs can be deduced from (7) and (8) fs = ton 1 Uin |uo | |uo |2 = + to Lh Uin (9)

Therefore, the input-voltage utilization rate in the proposed gridconnected inverter at this half line cycle is the same as that in full-bridge inverter. When S4 is turned OFF and S3 is turned ON at t = nT, the voltage uo changes from negative to positive, and the series branch of S4 and D4 begins to sustain positive voltage, and thus CS4 begins to be charged and D4 is still forward biased. When uds4 , i.e., the voltage across CS4 reaches to Uop at t = (n+1/4)T, the voltage across D4 (ud4 ), i.e., the voltage across CD4 , is still zero. As uo decreases after t = (n+1/4)T, the voltage ud4 will begin to be reverse biased, and uo begins to charge CD4 and discharge CS4 . The voltages uds4 and ud4 can be deduced from uo

where h is the hysteresis band of the lter inductor current on the inverter side, i.e., h/K1 (K1 is the feedback coefcient of the lter inductor current on the inverter side). The switching frequency at negative line cycle has the same conclusion as (9). As the power factor is controlled to be 1, the grid can be equivalent to a resistive load R, and thus ugrid and uo can be described as (10) ugrid = 2Ugrid sin(t) ugrid (j ) (jLg + R) (11) R where is the angular frequency of the grid and Ugrid is the root mean square (rms) of the grid voltage. Therefore, uo can be calculated as uo (j ) = uo = 2Ugrid Lg R
2

+ 1 sin(t + )

(12)

uds4 =

ud 4

nT t (n + 1/4)T , n {0, 1, 2, . . .} CD CS Uop + uo (n + 1/4)T < t < (n + 1/2)T CD + CS CD + CS nT t (n + 1/4)T 0 = , n {0, 1, 2, . . .} CS (Uop uo ) (n + 1/4)T < t < (n + 1/2)T CD + CS

(5)

(6)

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where = arctan[(Lg )/R]. According to (9) and (12), the average switching frequency fs av can be obtained as fsav = 1 fs d(t) 0 2 2 2Ugrid Uin Ugrid (Lg /R)2 + 1 Lh Uin

. (13)

According to (9), the maximum switching frequency fs m ax can be obtained at |uo | = Uin /2 fs m ax = fs ||u o |= U i n / 2 Uin = . 4Lh (14)

Fig. 4.

Variation of fs with time.

C. Inductor Design on the Inverter Side When Uin , fs m ax , and h are dened, the inductance L can be calculated from (14) L= 360 Uin = = 500 H. 4h fs m ax 4 1.8 100 103 (19)

The frequency fs m ax cannot be too small, or else the lter inductor size is large. The frequency fs m ax also cannot be too large, as the switching losses of the power devices are large. As MOSFETs are selected as the switches, fs m ax is chosen as 100 kHz when considering the efciency and volume of the proposed inverter. B. Hysteresis-Band Selection From (14), when Uin and fs m ax are dened, the hysteresis band h is inversely proportional to L. The hysteresis band cannot be too small, or else the lter inductor size is large, and thus the volume of the inverter is large. The hysteresis band also cannot be too large, as the losses of the switches, diodes, and lter inductors are large, and the lter inductor current may reduce the tracking accuracy with iref . In this way, the hysteresis band is chosen to 40% of the rated grid current when considering the efciency and volume of the proposed inverter and IEEE Std. 929-2000 h = 0.4Ig = 0.4Po 0.4 1000 = 1.8 A = Ugrid 220 (15)

Fig. 4 shows the variation of fs with time from (9), which is drawn by Mathcad software. As T is 20 ms, the period of |uo | is one-half of the line period, i.e., 10 ms, and thus the period of fs is 10 ms from (9). From Fig. 4, fs m ax is 100 kHz. From [24], the lter inductor on the inverter side can be chosen as two stacked 77894 Kool M cores with 62 turns of two paralleled #21 wires. As the permeability decreases with the current through the lter inductor, the inductance is 500 H at the average value of the inductor current IL av and reduces to 307.5 H at the peak value of the grid current Ig p [24]. The power loss of L1 can be estimated by [24]
1 . 23 2 PL 1 = Pcore + Pcu = 4.578B 2 . 56 fsav Vcore + Irm s1 Rcu (20) where Vcore is the volume of the magnetic core, B is the average value of ux density, Irm s1 is the rms of iL 1 , and Rcu is the winding resistance. Therefore, the power losses of L1 and L2 are about 1.568 W at full load.

where Ig is the rms of ig . The hysteresis current control can be realized by two voltage comparators, e.g., LM311, as shown in Fig. 1. The voltage at positive input terminal U+ can be calculated from Fig. 1 R2 R2 U+ iLf2 iref R1 + R2 R1 + R2 U+ = R2 R1 R2 iref + Us U+ > iLf2 . R1 + R2 R1 + R2 R1 + R2 (16) From Fig. 1 and (16), when iL f 2 < iref , S2 is turned ON; when iL f 2 > iref + Us R1 /R2 , S2 is turned OFF. Therefore, h is equal to Us R1 /R2 according to Fig. 2. The hysteresis band h can be obtained as h Us R 1 h = = . K1 R 2 K1 (17)

D. Filter Capacitor Design The lter capacitance is limited by the decrease of the power factor at rated power. Therefore, the reactive power generated by the lter capacitor is selected as 0.5% of the rated power. The lter capacitance can be obtained as Cf = 0.005Po 0.005 1000 = = 0.329 F. 2 Ugrid 314 2202 (21)

Thus, the lter capacitor is chosen to be three 1 F250 VAC connected in series. E. Filter Inductor Design on the Grid Side The inductor current on the inverter side is divided by the lter capacitor current and ig . Therefore, the current ripple attenuation with respect to the ripple on the inverter side, calculated neglecting losses and damping of the lter, can be given as 1/(jsw Cf ) ig (sw ) 2 = = 2 LC 2 iL (sw ) (1/jsw Cf ) + jsw Lg L C sw (22)

When Us and K1 are 15 V and 0.3, respectively, R2 /R1 can be calculated as 250 Us 15 R2 = . = = R1 h K1 1.8 0.3 9 (18)

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2 1 where L and sw is the switching angular C = (Lg Cf ) frequency. As fs varies with time, the switching frequency in (22) is chosen as one-half of the average switching frequency to estimate the current ripple attenuation. Selecting a current ripple of 1% and according to part B, the current ripple attenuation with respect to the current ripple on the inverter side is 2.5%, so Lg is selected as 2.5 mH according to (13) and (22). On the other hand, the resonant frequency should be higher than ten times the line frequency [25]. According to the earlier calculated parameters, the resonant frequency can be calculated as 13.57 kHz, which is larger than ten times the line frequency, i.e., 500 Hz. The inductor Lg is selected as ve of the same inductors as L1 connected in series. From [24], the inductance reduces to 1.537 mH at Ig p . As the harmonic of ig is very small, the harmonic frequency can be omitted. The power loss of Lg can be estimated as 2 PL g = Pcore + Pcu = 4.578B 2 . 56 f 1 . 23 Vcore + Ig Rcu

Fig. 5.

Control block diagram of the whole system.

(23)

Fig. 6.

Bode plot of G(s).

where f is the grid frequency. Therefore, the power loss of Lg is 5.515 W at full load. as F. Damping Resistor Design In order to avoid oscillation caused by the variable switching frequency with hysteresis current control, passive damping should be added [25]. The impedance of the lter capacitor at the resonant frequency is 35.5 . The damping resistance is chosen as one-third, i.e., 12 . The power loss of Rd from simulation is about 2 W at full load. IV. STABILITY ANALYSIS According to Section II, L1 and L2 function asynchronously, that is, only one of the two inductors operates with Cf at any time. Thus, the system is decreased to a third-order system. A. iref > 0 According to the state-space averaging method [26] and Section II, the averaged state-space equations can be derived as LdiL 2 Lg dig = d1 Uin ugrid dt dt Cf duc = iL 2 ig dt Lg dig Rd Cf duc = uc + ugrid dt dt (24) (25) (26)

The current transfer function of the LCL lter can be gained

2 ig (s) (Rd /Lg )s + L C = 2 2 . iL 2 (s) s + (Rd /Lg )s + L C

(30)

The transfer function of the input voltage of LCL lter-to-the inductor current on the inverter side, G(s), can be obtained from (27)(30). G(s) =
2 2 (s2 + Rd Cf L C s + L C ) 2 s + 2 ) sL(s2 + Rd Cf res res

(31)

2 2 where res = L C (Lg + L)/L.

B. iref < 0 A similar conclusion also can be gained at iref < 0. Therefore, the large-signal model of the whole inverter is shown as in Fig. 5, where iL f is the sum of iL f 1 and iL f 2 , d is the sum of d1 and the duty ratio of S1 (d2 ), and iL is the sum of iL 1 and iL 2 . From (31) and the parameters selected in Section III, the bode plot of G(s) is plotted in Fig. 6. From Fig. 6, the phase margin is no less than 90 in all range of the switching frequency from Fig. 4, so the LCL lter is stable. As the switching frequency is much larger than the grid frequency in most period of the line cycle, the average value of iL f can be controlled tightly by iref , and the average inductor current in one switching period iL (t)can be described as iref (t) iL (t) = K1 (32)

where uc is the voltage across the lter capacitor. In frequency domain, an equivalent description of the model is obtained by (24)(26), i.e., sLiL 2 (s) = d1 Uin ugrid (s) sLg ig (s) sCf uc (s) = iL 2 (s) ig (s) sLg ig (s) = (1 + sRd Cf )uc (s) ugrid (s). (27) (28) (29)

where iref (t) is the average current of iref in one switching period. Thus, Fig. 5 can be simplied to Fig. 7. The proposed grid-connected inverter becomes a current amplier at the average model under hysteresis current control, so it is globally stable.

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Fig. 7.

Simplied control block diagram of the whole system.

Fig. 9.

Harmonic spectrum of iL .

Fig. 10.

Harmonic spectrum of ig with simulation results.

Fig. 8.

Simulation results at full load.

Fig. 11.

Loss Plo ss with simulation results.

V. SIMULATION RESULTS A 1-kW two-switch dual-buck grid-connected inverter has been simulated to verify the theoretical analysis with the parameters shown in Section III, and the models of the MOSFETs and diodes used in SABER simulation software are SPW47N60C3 and DSEI30, respectively. Fig. 8 shows the simulation results at full load, where uA and uBC (see Fig. 1) are the voltages before the LCL lter. From Fig. 8, S1 and S2 operate in high frequency at negative and positive half line cycles, respectively. The voltage stresses of S1 and S2 are Uin and the voltage stresses of S3 and S4 are Uop . The inductor L2 operates at positive half line cycle, whereas L1 operates at negative half line cycle. Therefore, S3 and S4 can realize zero-current switching (ZCS). The voltages uA and uBC are unipolar at negative and positive half line cycles, respectively. As the models of the power devices are practical models, the voltages uds3 and uds4 sustain |uo | before they reach Uop . After that, they are divided by CS and CD . Therefore, the simulation veries the theoretical analysis. The simulated harmonic components of iL operating under rated condition are shown in Fig. 9. From Fig. 9, the harmonic frequency of iL mainly lies between 50 and 90 kHz, which is

in accordance with the switching frequency range shown in Fig. 4. Fig. 10 presents the harmonic spectrum of ig . From Fig. 10, the harmonic component is far less than the limits in IEEE Std. 929-2000. The total harmonic distortion (THD) of ig is 2.25%, which is less than the limit in IEEE Std. 929-2000, i.e., <5%. Fig. 11 shows the power losses of the power devices and damping resistor (Ploss ). From Fig. 11, Ploss increases with Po . VI. EXPERIMENTAL RESULTS A 1-kW prototype has been constructed to verify the theoretical analysis with the parameters shown in Section III, and the MOSFETs and diodes used in the prototype are SPW47N60C3 and DSEI8-06A, respectively. Fig. 12 gives the experimental results at full load. The difference between Figs. 8 and 12(a) is that the divided voltage by CS and CD in Fig. 8 is different from that in Fig. 12(a). The main reason for this is that the model of the diode in simulation is different from that in the practical diode, which cannot be found in the simulation software. As shown in Fig. 12(b), the inductors L1 and L2 operate at negative and positive half line cycles, respectively. The waveform quality of ig is good. From

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Fig. 13.

THD of ig at different output power.

Fig. 14.

Harmonic spectrum of ig with experimental results at rated power.

Fig. 15.

Efciency chart of the proposed grid-connected inverter.

Fig. 12. Experimental results at full load. (a) Waveforms of ug rid , ud s1 , ud s2 , ud s3 , and ud s4 . (b) Waveforms of ig , iL 2 , and iL 1 . (c) Waveforms of ug rid , uA , and uB C .

Fig. 12(c), the proposed grid-connected operates at unipolar modulation. The THD of ig at different power is given in Fig. 13. From Fig. 13, the THD of ig is less than 5% when Po is larger than 400 W. Fig. 14 presents the harmonic spectrum of ig with experimental results at rated power. From Fig. 14, the harmonic component of ig satises the IEEE Std. 929-2000. The THD of ig is 2.93% and power factor is 0.998. Fig. 15 shows the efciency chart of the proposed gridconnected inverter. One point that needs to be claried is that the power loss does not include the power loss of the control circuit. The efciency is high from light load to full load, and the efciency is 98.7% at full load. The main reasons for the high efciency are as follows: 1) only one switch and one diode

switch at high frequency at each half line cycle; 2) half of the switches and diodes operate at grid frequency with ZCS; and 3) the freewheeling current ows through the independent diodes instead of the body diodes of the switches. The proposed grid-connected inverter is simulated by the models of the practical power devices and ideal inductors, so efciency can be estimated by the power loss shown in Fig. 11, (20), and (23). From Fig. 15, the efciency between simulation and experimental results has large difference at low power. The main reason for this is that the inductor current on the inverter side is at discontinuous current mode (DCM), then the harmonic of ig at DCM is larger than that at CCM, and thus the power losses of the inductors estimated by (20) and (23) can cause a large error. The main reasons for the difference in efciency between simulation and experimental results at high power are as follows. 1) The inductors are selected as powder cores, so the inductance varies with ig in practical system. However, the inductance is constant in simulation. 2) The estimated core losses by (20) and (23) are based on fsav .

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VII. COMPARISON BETWEEN FULL-BRIDGE INVERTER AND THE PROPOSED INVERTER In this section, the proposed inverter and full-bridge inverter are compared with the parameters shown in Section III. They have the same input-voltage utilization rate according to the analysis in Section II. A. Total Switching Device Power Comparison In an inverter system, total switching device power (SDP) is a measure of the total semiconductor device requirement, which is an important cost indicator of an inverter system. Based on the analysis in Section II, the rms currents of high-frequency switches Isrm s1 and low-frequency switches Isrm s2 can be expressed as Isrm s1 = 1 T 1 T 1 T 1 T
T /2

TABLE I COMPARISON BETWEEN FULL-BRIDGE INVERTER AND THE PROPOSED INVERTER

(is 1 (t))2 dt
0 T /2

(d2 iL 1
0 T /2

(t))2 dt

3ILp M 4

(33)

Isrm s2 =

(is 4 (t))2 dt
0 T /2 0

(iL 1 (t))2 dt

ILp 2

(34)

where M is equal to 2Ugrid /Uin and the peak lter inductor current ILp omitting the current through Cf can be estimated as 2Ig . The average currents of high-frequency diodes Idav1 and lowfrequency diodes Idav2 can be expressed as Idav1 = Idav2 = = 1 T ILp 2 1 T 1 T
T /2 0

|id 1 (t)| dt = .

1 T

T /2 0

|(1 d2 )iL 1 (t)| dt (35)

2 M 2
T /2 0 T /2 0

problem does not exist in the proposed inverter, which can be a major detriment to the full-bridge inverter. Consequently, the proposed inverter can be used in high-reliability application. In addition, the freewheeling current does not ow through the body diodes of the switches in the proposed inverter, so independent freewheeling diodes with lower reverse-recovery time can be selected. B. Requirement of Passive Components Comparison

|id 4 (t)| dt |iL 1 (t)| dt ILp . (36)

Based upon the earlier analysis and the design guidelines in Section III, the components comparison between the proposed inverter and full-bridge inverter is illustrated in Table I. As shown by Table I, the total SDP of the proposed inverter is a little larger than that of full-bridge inverter. However, the SDP of the switches in the proposed inverter is lower than that of full-bridge inverter. Moreover, the voltage stress of the lowfrequency switches in the proposed inverter is just equal to Uop , which is less than that in full-bridge inverter. The number of high-frequency switches at each half line cycle in the proposed inverter is half of that in the full-bridge inverter. Although the proposed inverter has four extra independent diodes compared with the full-bridge inverter, the shoot-through

Passive components, namely inductors and capacitors, are also important parts to determining the inverter cost and volume. The lter inductors and lter capacitor can be calculated according to Section III. As the compared inverters have the same lter capacitor and lter inductor on the grid side, only the lter inductors on the inverter side are described in Table I. The number of the lter inductors in the proposed inverter is twice than that in full-bridge inverter, but the rms current of the lter inductors in full-bridge inverter is 2 times than that in the proposed inverter. Thus, the required lter inductors in the proposed inverter are a little larger than that in full-bridge inverter. The comparison between full-bridge inverter and the proposed inverter shows that the cost of the proposed inverter is a little higher than that of full-bridge inverter, but the proposed inverter is very promising in high-reliability application.

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VIII. CONCLUSION This paper proposed a two-switch dual-buck grid-connected inverter with hysteresis current control. Unipolar modulation has been chosen. The operating principle, design guidelines and example, and stability analysis have been given. The simulation and experimental results from a 1-kW two-switch dual-buck grid-connected inverter verify the theoretical analysis. The proposed grid-connected inverter has the following characteristics. 1) Only one switch and one diode operate in high frequency at each half line cycle, and half of the power devices switch at grid period with ZCS. 2) In contrast to the DBHBI, the input-voltage utilization rate doubles, and the voltage stresses of the switches and diodes can be reduced at the same output voltage. 3) Compared with the conventional bridge-type voltagesource inverters, the shoot-through problem does not exist. 4) Compared to the full-bridge inverter, the freewheeling current ows through the independent diodes instead of the body diodes of the switches, so reverse-recovery loss of the diodes can be reduced. 5) Compared with the DBHBI and DBFBI, unipolar modulation is used, so weight and volume of the output lter can be reduced. 6) Compared to the Z-source inverter, inrush current at startup does not exist. The comparison between full-bridge inverter and the proposed inverter demonstrated that the proposed inverter is more attractive in high-reliability applications. REFERENCES
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