References

[1] Chia-Chun Tsai, Kai-Wei Hong, Yuh-Shyan Hwang, Wen-Ta Lee and Trong-Yen Lee 2004 IEEE [2] Daegyu Lee, JincheolYoo, and Kyusun Choi 2002 IEEE [3] P.Iyappan1, P.Jamuna2, and S.Vijayasamundiswary 2009 IEEE [4] Mohamed O. Shaker, Soumik Gosh, and Magdy A. Bayoumi2009 IEEE [5] Mahesh Kumar Adimulam, SreehariVeeramachaneni, N MoorthyMuthukrishnan, M.B Srinivas.IEEE2010. [6] YooJincheol, Lee Daegyu, Choi Kyusun and Kim Jongsoo, A power and resolution adaptive flash analog-to-digital converter, International Symposium on Low Power Electronics and Design, Aug. 2002, pp. 233-236. [7] J. Terada, Y. Matsuya, F. Morisawa and Y. Kado, 8-mW, 1-V, 100-Msps, 6-bit A/D converter using a trans-conductance latched comparator, Proceedings of the Second IEEE Asia Pacific Conference on ASIC, Aug. 2000, pp.53-56. [8] B. Yu, andW. Black.Jr, A 900MS/s 6b Interleaved CMOS Flash ADC, IEEE Custom Integrated Circuits Conference, pp. 149152, 2001. [9] M. Choi, and A. A. Abidi, A 6b 1.3GSample/s A/D Converter in 0.35 _m CMOS, IEEE International Solid-State Circuits Conference, pp. 126127, 2001. [10] G. Geelen, A 6b 1.1GSample/s CMOS A/D converter, IEEE International Solid-State Circuits Conference, pp. 128129, 2001. [11] H. Chen, B. Song, and K. Bacrania, A 14-b 20- MSamples/s CMOS Pipelened ADC, IEEE Journal of Solid-State Circuits, 36(6):9971001, June 2001. [12] Y. Park, S. Karthikeyan, F. Tsay, and E. Bartolome, A 10b 100MSamples/s CMOS Pipelined ADC with 1.8V Power upply, IEEE International Solid-State Circuits Conference, [13] S. Mortezapour, and E.K.F. Lee, A 1-V, 8-Bit Successive Approximation ADC in Standard CMOS Process, IEEE Journal of Solid-State Circuits, 35(4):642646, April 2002. [14] J. Yoo, K. Choi, and A. Tangel, A 1-GSPS CMOS Flash A/D Converter for System-on-

Chip Applications, IEEE Computer Society Workshop on VLSI, pp. 135139, 2001. pp. 130 131, 2001

[15] J. Yoo, D. Lee, K. Choi, and A. Tangel, Future-Ready Ultrafast 8Bit CMOS ADC for Systemon-ChipApplications,IEEE International ASIC/SOC Conference, pp. 455 459, 2001. [16] T. Broekaert, B. Brar, J. van der Wagt, A. Seabaugh, T. Moise, F. Morris, E. B. III, and G. Frazier, A Monolithic4 Bit 2 GSps Resonant Tunneling Analog-to-Digital Converter, Gallium Arsenide Integrated Circuit Symposium, pp. 187190, 1997. [17] D. Dalton, G. J. Spalding, H. Reyhani, T. Murphy, K. Deevy, M. Walsh, and P. Griffin, A 200MSPS 6-BitFlash ADC in 0.6-_m CMOS, IEEE Transactions on Circuit and Systems, 45(11):14331444, November 1998. [18] J. Singh, High Speed Multi-Channel Data Acquisition Chip, IEEE International Conference on Electronics, Circuitsand Systems, volume 1, pp. 401404, 1998. [19] Y. Tamba and K. Yamakido, A CMOS 6b 500MSample/s ADC for a Hard Disk Drive Read Channel, IEEE International Solid-State Circuits Conference, pp. 324325, 1999. [20] Y.-T. Wang and B. Razavi, An 8-Bit 150-MHz CMOSA/D Converter, IEEE Journal of SolidState Circuits,35(3):308317, March 2000. [21] K. Yoon, S. Park, and W. Kim, A 6b 500MSample/sCMOS Flash ADC with a Background I interpolated Auto-Zeroing Technique, IEEE International Solid-State CircuitsConference, pp. 326327, 1999. [22] K. Nagaraj, D. A. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio, and T. R. Viswanathan, A dual-mode 700-Msamples/s 6 bit 200-Msamples/s 7-bit A/D Converter in a 0.25-m digital CMOS process, IEEE J. Solid State Circuits, vol. 35, no. 12, pp. 17601768, Dec. 2000.

[23] J. Lee, P. Roux, U.-V. Koc, T. Link, Y. Baeyens, and Y.-K. Chen, A 5-b 10-GSample/s A/D converter for 10-Gb/s optical receivers, IEEE J. Solid-State Circuits, vol. 39, no. 10, pp. 16711679, Oct. 2004. [24] S. Park, Y. Palaskas, and M. P. Flynn, A 4 GS/s 4b flash ADC in 0.18m CMOS, in IEEE ISSCC Dig., 2006, pp. 570571, 674. [25] R. Kanan, F. Kaess, and M. Declercq, A 640 mW high accuracy 8-bit 1 GHz flash ADC encoder, in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 1999, pp. 420423. [26] J. Sauerbrey, D. Schmitt-Landsiedel and R. Thewes, A 0.5V, 1mW Successive Approximation ADC, Proc. 28th Euro.Solid State Circuits Conf., September 2002, Firenze, pp.247-250. [27] S. Mortezapour and E. K. F. Lee, A 1-V, 8 Bit Successive Approximation ADC in Standard CMOS Process, IEEE J. Solid-State Circuits, vol.35, No.4, pp.642-646, April 2000. [28] LE, H.P., Zayegh, A., and Singh, J. "A highspeed low-power CMOS comparator with 10bits resolution,". Proc. 4th Int. Conf on Modeling and Simulation, MS'02, Melbourne, Australia, pp.138-142, March 2003. [29] H.P. Le, A. Zayegh and J. Singh , Performance analysis of optimized CMOS comparator, IEEE E. Letters, Vol. 39, Issue 11, pp. 833 835, 2003. [30] R. Blazquez, P. P. Newaskar, F. S. Lee, A. P. Chandrakasan, "A baseband processor for impulse ultra-wideband communications,"IEEE Journal of Solid-State Circuits, Vol. 40, No. 9, pp.18211828 Sept. 2005. [31] ChristophSandner, Martin Clara, Andreas Santner, Thomas Hartig, and Franz Kutter, A 6bit, 1.2Gs/s Low-Power Flash-ADC in 0.13-m Digital CMOS, IEEE Journal of Solid-State Circuits, Vol. 40, No. 7, pp. 14991505, Jul. 2005. [32] K. Uyttenhove, M. S. J. Steyaert, A 1.8V 6-Bit 1.3-GHz Flash ADC in 0.25-m CMOS, IEEE Journal of Solid-State Circuits, Vol.38, No.7, pp.1115 1122, Jul. 2003.

[33] C. Donovan and M. P. Flynn. A Digital 6 -bit ADC in 0.25m CMOS. IEEE Journal of Solid Stat e Circuits, 37(3):432437, March 2002. .[34] P. C. S. Scholtens and M. Vertregt. A 6b 1.6 Gsample/s Flash ADC in 0.18m CMOS using Averaging Termination, IEEE Journal of Solid State Circuits, 37(12):15991609, December 2002. [35] A Mahesh Kumar, SreehariVeeramachaneni, VenkatTummala, M.B.Srinivas, Design of a Low Power Variable-Resolution Flash ADC", In the Proceedings of the 22nd IEEE/ACM International Conference on VLSI Design and Embedded Systems (VLSI DESIGN 2009),New Delhi , India, 5th -9th January 2009. [36] Maxim Integrated Products, INL/DNL Measurements for High-Speed Analog to-Digital Converters (ADCs). [37] Maxim Integrated Products. Defining and Testing Dynamic Parameters in High -Speed ADCs, 2001 [38] A 3-Bit 2.2V 3.08pJ/Conversion-Step 11GS/s Flash ADC in A 0.12m SiGe BiCMOS TechnologyYuan Yao, Foster Dai, Senior Member IEEE, J. David Irwin, Life Fellow IEEE and Richard C. Jaeger, Fellow IEEE [39] K. Poutlon, K.L. Knudsen, J.J. Corcoran, K. Wang, R.B. Nubling, R.L. Pierson, M.F. Chang, P.M. Asbeck, and R.T. Huang, A 6-b 4GSa/s GaAs HBT ADC, IEEE J. Solid- State Circuits, vol. 30, No. 10, pp. 1109-1118, Oct. 1995. [40] F. Vessal and C.A.T. Salama, An 8-Bit 2-Gsample/s Folding-Interpolating Analog-to-Digital Convert in SiGeTechnology, IEEE J. Solid-State Circuits, vol. 39, No. 1, pp. 238-241, Jan. 2004. [41] T. Broekaert, W.W. Ng, J.F. Jensen, D. Yap, C.H. Fields, S. Bourgholtzer, D.L. Persechini, Y.K.B. Boegeman, B. Shi and R.H. Walden, InP-HBT optoelectronic integrated circuits for photonic analog-to-digital conversion, IEEE J.Solid-State Circuits, vol. 36, No. 9, pp. 1335-

1342, Sep. 2001. [42] W. Cheng, W Ali, M. Choi, K. Liu, T. Tat, D. Devendorf, L. Linder, and R. Stevens, A 3b 40GS/s ADC-19, Feb. 2004.

[43] R.V.D. Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd Edition, KluwerAcademic Publishers, 2003. [44] P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and Design of Analog Integrated Circuits, 4th Edition, John Wiley & Sons, Inc., 2001. [27] H. Nosaka, M. Nakamura, M. Ida, K. Kurishima, T. Shibata, M. Tokumitsu, and M. Muraguchi, A 24-GSPS 3-bit Nyquist ADC usingInP HBTs for electronic dispersion compensation, IEEE MTT-S Intl. Microwave Symp. Dig., vol. 1, pp. 101-104, Jun. 2004. [45] H. Nosaka, M. Nakamura, M. Ida, K. Kurishima, T. Shibata, M. Tokumitsu, and M. Muraguchi, A 24-GSPS 3- bitNyquist ADC using InP HBTs for electronic dispersion compensation, IEEE MTT-S Intl. Microwave Symp. Dig., vol. 1, pp. 101-104, Jun. 2004. [46] B. Razavi, Principles of Data Conversion Systems. New York: IEEE Press, 1995. [47] H. Kimura, A. Matsuzawa, T. Nakamura, and S. Sawada, A 10-b 300-MHz interpolated-parallel A/D converter, IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 438446, Apr. 1993. [48] H. Lee, A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC, IEEE J. SolidState Circuits, vol. 29, no. 4, pp. 509515, Apr. 1994. [49] H. Fiedler, B. Hoefflinger, W. Demmer, and P. Draheim, A 5-bit building block for 20 MHz A/D converters, IEEE J. Solid-State Circuits, vol. SC-16, no. 3, pp. 151155, Jun. 1981. [50] J. Robert, G. Temes, V. Valencic, R. Dessoulavy, and P. Deval, A 16-bit low-voltage CMOS A/D converter, IEEE J. Solid-State Circuits, vol. SC-22, no. 2, pp. 157163, Apr. 1987. [51] B. Song, S. Lee, and M. Tompsett, A 10-b 15-MHz CMOS recycling two-step A/D converter,

IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 13281338, Dec. 1990. [52] S. Lewis, H. Fetterman, G. Gross, R. Ramachandran, and T. Viswanathan, A 10-b 20 -Msample/s analog-to-digital converter, IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 351 358, Mar. 1992. [53] B. Nauta and A. Venes, A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter, IEEE J. Solid-State Circuits, vol. 30, no. 12, pp. 13021308, Dec. 1995. [54] A. Venes and R. Plassche, An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing, IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 18461853, Dec. 1996. [55] A. Yukawa, A CMOS 8-bit high-speed A/D converter IC, IEEE J. Solid-State Circuits, vol. SC-20, no. 3, pp. 775779, Jun. 1985. [56] S. Sutarja and P. Gray, A pipelined 13-bit, 250-ks/s, 5-V analog-to-digital converter, IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 13161323, Dec. 1988. [57] G. Yin, F. Eynde, and W. Sansen, A high-speed CMOS comparator with 8-b resolution, IEEE J. Solid-State Circuits, vol. 27, no. 2, pp. 208211, Feb. 1992. [58] P. Amaral, J. Goes, N. Paulino, and A. Steiger-Garo, An improved low-voltage low-power CMOS comparator to be used in high-speed pipeline ADCs, in Proc. IEEE Int. Symp. Circuits Syst., May 2002, vol. 5, pp. 141144. [59] K. Uyttenhove and M. Steyaert, A 1.8 V 6-bit 1.3-GHz flash ADC in 0.25 _m CMOS, IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 11151122, Jul. 2003. [60] T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, A currentcontrolled latch sense amplifier and a static power-saving input buffer for low-power architecture, IEEE J. SolidState Circuits, vol. 28, no. 4, pp. 523527, Apr. 1993. [61] T. Cho and P. Gray, A 10 b, 20 Msample/s, 35 mW pipeline A/D converter, IEEE J. SolidState Circuits, vol. 30, no. 3, pp. 166172, Mar. 1995.

[62] W. Song, H. Choi, S. Kwak, and B. Song, A 10-b 20-Msample/s lowpower CMOS ADC, IEEE J. Solid-State Circuits, vol. 30, no. 5, pp. 514521, May 1995. [63] M. Choi and A. Abidi, A 6-b 1.3-Gsample/s A/D converter in 0.35- _m CMOS, IEEE J. SolidState Circuits, vol. 36, no. 12, pp. 18471858, Dec. 2001. [64] D. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1996. [65] S. Kim and M. Song, An 8-bit 200MSPS CMOS A/D converter for analog interface module of TFT-LCD Driver, in Proc. IEEE Int. Symp. Circuits Syst., May 2001, vol. 1, pp. 528531. [66] Y. Wang and B. Razavi, An 8-bit 150-MHz CMOS A/D converter, IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 308317, Mar. 2000. [67] L. Nathawad et al., A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling, IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 20212030, Dec. 2000. [68] K. Sushihara and A. Matsuzawa, A 7b 450Msample/sCMOSADC in 0.3 mm , in Dig. Tech. Papers IEEE ISSCC, Feb. 2002, pp. 170171. [69] C. Enz and G. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization,"Proc. IEEE, vol. 84, no. 11,p. 15841614, Nov. 1996. [70]A 5-GS/s 4-Bit Flash ADC with Triode-Load BiasVoltage Trimming Offset Calibration in 65-nm CMOS [71] P. Xiao, et al., A 4b 8GSample/s A/D Converter in SiGe Bipolar Technology, IEEE ISSCC Dig. Tech. Papers, Feb. 1997, pp. 124-125. [72] J. Lee, et al., A 5-b 10-Gsamples/s A/D Converter for 10-Gb/s Optical Receivers, IEEE J. of Solid State Circuits, vol. 39, no. 10, pp. 1671-1679, Oct. 2004. [73] S. Park, Y. Palaskas, A. Ravi, R. E. Bishop, and M. P. Flynn, A 3.5GS/s 5-b Flash ADC in 90nm CMOS, Proc. IEEE CICC, Sept. 2006, pp.489-492.

[74] Y. Lin, Y. Liu, and S. Chang, A 5-bit 4.2-GS/s Flash ADC in 0.13-m CMOS, Proc. IEEE CICC, Sep. 2007, pp. 213-216. [75] K. Deguchi, N. Suwa, M. Ito, T. Kumamoto, and T. Miki, A 6-bit 3.5- GS/s 0.9V 98-mW Flash ADC in 90nm CMOS, IEEE Symposium onVLSI circuits Dig. Tech. Papers, Jun. 2007, pp. 64-65. [76] M. Choi, J. Lee, J. Lee, and H. Son, A 6-bit 5-GSample/s Nyquist A/D Converter in 65nm CMOS, IEEE Symposium on VLSI circuits Dig.Tech. Papers, Jun. 2008, pp. 16-17. [77] H. Chung, et al., A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS, IEEE Symposium on VLSI circuits Dig. Tech. Papers, Jun. 2009, pp. 268269. [78] J. Yao, J. Liu, and H. Lee, Bulk Voltage Trimming Offset Calibration for High-Speed Flash ADCs, IEEE Trans. on Circuits Syst. II, vol. 57, no. 2, pp. 110-114, Feb. 2010. [79] K. Uyttenhove and M. Steyaert, Speed-Power-Accuracy Tradeoff in High-Speed CMOS ADCs, IEEE Trans. Circuits Syst. II, Analog andDigital Signal Processing, vol. 49, no. 4, pp. 280-287, Apr. 2002. [80] A Low Power 6-bit Flash ADC With Reference Voltage and Common-Mode Calibration [81] K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio, and T. Viswanathan, A 700 MSample/s 6b read channel A/D converter with 7b servo mode, in IEEE ISSCC Dig. Tech. Papers, Feb. 2000, pp. 426427. [82] S. Huss, M. Mullen, C. Gray, R. Smith, M. Summers, J. Shafer, P. Heron, T. Sawinska, and J. Medero, A DSP based 10 baseT/100 baseTX Ethernet transceiver in a 1.8 V, 0.18 um CMOS technology, in Proc. IEEE Custom Integrated Circuits Conf., 2001, pp. 135138. [83] D. Sun, A. Xotta, and A. Abidi, A 1 GHz CMOS analog-front-end for a partial-response read channel, IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 22752285, Nov. 2005.

[84] I. Mehr and D. Dalton, A 500 MSample/s ADC or a hard disk-drive channel, IEEE J. SolidState Circuits, vol. 34, no. 7, pp. 912920, Jul. 1999. [85] Y. Tamba and K. Yamakido, A CMOS 6-b 500 MSample/s ADC for a hard drive read channel, in IEEE ISSCC Dig. Tech. Papers, Feb. 1999, pp. 324325. [86] S. Tsukamoto, W. Schofield, and T. Endo, A CMOS 6-b 400 MSample/s ADC with error correction, IEEE J. Solid-State Circuits,vol. 33, no. 12, pp. 19391947, Dec. 1998. [87] M. Choi and A. Abidi, A 6b 1.3 GSamples/s A/D converter in 0.35 um CMOS, in IEEE ISSCC Dig. Tech. Papers, Feb. 2001, pp. 126127. [88] J. Mulder, C.Ward, C. Lin, D. Kruse, J.Westra, M. Lugthart, E. Arslan, R. van de Plassche, K. Bult, and F. van der Goes, A 21 mW 8b 125 MS/s ADC occupying 0.09 mm in 0.13 um CMOS, in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 260261. [89] H. Pan, M. Segami, M. Choi, J. Cao, F. Hator, and A. Abidi, A 3.3 V 12b 50 MSample/s A/D converter in 0.6 um CMOS with over 80 dB SFDR, in IEEE ISSCC Dig. Tech. Papers, Feb. 2000, pp. 4041. [90] K. Kattermann and J. Barrow, A technique for reducing differential nonlinearity errors in flash A/D converters, in IEEE ISSCC Dig. Tech. Papers, Feb. 1991, pp. 170171. [91] K. Bult, A. Buchwald, and J. Laskowski, A 170 mW 10b 50 MSamples/s CMOS ADC in 1 mm , in IEEE ISSCC Dig. Tech. Papers, Feb.1997, pp. 136137. [92] R. Taft, C. Menkus, M. R. Tursi, O. Hidri, and V. Pons, A 1.8 V 1.6 GS/s 8b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency, in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 252253. [93] H. Reyhani and P. Quinlan, A 5 V, 6-b, 80 Ms/s BiCMOS flash ADC, IEEE J. Solid-State Circuits, vol. 29, no. 8, pp. 873878, Aug. 1994. [94] P. Scholtens and M. Vertregt, A 6-b 1.6 Gsample/s flash ADC in 0.18 m CMOS using

averaging termination, IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 15991609, Dec. 2002. [95] K. Uyttenhove and M. Steyaert, A 1.8 V 6-bit 1.3 GHz flash ADC in 0.25 um CMOS, IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 11151122, Jul. 2003. [96] X. Jiang, Z. Wang, and M. Chang, A 2 GS/s 6b ADC in 0.18 um CMOS, in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 322323. [97] M. Pelgrom, A. Duinmaijer, and A. Welbers, Matching properties of MOS transistors, IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 14331440, Oct. 1989. 1046 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 4, APRIL 2009 [98] R. W. Gregor, On the relationship between topography and transistor matching in an analog CMOS technology, IEEE Trans. Electron Device, vol. 39, no. 2, pp. 275282, Feb. 1992. [99] J.-B. Shyu, G. C. Temes, and F. Krummenacher, Random error effect in matched MOS capacitors and current sources, IEEE J. Solid-State Circuits, vol. SC-19, pp. 948955, Dec. 1984. [100] C. Y. Chen, M. Le, and K. Y. Kim, A low power 6-bit flash ADC with reference voltage and common-mode calibration, in Symp. VLSI Circuits Dig., Jun. 2008, pp. 1213. [101] R. van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters. Boston, MA: Kluwer Academic Publishers, 2003. [102] D. Johns and K. Martin, Analog Integrated Circuit Design. New York, NY: Wiley, 1997. [103] F. Kaess, R. Kanan, B. Hochet, and M. Declercq, "New encoding scheme for highspeed flash ADC's," in Proc. IEEE Int. Symp. Circuits Syst., 1997, p. 58. [104]Christopher W. Mangelsdorf, "A 400-MHz Input Flash Converter with Error Correction", IEEE Journal of Solid-State Circuits, Vol. 25, No. 1, February 1990, pp. 184-191. (a discussion of

the AD770, an 8-bit 200 MSPS flash ADC. The paper describes the comparator metastable state problem and how to optimize the ADC design to minimize its effects). [105]Charles E. Woodward, "A Monolithic Voltage-Comparator Array for A/D Converters," IEEE Journal of Solid State Circuits, Vol. SC-10, No. 6, December 1975, pp. 392-399. (an early paper on a 3-bit flash converter optimized to minimize metastable state errors). [106]J. Peterson, "A Monolithic video A/D Converter," IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 6, December 1979, pp. 932-937. [107]Yukio Akazawaet. al., "A 400MSPS 8 Bit Flash A/D Converter," 1987 ISSCC Digest of Technical Papers, pp. 98-99. (describes a monolithic flash converter using Gray decoding). [108]Matsuzawa et al., "An 8b 600MHz Flash A/D Converter with Multi-stage Duplex-gray Coding," Symposium VLSI Circuits, Digest of Technical Papers, May 1991, pp. 113-114. (describes a monolithic flash converter using Gray decoding) [109] A New Approach to Thermometer-to-Binary Encoder of Flash ADCs- Bubble Error Detection Circuit. Bui Van Hieut, SeunghwanChoit, JongkugSeon, YoungcheolOht, ChongdaeParkt, JaehyounParkt, HyunwookKimt, and TaikyeongJeongt,* [110] Comparison of 5-bit Thermometer-to-Binary Decoders in 1.8V, 0.18m CMOS Technology for Flash ADCs[110] [111] D. C. Daly and A. P. Chandrakasan, "A 6-bit, 0.2 V to 0.9 V Highly DigitalFlash ADC With Comparator Redundancy," Solid-State Circuits, IEEEJournal oj, vol. 44, pp. 3030-3038, November 2009. [112] K. Deguchi, N. Suwa, M. Ito, T. Kumamoto, and T. Miki, "A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS," Solid-State Circuits,IEEE Journal oj, vol. 43, pp. 2303-2310, October 2008. [113] C. Sandner, M. Clara, A. Santner, T. Hartig, and F. Kuttner, "A 6-bit 1.2-GS/s low-power

flash-ADC in O.13-μm digital CMOS," Solid-StateCircuits, IEEE Journal oj, vol. 40, pp. 1499-1505, July 2005. [114] R. van de Plassche, CMOS integrated analog-to-digital and digital-toanalogconverters, 2nd ed.: Kluwer Academic Pulisher, 2003. [115] Y. Chia-Nan and 1. Yen-Tai, "A novel flash analog-to-digitalconverter," in Circuits and Systems, IEEE International Symposium on,2008,pp. 2250-2253. [116] K. Uyttenhove, A. Marques, and M. Steyaert, "A 6-bit 1 GHz acquisitionspeed CMOS flash ADC with digital error correction," in CustomIntegrated Circuits, Proceedings of the IEEE Conference on, Orlando,2000, pp. 249-252. [117] F. Kaess, R. Kanan, B. Hochet, and M. Declercq, "New encodingscheme for high-speed flash ADC's," in Circuits and Systems,Proceedings of IEEE International Symposium on, 1997, pp. 5-8. [118] R. Kanan, F. Kaess, and M. Declercq, "A 640 mW high accuracy 8-bit 1GHz flash ADC encoder," in Circuits and Systems, Proceedings of theIEEE International Symposium on, 1999, pp. 420-423. [119] 1.Daegyu, Y. Jincheol, C. Kyusun, and 1.Ghaznavi, "Fat tree encoderdesign for ultra-high speed flash AID converters," in Circuits andSystems, the 45th Midwest Symposium on, 2002, pp. 87-90. [120] E. Sail and M. Vesterbacka, "A multiplexer based decoder for flashanalog-to-digital converters," in TENCON 2004, IEEE Region 10Coriference, pp. 250-253. [121] E. Sail and M. Vesterbacka, "Comparison of two thermometer-to-binarydecoders for highperformance flash ADCs," in 23rd NORCHIPCoriference Finland, 2005, pp. 253-256. [122] E. Sail and M. Vesterbacka, "Thermometer-to-binary decoders for flashanalog-to-digital converters," in Circuit Theory and Design, 18thEuropean Coriference on, 2007, pp. 240-243. [123] N. Agrawal and R. Paily, "An improved ROM architecture for bubbleerror suppression in high

speed flash ADCs," in Student Paper, AnnualIEEE Coriference, 2008, pp. 1-5. [124] M. Rahman, K. 1.Baishnab, and F. A. Talukdar, "A novel ROMarchitecture for reducing bubble and metastability errors in high speedflash ADCs," in Electronics, Communications and Computer, 20thInternational Coriference on, 2010, pp. 15-19. [125] I.-H.Wang and 5.-1. Liu, "A CMOS 5-bit 5GSampie/Sec Analog-todigitalConverter in 0.13um CMOS," in Journal of SemiconductorTechnology and Science, vol.7, no.1, 2007, pp.28-35, [126] R. J. Van de Plassche, Integrated Analog to Digital and Digitalto Analog Converters, Kluwer Academic Publishers, 1994. [127]. K.Uyttenhove and M.Steyaert, A 1.8 V6-bit 1.3GHz flashADC in 0.25 m CMOS, IEEE J. Solid-State Circuits, vol.38,no.7, pp. 1115-1122, July 2003. [128] Portmann, C. L. and Meng, T. H. Y., Power-EfficientMetastability Error Reduction in CMOS Flash A/D Converters,IEEE Journal of Solid-State Circuits, Vol.31, No.8, Aug. 1996, pp.1132-1140 [129] F. Kaess, R. Kanan, B. Hochet and M. Declercq, Newencoding scheme for high-speed flash ADCs, IEEE Proc.Circuits and Syst., vol. 1, pp. 5-8, June 1997. [130] E. Sll, M. Vesterbacka and K.O. Andersson, A study ofdigital decoders in flash analog-todigital converters, IEEE Int.Symp. Circuits Syst., Vancouver, Canada, May 23-26, 2004. [131] E. Sll, and M. Vesterbacka, A multiplexer-based decoder forflash analog-to-digital converters, Proc. TENCON 2004, Nov. 21-24, 2004. [132] Daegyu Lee, JincheolYoo, Kyusun Choi, and JahanGhaznavi,Fat tree encoder design for ultra-high speed flash A/Dconverters, IEEE Midwest Symposium on Circuits and Systems,2002.