Fpga Based Implementation

International Journal of Computer Engineering and Technology (IJCET), ISSN 0976 INTERNATIONAL JOURNAL OF COMPUTER ENGINEERING 6367(Print), ISSN
N 0976 6375(Online) Volume 3, Issue 2, July- September (2012), IAEME & TECHNOLOGY (IJCET)
ISSN 0976 6367(Print) ISSN 0976 6375(Online) Volume 3, Issue 2, July- September (2012), pp. 92-107 IAEME: www.iaeme.com/ijcet.html Journal Impact Factor (2011): 1.0425 (Calculated by GISI) www.jifactor.com
IJCET
IAEME
FPGA BASED IMPLEMENTATION OF DOUBLE PRECISION FLOATING POINT ARITHMETIC OPERATIONS USING VERILOG
Addanki Purna Ramesh Department of ECE, Sri Vasavi Engineering College, Pedatadepalli, Tadepalligudem, India. purnarameshaddanki@gmail.com Dr. A.V. N. Tilak Department of ECE, Gudlavalleru Engineering College, Gudlavalleru, India. avntilak@yahoo.com Dr.A.M.Prasad Department of ECE, UCEK, JNTU, Kakinada, India. a_malli65@yahoo.com ABSTRACT Floating Point Arithmetic is widely used in many areas, especially scientific computation and signal processing. The greater dynamic range and lack of need to scale the numbers makes development of algorithms much easier. However, implementing arithmetic operations for floating point numbers in hardware is very challenging. The IEEE floating point standard defines both single precision (32-bit) and double precision (64-bit) formats, and efficient hardware implementations of arithmetic operations for this standard form a crucial part of many processors. In this paper a double precision floating point arithmetic unit is implemented using Verilog that performs addition, subtraction, multiplication and division. The code is dumped into vertex-5 FPGA. KEYWORDS Floating Point, IEEE, FPGA, Double Precision, Verilog, Arithmetic Unit.
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International Journal of Computer Engineering and Technology (IJCET), ISSN 0976 6367(Print), ISSN 0976 6375(Online) Volume 3, Issue 2, JulyJuly September (2012), IAEME
1. INTRODUCTION The IEEE standard for floating point (IEEE (IEEE-754) 754) defines the format of the numbers, and also specifies various rounding modes that determine the accuracy of the result. For many signal processing, and graphics applications, it is acceptable to trade off some accuracy (in the least significant bit positions) for faster and better implementations. The advantage of floating-point point representation over fixed-point and integer representation is that it can support a much wider range of values. A Floating point describes a method of representing real numbers in a way that can support a wide range of values. Numbers are, in general, represented approximately to a fixed number of significant digits and scaled using an exponent exponent. . The base for the scaling is normally 2, 10 or 16. The typical number that can be represented exactly is of the form Significant digits base exponent over the years, a variety of floating floating-point representations have been used in computers. however, since the 1990s, the most commonly encountered representation is that defined by the IEEE 754 standard. 2. DOUBLE PRECISION FLOATING FLOATING-POINT FORMAT Double precision is a computer numbering format that occupies two adjacent storage locations in computer memory. A double precision number, , sometimes simply called a double, , may be defined to be an integer, fixed point, or floating point. point Modern computers with 32-bit bit storage locations use two memory locations to store a 64-bit 64 double precision number (a single storage location can hold a single precision number). Double precision floating point is an IEEE 754 standard for encoding binary or decimal floating point numbers in 64 bits. Double precision binary floating-point point is a commonly used format on PCs, due to its wider range over single precision floating po point, even if it's at a performance and bandwidth cost. As with single precision floating point format, it lacks precision on integer numbers when compared with an integer format of the same size. It is commonly known simply as double. The IEEE 754 standard defines a double as Sign bit: 1 bit Exponent width: 11 bits Significand precision: 53 bits (52 explicitly stored) The format is written with the significand having an implicit integer bit of value 1,unless the written exponent is all zeros zeros. . With the 52 bits of the fraction significand appearing in the memory format, the total precision is therefore 53 bits (approximately 16 decimal digits, 53log102= 15.95). . The bits are laid out as shown in figure 1.
1 sign bit
11-bits exponent
52-bits bits mantissa
Figure 1: Double Precision Floating Floating-Point Format The real value assumed by a given 64 bit double precision data with a given biased exponent e and a 52 bit fraction is
Where more precisely we have
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International Journal of Computer Engineering and Technology (IJCET), ISSN 0976 6367(Print), ISSN 0976 6375(Online) Volume 3, Issue 2, July July- September (2012), IAEME
2.1 Significand The significand or coefficient or mantissa is the part of a floating-point point number that contains its significant digits. Depending on the interpretation of the exponent, the significand may be considered to be an integer or a fraction. For example, the number 123.45 can be represented as a decimal floating-point point number with integer significand 12345 and exponent 2. Its value is given by the arithmetic12345 102.This same value could also be represented in normalized form with the fractional (non-integer) integer) coefficient 1.2345 and exponent +2( 1.2345 10+2). 2.2 Exponentiation Exponentiation is a mathematical operation, written as an, involving two numbers, the base a and the exponent (or power) n. When n is a positive integer, integer exponentiation corresponds to repeated multiplication; multiplicat in other words, a product of n factors of a (the product itself can also be called power)
Just as multiplication by a positive integer corresponds to repeated addition
The exponent is usually shown as a superscript to the right of the base. The exponentiation an can be read as: a raised to the n-th power, a raised to the power [of] n, or possibly a raised to the exponent [of] n, or more briefly as a to the n. Some exponents have their own pronunciation: for example, a2 is usually read as a squared and a3 as a cubed. . When superscripts cannot be used, as in plain ASCII text text, common alternative formats include a^n and a**n. For an example, the number 3.5 is represented in a double precision floating point format as follows. The sign bit 63 is 0 to represent a positive number. The exponent will be 1024. This is calculated by breaking down 3.5 as (1.75) * 2^ 2 (1). The exponent offset fset is 1023, so you add 1023 + 1 to calculate the value for the exponent field. Therefore, bits 62-52 52 will be 1000000000. The mantissa corresponds to the 1.75, which is multiplied by the power of 2 (2^1) to get 3.5. The leading ing 1 is implied in the mantissa but not actually included in the 64 64-bit format. So 0.75 is represented by the mantissa. Bit 51, the highest bit of the mantissa, corresponds to 2 1 . Bit 50 corresponds to 2-2, and this continues down to Bit 0 which co corresponds rresponds to 2-52. To represent .75, bits 51 and 50 are 1s, and the rest of the bits are 0s. So 3.5 as a double-precision double floating point number is shown in figure 2.
Figure 2 : Representation of a number (3.5) in Double Precision format
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International Journal of Computer Engineering and Technology (IJCET), ISSN 0976 6367(Print), ISSN 0976 6375(Online) Volume 3, Issue 2, July July- September (2012), IAEME
2.3 Special Cases A summary of special cases is shown in Table 1. These are useful in representing exceptional cases like adding to , multiplying to etc. Table 1 Special Cases in IEEE Fl Floating oating Point Representation
2.3.1 Denormalized Numbers A denormalized number is any nonzero number with an exponent field of 0. The exponent offset is 1023, but for the case when the value in the exponent field is 0, then the offset is changed to 1022. The value multiplied by the mantissa is 2 2^ (-1022). 1022). The exponent offset is changed to 1022 because for denormalized numbers, the implied leading 1 is no longer included. So to calculate the actu actual al value of a denormalized number, you multiply 2 2^ (-1022) by the mantissa without the leading 1. The range of values that can be represented by a denormalized number is approximately 2.225e-308 2.225e to 4.94e-324.For 324.For example, the number 2e2e 309 is represented in the double precision floating point format as shown in figure 3.
Figure 3 : Representation of a denormalized number 2.3.2 Infinity The behavior of infinity in floating floating-point point arithmetic is derived from the limiting cases of real arithmetic with operands of arbitrarily large magnitude, when such a limit exists. Infinities shall be interpreted in the affine sense, that is: < {every finite number} < +. Operations on infinite operands are usually exact and therefore signal no exceptions, including, among others, Addition (, x), addition(x, ), subtraction (, x), or subtraction (x, ), for finite x Multiplication (, x) or multiplication(x, ) for finite or infinite x 0 Division (, x) or division(x, ) for finite x Square Root (+) Remainder (x, ) for finite normal x Conversion of infinity into infinity in another format. The exceptions that do pertain to infinities are signalled only when is an invalid operand is created from finite operands by overflow or division div by zero Remainder (subnormal, ) signals underflow 95
International Journal of Computer Engineering and Technology (IJCET), ISSN 0976 6367(Print), ISSN 0976 6375(Online) Volume 3, Issue 2, July- September (2012), IAEME
2.3.3 NaN A NaN is (not a number) a symbolic floating-point datum. There are two kinds of NaN representations: quiet and signalling. Most operations propagate quiet NaNs without signalling exceptions, and signal the invalid operation exception when given a signalling NaN operand. Quiet NaNs are used to propagate errors resulting from invalid operations or values, whereas signalling NaNs can support advanced features such as mixing numerical and symbolic computation or other extensions to basic floating-point arithmetic. For example, 0/0 is undefined as a real number, and so represented by NaN; the square root of a negative number is imaginary, and thus not representable as a real floating-point number, and so is represented by NaN; and NaNs may be used to represent missing values in computations. 3. IMPLEMENTATION OF DOUBLE PRECISION FLOATING POINT ARITHMETIC UNIT The double precision floating point arithmetic unit performs various arithmetic operations such as addition, subtraction, multiplication, division. The block diagram of double precision floating point arithmetic unit (fpu_double) is shown in figure 4.
Figure 4: Block diagram of double precision floating point arithmetic unit (fpu_double). It consists of 6 sub blocks. The blocks are 1. Fpu_add 2. Fpu_sub 3. Fpu_mul 4. Fpu_div 5. Fpu_round 6. Fpu_exceptions The Black box view of double precision floating point arithmetic unit is shown in figure 5.
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Figure:5 Black box view of Double Precision Arithmetic Unit The input signals to the top level module are 1. Clk 2. Rst 3. Enable 4. Rmode (Rounding mode) 5. Fpu_op 6. Opa (64 bits) 7. Opb (64 bits) Table 2&3 shows the Rounding Modes selected for various bit combinations of rmode and Operations selected for various bit combinations of Fpu_op. Table 2: Rounding Modes selected for various bit combinations of rmode Bit Rounding Mode combination 00 round_nearest_even 01 round_to_zero 10 round_up 11 round_down Table 3: Operations selected for various bit combinations of Fpu_op Bit combination 000 001 010 011 1xx Operation Addition Subtraction Multiplication Division Not used
The output signals from the module are the following 1. Out_fp (output from operation, 64 bits) 2. Ready 3. Underflow 97
4. Overflow 5. Inexact 6. Exception 7. Invalid. 3.1 Addition The addition module (fpu_add) is shown in figure 6. The input operands are separated into their mantissa and exponent components, and the larger operand goes into mantissa large and exponent large, with the smaller operand populating mantissa small and exponent small. The comparison of the operands to determine which is larger by comparing the exponents of the two operands. So in fact, if the exponents are equal, the smaller operand might populate the mantissa large and exponent large registers. This is not an issue because the reason the operands are compared is to find the operand with the larger exponent, so that the mantissa of the operand with the smaller exponent can be right shifted before performing the addition. If the exponents are equal, the mantissas are added without shifting.
Figure 6: Black box view of Addition Module 3.2 Subtraction The black box view of subtraction module (fpu_sub) is shown in figure 7. The input operands are separated into their mantissa and exponent components, and the larger operand goes into mantissa large and exponent large, with the smaller operand populating mantissa small and exponent small. Subtraction is similar to addition in that you need to calculate the difference in the exponents between the two operands, and then shift the mantissa of the smaller exponent to the right before subtracting. The definition of the subtraction operation is to take the number in operand B and subtract it from operand A. However, to make the operation easier, the smaller number will be subtracted from the larger number, and if A is the smaller number, it will be subtracted from B and then the sign will be inverted of the result. For example the operation 5- 20. You can take the smaller number (5) and subtract it from the larger number (20), and get 15 as the answer. Then invert the sign of the answer to get 15. This is how the subtraction operation is performed in the module Fpu_sub.
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Figure 7: Black box view of subtraction module 3.3 Multiply The black box view of Multiplication module (fpu_mul) is shown in figure 8. The mantissa of operand A and the leading 1 (for normalized numbers) are stored in the 53-bit register (mul_a). The mantissa of operand B and the leading 1 (for normalized numbers) are stored in the 53-bit register (mul_b). Multiplying all 53 bits of mul_a by 53 bits of mul_b would result in a 106-bit product. 53 bit by 53 bit multipliers are not available in the Xilinx FPGAs, so the multiply would be broken down into smaller multiplies and the results would be added together to give the final 106-bit product. The module (fpu_mul) breaks up the multiply into smaller 24bit by 17-bit multiplies. The Xilinx Virtex5 Device contains DSP48E slices with 25 by 18 twos complement multipliers, which can perform a 24-bit by 17-bit unsigned multiply.
Figure 8: Black box view of multiplication Module The breakdown of the 53-bit by 53-bit floating point multiply into smaller components is product_a = mul_a [23:0] * mul_b [16:0] product_b = mul_a [23:0] * mul_b [33:17] product_c = mul_a [23:0] * mul_b [50:34] product_d = mul_a [23:0] * mul_b [52:51] product_e = mul_a [40:24] * mul_b [16:0] product_f = mul_a [40:24] * mul_b [33:17] product_g = mul_a [40:24] * mul_b [52:34] product_h = mul_a [52:41] * mul_b [16:0] product_i = mul_a [52:41] * mul_b [33:17] Product_ j = mul_a [52:41] * mul_b [52:34]
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The products (a-j) are added together, with the appropriate offsets based on which part of the mul_a and mul_b arrays they are multiplying. For example, product_b is offset by 17 bits from product_ a when adding product_a and product_b together. Similar offsets are used for each product (c-j) when adding them together. The summation of the products is accomplished by adding one product result to the previous product result instead of adding all 10 products (a-j) together in one summation. The final 106-bit product is stored in register (product). The output will be left-shifted if there is not a 1 in the MSB of product. The number of leading zeros in register (product) is counted by using signal (product_shift). The output exponent will also be reduced by using signal (product_shift) The exponent fields of operands A and B are added together and then the value (1022) is subtracted from the sum of A and B. If the resultant exponent is less than 0, than the (product) register needs to be right- shifted by the amount. This value is stored in register (exponent_under). The final exponent of the output operand will be 0 in this case, and the result will be a denormalized number. If exponent_under is greater than 52, than the mantissa will be shifted out of the product register, and the output will be 0, and the underflow signal will be asserted. The mantissa output from the (fpu_mul) module is in 56-bit register (product_7). The MSB is a leading 0 to allow for a potential overflow in the rounding module. The first bit 0 is followed by the leading 1 for normalized numbers, or 0 for denormalized numbers. Then the 52 bits of the mantissa follow. Two extra bits follow the mantissa, and are used for rounding purposes. The first extra bit is taken from the next bit after the mantissa in the 106-bit product result of the multiply. The second extra bit is an OR of the 52 LSBs of the 106-bit product. 3.4 Divide The divide operation is performed in the module fpu_div whose black box view is shown in figure 9. The leading 1 (if normalized) and mantissa of operand A is the dividend, and the leading 1 (if normalized) and mantissa of operand B is the divisor. The divide is executed long hand style, with one bit of the quotient calculated each clock cycle based on a comparison between the dividend register (dividend_reg) and the divisor register (divisor_reg). If the dividend is greater than the divisor, the quotient bit is 1, and then the divisor is subtracted from the dividend, this difference is shifted one bit to the left, and it becomes the dividend for the next clock cycle. If the dividend is less than the divisor, the dividend is shifted one bit to the left, and then this shifted value becomes the dividend for the next clock cycle.
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Figure 9: Black box view of division Module The exponent for the divide operation is calculated from the exponent fields of operands A and B. The exponent of operand A is added to 1023, and then the exponent of operand B is subtracted from this sum. The result is the exponent value of the output of the divide operation. If the result is less than 0, the quotient will be right shifted by the amount. 3.5 Rounding Rounding takes a number regarded as infinitely precise and, if necessary, modifies it to fit in the destinations format while signalling the inexact exception, underflow, or overflow when appropriate. Except where stated otherwise, every operation shall be performed as if it first produced an intermediate result correct to infinite precision and with unbounded range, and then rounded that result according to one of the attributes in this clause. An infinitely precise result with magnitude at least b emax (b b 1p) shall round to with no change in sign; here emax and p are determined by the destination format as RoundTiesToEven, the floating-point number nearest to the infinitely precise result shall be delivered; if the two nearest floating-point numbers bracketing an unrepresentable infinitely precise result are equally near, the one with an even least significant digit shall be delivered RoundTiesToAway, the floating-point number nearest to the infinitely precise result shall be delivered; if the two nearest floating-point numbers bracketing an unrepresentable infinitely precise result are equally near, the one with larger magnitude shall be delivered. Three other user-selectable rounding-direction attributes are defined, the directed rounding attributes RoundTowardPositive, the result shall be the formats floating-point number (possibly +) closest to and no less than the infinitely precise result RoundTowardNegative, the result shall be the formats floating-point number (possibly ) closest to and no greater than the infinitely precise result RoundTowardZero, the result shall be the formats floating-point number closest to and no greater in magnitude than the infinitely precise result. Fpu_round module performs the rounding operation. The black box view is shown in figure 10. 4.3.1.0
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Figure 10: Black box view of rounding Module The inputs to the (fpu_round) module from the previous stage (addition, subtraction, multiply, or divide) are sign (1 bit), mantissa_term (56 bits), and exponent_term (12 bits). The mantissa_term includes an extra 0 bit as the MSB, and two extra remainder bits as LSBs, and in the middle are the leading 1 and 52 mantissa bits. The exponent term has an extra 0 bit as the MSB so that an overflow from the highest exponent (2047) will be caught; if there were only 11 bits in the register, a rollover would result in a value of 0 in the exponent field, and the final result of the fpu operation would be incorrect. There are 4 possible rounding modes. Round to nearest (code = 00), Round to zero (code = 01), Round to positive infinity (code = 10), and Round to negative infinity (code = 11). For round to nearest mode, if the first extra remainder bit is a 1, and the LSB of the mantissa is a 1, then this will trigger rounding. To perform rounding, the mantissa_term is added to the signal (rounding_amount). The signal rounding_amount has a 1 in the bit space that lines up with the LSB of the 52-bit mantissa field. This 1 in rounding_amount lines up with the 2 bit of the register (mantissa_term); mantissa_term has bits numbered 55 to 0. Bits 1 and 0 of the register (mantissa_term) are the extra remainder bits, and these dont appear in the final mantissa that is output from the top level module, fpu_double. For round to zero modes, no rounding is performed, unless the output is positive or negative infinity. This is due to how each operation is performed. For multiply and divide, the remainder is left off of the mantissa, and so in essence, the operation is already rounding to zero even before the result of the operation is passed to the rounding module. The same occurs with add and subtract, in that any leftover bits that form the remainder are left out of the mantissa. If the output is positive or negative infinity, then in round to zero mode, the final output will be the largest positive or negative number, respectively For round to positive infinity mode, the two extra remainder bits are checked, and if there is a 1 in both bit, and the sign bit is 0, then the rounding amount will be added to the mantissa_term, and this new amount will be the final mantissa.Likewise, for round to negative infinity mode, the two extra remainder bits are checked, and if there is a 1 in either bit, and the sign bit is 1, then the rounding amount will be added to the mantissa_term, and this new amount will be the final mantissa.The output from the fpu_round module is a 64-bit value in the round_out register. This is passed to the exceptions module. 102
3.6 Exceptions Exception is an event that occurs when an operation on some particular operands has no outcome suitable for a reasonable application. That operation might signal one or more exceptions by invoking the default or, if explicitly requested, a language-defined alternate handling. Note that event, exception, and signal are defined in diverse ways in different programming environments. The exceptions module is shown in figure11.All of the special cases are checked for, and if they are found, the appropriate output is created, and the individual output signals of underflow, overflow, inexact, exception, and invalid will be asserted if the conditions for each case exist.
Figure 11: Black box view of Exception Module The exception signal will be asserted for the following special cases. 1. Divide by 0: Result is infinity, positive or negative, depending on sign of operand A 2. Divide 0 by 0: Result is SNaN, and the invalid signal will be asserted 3. Divide infinity by infinity: Result is SNaN, and the invalid signal will be asserted 4. Divide by infinity: Result is 0, positive or negative, depending on the sign of operand A the underflow signal will be asserted 5. Multiply 0 by infinity: Result is SNaN, and the invalid signal will be asserted 6. Add, subtract, multiply, or divide overflow: Result is infinity, and the overflow signal will be asserted 7. Add, subtract, multiply, or divide underflow: Result is 0, and the underflow signal will be asserted 8. Add positive infinity with negative infinity: Result is SNaN, and the invalid signal will be asserted 9. Subtract positive infinity from positive infinity: Result is SNaN, and the invalid signal will be asserted 10. Subtract negative infinity from negative infinity: Result is SNaN, and the invalid signal will be asserted 11. One or both inputs are QNaN: Output is QNaN 12. One or both inputs are SNaN: Output is QNaN, and the invalid signal will be asserted 13. If either of the two remainder bits is 1: Inexact signal is asserted.
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If the output is positive infinity, and the rounding mode is round to zero or round to negative infinity, then the output will be rounded down to the largest positive number (exponent = 2046 and mantissa is all 1s). Likewise, if the output is negative infinity, and the rounding mode is round to zero or round to positive infinity, then the output will be rounded down to the largest negative number. The rounding of infinity occurs in the exceptions module, not in the rounding module. QNaN is defined as Quiet Not a Number. SNaN is defined as Signaling Not a Number. If either input is a SNaN, then the operation is invalid. The output in that case will be a QNaN. For all other invalid operations, the output will be a SNaN. If either input is a QNaN, the operation will not be performed, and the output will be a QNaN. The output in that case will be the same QNaN as the input QNaN. If both inputs are QNaNs, the output will be the QNaN in operand A. 4. SIMULATION RESULTS The simulation results of double precision floating point arithmetic operations (Addition, Subtraction, Multiplication, and Division) are shown in figures 12, 13, 14 and 15 respectively. Table 4 and 5 shows the Device utilization and Timing Summary.
Figure 13: Simulation Results for Floating point addition
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Figure 14: Simulation Results for Floating point subtraction
Figure 15: Simulation Results for floating point Multiplication
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Figure 16: Simulation Results for Floating point division Table 4: Device utilization summary Device utilization summary (Vertex-5VLX50FF324-3) Logic Utilization Used Available Number of Slice Registers 4599 28800 Number of Slice LUTs 6118 28800 Number of fully used Bit Slices 3117 7600 Number of bonded IOBs 206 220 Number of BUFG/BUFGCTRLs 2 32 Number of DSP48Es 12 48 Table 5: Timing Summary Timing Summary Minimum period Minimum input arrival time before clocks Maximum output required time after clock 4.253ns (Maximum Frequency: 235.145MHz) 2.228ns 2.520ns
Utilization 15% 21% 41% 93% 6% 25%
5. CONCLUSION This paper presents the implementation of double precision floating point arithmetic operations (addition, subtraction, multiplication, division). The whole design was captured in Verilog Hardware description language (HDL), tested in simulation using Model Techs modelsim, placed and routed on a Vertex 5 FPGA from Xilinx. When synthesized, this module used 15% number of slice registers, 21% Number of Slice luts, and 41% number of fully used Bit Slices. For timing report, this module used 4.253ns (Maximum Frequency: 235.145 MHz).The
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proposed VLSI implementation of the Double Precision arithmetic unit increases the precision over the Single Precision arithmetic unit. 6. REFERENCES [1]. Shamsiah Suhaili and Othman Sidek Design and implementation of reconfigurable alu on fpga, 3rd International Conference on Electrical & Computer Engineering ICECE 2004, 28-30 December 2004, Dhaka, Bangladesh [2]IANSIWEE Std 754-1985, IEEE Standard for Binary Flooring-Point Arithmetic, IEEE, New York, 1985. [3]M. Daumas, C. Finot, "Division of Floating Point Expansions with an Application to the Computation of a Determinant", Journal o/ Universol Compurer Science, vo1.5, no. 6, pp. 323338, June 1999. [4]AMD Athlon Processor techmcal brief, Advance Micro Devices Inc., Publication no. 22054, Rev. D,Dec. 1999. [5]S. Chen, B. Mulgeew, and P. M. Grant, "A clustering techmque for digital communicationschannel equalization using radial basis functionnetworks,'' IEEE Trans. Neural Networks, vol. 4,pp. 570-578, July 1993 [6]S. Hauck, The Roles of FPGAs in reprogrammable System, Proceedings of the IEEE, Vol. 86, No. 4, pp 615-638, April 1998. [7] C. Gloster, Jr., Ph.D., P.E., E. Dickens, A Reconfigurable Instruction Set, MAPLD International Conference 2002. [8] Y. Solihin, W. Cameron, L. Yong, D. Lavenier, M.Gokhale, Mutable Functional Unit and Their Application on Microprocessors, ICCD 2001,International Conference on Computer Design, Austin,Texas, sep 23-26, 2001. [9] D.Lavenier, Y.Solihin, W.Cameron,Integer/floating-point Reconfigurable ALU,Technical Report LA-UR #99-5535, Los Alamos National Laboratory, sep 1999. [10] D.Lavenier, Y.Solihin, W. Cameron, Reconfigurable arithmetic and logic unit. SympA6: 6th Symposium on New Machine Architectures, Besancon, France, June 2000.
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International Journal of Computer Engineering and Technology (IJCET), ISSN 0976 INTERNATIONAL JOURNAL OF COMPUTER ENGINEERING 6367(Print), ISSN

52-bits bits mantissa

Where more precisely we have

Just as multiplication by a positive integer corresponds to repeated addition

Figure 2 : Representation of a number (3.5) in Double Precision format

Figure 13: Simulation Results for Floating point addition

Figure 14: Simulation Results for Floating point subtraction

Figure 15: Simulation Results for floating point Multiplication

Utilization 15% 21% 41% 93% 6% 25%

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