VLSI Realization of a Secure Cryptosystem for

Image Encryption and Decryption

K. Deergha Rao and Ch.Gangadhar
Research and Training Unit for Navigational Electronics
Osmania University
Hyderabad, India.
E-mail:koraidrao@yahoo.com
Abstract- Chaotic maps have been widely used in data encryption.
However, a number of chaos-based algorithms have been shown to
be insecure. The application of BB equation for encryption is
reported in a recent article. In this paper, new algorithms based on
chaos and BB equation are reported for image encryption and
decryption. The algorithms are illustrated through an example. For
practical use, VLSI architectures of the proposed algorithms are
designed and realized using Xilinx ISE VLSI sofware for hardware
implementation. Further, the hardware complexity of the proposed
algorithms is compared with the algorithm reported in [6]
Kewords- BB equation,Cl aos, image encrtion, image
decrtion, VS
I. INTRODUCTION
The use of chaotic signal for secure data tansmission has
seen a signifcant growth in developing chaos-based encryption
and decryption algorithms. However, a number of chaos-based
algorithms have been shown to be insecure [1-5]. A modifed
chaotic key based algorithm with increased key size is
developed in [6] for improved security and VLSI achitecture
of it is developed and realized using Xilinx I SE VLSI sofware
where p is an odd prime. The alterative representation of BB
equation in GF(p) can be rewritten [7] as
(nqx+1)
p
=
(q
y
)
p
(2)
where qx
=(x
2
)
p
,q
y
=(y
2
)
p
' and the subscriptp stands
for modulo operation by p on the argument values of the
expressions. The application of the BB equation for encryption
depends on the following two properties.
I. Given n and p, with p>n>O, it is alwas possible to
obtain
q x
and
q
y coresponding to the roots of the BB
equation (nx
2
+ 1)
p
= (i) p'
2. Given
q x
and
q
y coresponding to any root of the BB
equation (nx
2
+ 1)
p
=
(y
2
)
P
, it is always possible to compute
uniquely, the coresponding value of n ,
o
nly with the
kowledge of p.
The encryption process based on the BB equation is as
follows.
I) n coresponds to the cleartext or plaintext in a block that
is being encrypted.
2) p coresponds to the primary secret key used in the
encryption of the plaintext in a block.
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A cryptosystem based on Brahmagupta-Bhaskara (BB)
equation is proposed in [7]. The cryptosystem proposed in [7]
was subsequently improved i [8] to avoid known plaintext
attacks reported in [9]. However, It is shown in [10] that the
two cryptosystems proposed in [7] and [8] are vulnerable to
kown plaintext attacks. Equation-based approaches, with
moderate size of keys; it is possible to develop algorithms with
high security.
3) The ciphertext corresponding to n is the pair
(qx, q
y ) of
the coresponding BB equation.
Hence, in this paper, based on chaos and the BB-equation,
new algorithms are developed for image encryption and
decryption. Further, for the hardware implementation of the
developed algorithms for practical use, VLSI architectures of
the proposed algorithms are developed and realized using
Xilinx I SE VLSI sofware. Furthermore, the hardware
complexity of the proposed algorithms is compared with the
hardware complexity of the chaos based algorithm proposed in
[6].
as
II. APPLICATION OF BB EQUATION IN
CRYPTOGRAPHY
The BB-equation in Galois Field GF(), can be written [7]
(1)
III. THE PROPOSED ENCRYPTION AND
DECRYPTION ALGORITHMS BASED ON CHAOS AND
BB EQUATION
A. The Pr
o
p
o
se
d
Encrypti
o
n Alg
o
rith
m
The chaotic fnction that used is the well kown logistic
map given by
x
U + 1) = ;U)(1- x
U))
(3)
where f =
3.9
. Let f denote an image of size MxN pixels
and f(x, y
) ,os x S M -1
,
0 S
Y
S N -1
,
be the gray level f at
position (x, y ).In this algorithm
qx, q
y are computed using
the BB equation-based encryption procedure, then a nonlinear
978-1-4244-9799-7111/$26.00 20 11 IEEE
operation (mod operation) on the added value of
qx, q y
and
key in addition to the operations of the CKBA .
The proposed encryption algorithm is as follows.
Step I: Choose p, key 1 and key2 and set j=O.
Step 2: Choose the initial point x (0) and generate the
chaotic sequence x (0), x (I), x(2), .... , x (MN/16-1) using
eq.(1) and then create b (0), b (1), b (2), . . . . , b (2MN-1) fom
x(O), x (I), x (2), . . ... , x (MN/16 - I) by the generating scheme
such that b(32i+0)b(32i+ 1). . . b(32i+ 29) b(32i+ 30)
b(32i+ 31) . . . is the binary representation of x (i) for i = 0, I, 2, ..
.. (MNI16-1)
Step 3: For x=O to M-1
For y = 0 to N- I
obtain
qx (x,y),q/x,y)
for chosenp and given f(x, y )
fom the solution of the BB equation
Switch (2xbU) + b U+1))
Case 3:
qxe (x,y)
=
mod ((qx (x,y) +
kel), 2n-l)
qxe (x,y) = qxe (X,y)XORkeyl
qye (x,y) = mod ((q/x,y) +keyl
), 2n-1)
qye (x, y) = qye (X
,y)XOR keyl
Case
2
:
qxe (x,y)
=
mod ((qx (x,y) +kel
), 2n-1)
qxe (x,y) = qxe (X,y)XORkeyl
qye (x,y) = mod ((q/x,y) +keyl
), 2n-1)
qye (x,y) = qye (x,y)XOR keyl
Case I :
qxe (x,y)
=
mod ((qx (x,y) +
key
2), 2n-l)
qxe (x,y) = qxe (X
,y)XORkey2
qye (x,y) = mod ((q/x,y) +key
2), 2n-1)
qye (x,y) = qye (x, Y)XOR key
2
Case 0: qxe (x, y)
=
mod (( qx (x, y) +
ke2), 2n-1)
qxe (x,y) = qxe (x,y) X key2
qye (x, y) = mod (( q/x, y) +key2), 2n-l)
qye (x, y) = qye (X,y) X key
2
j = j + 2
End; End
Step 4: The result
qxe (x,y)
,
qye (x,y)
is obtained and
stop the algorithm.
Since some of the keys in the key space are crypto
graphically weak, the basic criterion to select kel and key2
should satisf
m-I
I
(aj E d;) = ml2,
i=O
m-I m-I
where keyl = I a jxi , key2 = I d
i
x 2
i
, and
m
is
i=O i=O
the bit length of keyl and key2.
B. The Decrypti
o
n Alg
o
rith
m
Steps 1 and 2 are the same as in the above encryption
algorithm. Steps 3 and 4 for the decryption are as follows.
Step3: F
o
r x=O t
o
M
-
l
For y = 0 to N-I
Switch
(2x + bO+ I))
Case 3:
qx (x,y) = qxe (x,y)
XOR kel
qx (x,y) = mod((qx (x,y) -
keyl
),2n-l)
qy (x,y) = qye (X
,y)
XOR kel
q/x,y) = mod((q/x,y)-
keyl
),2n-1)
f(x,y
) =
(qx (i))-l(qy (i) -l)mod(p).
Case 2:
qx (x,y) = qxe (X,y) X kel
qx (x,y) = mod((qx (x,y) _
keyl
),2n-l)
q/x,y)= qye (X,y)XORkeyl
q/x,y) = mod((q/x,y)-
keyl
),2n-1)
f(x,y
) =
(qx(i))-I(qy(i)-I)mod(p).
Case I:
qx (x,y) = qxe (X,y)XOR key2
qx (x,y) = mod((qx (x,y) _
key
2),2n-l)
q/x,y) = qye (X
,y)XORke
2
q/x,y) = mod((q/x,y)-
key
2),2n-1)
f(x, y
) =
(qx (0-1 (qy (i) - 1) mod(p).
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Case 0:
qx (X' Y)
=
qxe (X,y)XORkey2
qx (X' Y)
=
mod((qx (x,y) -
ke
2),2n-l)
qy (x,y)
=
qye (X,y)
XOR key2
qy (x,y)
=
mod((q/x,y)-
key
2),2n-l)
f(x, y) =
(qx(x, y)r
1
(q/x, y) -l)mod(p).
j
=
j+ 2
End; End
Step 4: The result f is obtained and stop the algorithm.
The 'mod' stands for modulus afer division, the inverse
stands for the modulo inverse, and * represents multiplication
IV. VLSI ARCHITECTURE OF THE PROPOSED
ENCRYPTION AND DECRYPTION ALGORITHMS
The proposed VLSI architectures have two key modules,
one for the generation of chaotic bits (CB), and the other for
encryption or decryption. The architecture of the chaotic bits
(CB) generator is the same as given in [1] where in the word
lengths of x(O) and f are 32. The concept of parallel
processing is adopted so that the encryption or decryption of 16
data values can be performed at the same time. Fig. 1 shows
the hardware architecture of the encryption unit (EU). This
architecture consists of one 32 bit parallel-in parallel-out
register, and 16 encryption processing elements (EPEs). The
hardware architecture of decryption unit (OU) is similar to the
structure shown in Fig. I except that the EPEs are replaced by
decryption processing elements (OPEs) with the encrypted data
as the input.
The cascade architecture of the encryption processing
element (EPE) is shown in Fig. 2. The architecture of EPE 1 is
shown in Fig. 3. It consists of three multipliers, one adder,
two Mod operations and one comparator. The architecture of
EPE2 is shown in Fig. 4. It consists of four data multiplexers,
two adders, two XOR gates, two MOD operations, and two
inverters, four parallel-to-serial converters, and two serial-to
parallel converters. The cascade architecture of the decryption
processing element (OPE) is shown in Fig.5. The architecture
of OPEl is the same as that of EPE2 with qxe and q
y
e as the
inputs. The architecture of OPEl is shown in Fig. 6. The
architecture of DPE2 is shown in Fig. 7. It consists of one
subtractor , one Modulo inverse operation, one multiplier and
one Mod operation.
V. ILLUSTRATEO EXAMPLE
The proposed algorithms are illustrated with the following
example. The 16 bit keys are used in this example. The keys
p,key1, and key2 are chosen as p
=
23687, key1
=
36408
(10001110001110002), and key2 61499
(1ll1000000ll10ll2), and
f
=3.9
, x(O)
=
0.75 are used for
the logistic maps. The proposed encryption algorithm is
implemented on 256X256 Girl(USC) black and white image
using the same keys as mentioned above. The encrypted Girl
image obtained using the proposed encryption algorithm is
shown in Fig. 8(b). From Fig.8(b), it can be observed that the
proposed approach has created highly disordered image of the
original image.
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We designed the proposed encryption and decryption using
VHDL and executed logic simulation with the use of
XILINX's ModelSim on the Girl(USC) image.
The hardware requirements for implementation of the VLSI
architecture of the proposed method and the method reported in
[6] using XILINX sofware are shown in Tables 1 and 2,
respectively for comparison.
VI. CONCLUSIONS
In this paper a secure cryptosystem based on BB equation
and chaos with moderate size of keys is reported and for real
time use of the system, VLSI architecture of the cryptosystem
is designed and realized using Xilinx I SE VLSI sofware on an
image. The hardware complexity of the system is compared
with another cryptosystem. The complexity of the reported
algorithm is high with high security.
REFERENCES
[I] Jui-cheng .. Yen and Jiun-In Guo , "A New Chaotic Key Based Design
for Image Encryption and Decryption, ," Proc. IEEE International
Symposium on Circuits and Systems, May 28-31,2000, Geneva,
Switzerland, vol. IV, pp.49-52.
[2] M.I. Sobhy, and A.R. Shehata, "Methods of attacking chaotic encryption
and countermeasures," Proc. IEEE Inernational Conf Acoustics,
Speech, and Signal Processing (ICASSP 2001), vol. 2, pp. 1001-1004.
[3] S. 1. Li and X. Zheng , "On the security of an image encryption
method," Proc. IEEE International Conference on Image Processing
(ICIP 2002), vo1.2, pp. 925-928, 2002.
[4] S.J. Li and X. Zheng, "Cryptanalysis of a Chaotic Image Encryption
Method", IEEE International Symposium on Circuits and Systems
(ISCAS 2002), vo1. 2, pp. 708-711,2002.
[5] G. Alvarez, F. Montoya, M. Romera, and G. Pastor, "Cryptanalyzing a
discrete-time chaos synchronization secure communication system,"
Chaos, Solitons &fractals, 2003, vo1.21, no.3, pp. 689-694.
[6] K. Deergha Rao and Ch. Gangadhar, "Modifed chaotic key-based
algorithm for image encryption ad its VLSI realization " IEEE
International Conference on Digital Signal Processing (DSP-2007), July
1-4,2007, Cardiff, Wales, U. K, pp. 439 - 442.
[7] N.Rama Murthy and M. N.S. Swamy, " Cryptographic Applications of
Brahmagupta- Bhaskara Equation ", IEEE Transactions on circuits -I,
Regular Papers, Vo1.53, July 2006, pp. 1565-1571.
[8] N. Rama Murthy and M. N.S. Swamy, Author's reply, IE Trans.
Circuits Syst. 1 Reg. Papers, vo1. 54, no. 4, pp. 928-929.
[9] A. M. Youssef, A comment on "Cryptographic applications of
Bramagupta Bhakara equation ", IE Trans. Circuits Syst. I, Reg
Papers, vo1. 54,no. 4,pp. 927-928
[10] G. Alvarez, L. H.Encinas, and ..M. Masque, "Known-Plaintext Attack to
Two Cryptosystems Based on the BB Equation", IEEE Transactions
onCircuits and Systems II: Express Briefs Volume 55, Issue 5, May
2008 Page(s):423 - 426.
[II] KDeerghac Rao,K. Pravween Kumar,and P. V. Muralikrishna, " A New
and Secure Cryptosystem for Image Encryption ad decryption", appear
in IETE Journal of Research, March-Apr. 2011
Table.1 Hardware complexity for VLSI architecture of the
algorithm reported in [6] for encryption and decryption
Hardware Encryption Decryption
component
32 bit register I I
32x32 multiplier 2 2
2-to-1 multiplexer 33 33
32-bit subtractor I I
48-bit substractor 0 16
48-bit adder 16 0
48-bit xor2 16 16
Table.2 Hardware complexity for VLSI architecture of the proposed
algorithm for encryption ad decryption
Hardware
component Encryption Decryption
32-bit register 2 2
I-bit latch 2560 3120
I-bit 2-to-1 multiplexer 1056 2048
16-bit 2-to-1 multiplexer 48 48
32-bit 2-to-1 multiplexer 177 369
33-bit 2-to-1 multiplexer 48 96
64-bit 2-to-1 multiplexer 816 1872
32xl6-bit multiplier 96 160
32x26-bit multiplier I I
32x31-bit multiplier I I
32x32-bit multiplier 64 64
I 7 -bit adder 32 0
32-bit adder 112 128
IS-bit subtractor 0 32
32-bit subtractor 49 161
33-bit subtractor 96 192
64-bit subtractor 816 1872
32-bit comparator equal 32 0
32-bit comparator greater 160 368
32-bit comparator lessequal 80 96
32-bit comparator not equal 0 16
64-bit comparator lessequal 816 1888
16-bit xor2 32 64
Parallel-in
Parallel-out
32-bit Register
CB (31,0)
f
(O

EPE
I
)
CB(3,2)
.
EPE
I
I
f
(1)
CB(29,28)
f
(14
'

EPE

CB(31,30)


.
qxe
(
O)
qye(O)
qxe(l)
qye(l)
qxe(14)
qye(
14)
546
I

f
(15)

EPE

qxe(15)

qye(15)
Fig. 1 Architecture of Encryption Unit
CB(l:O)
3
qxe
: I
EPE2
:
EPEI
qy
qye
Fig. 2 Cascade architecture of EPE
p
qx
qy

Mod
p
Fig. 3 Architecture of EPEI
Key 1
CB (I)
M
U
X
qxe
M
o
D
x
o
R
Fig. 4 Architecture of EPE2
SB
qXe
qye
Fig. 5 Cascade architecture of DPE
CB (0)
CB (0)
+

qxe
X
M
o
D
qx
Fig.6. Architecture of DPE I in the Decryption Unit
Fig. 8 (a) Original Girl(USC)
image
qx
Mod
Fig. 7 Architecture of DPE2
f
Fig. 8 (b) Encrypted Girl(USC) image
using the proposed encryption algorithm
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