International Journal of Engineering Trends and Technology- Volume4Issue2- 2013

ISSN: 2231-5381 http://www.internationaljournalssrg.org Page 81

AbstractBased on fast FIR algorithms (FFAs), this brief
proposes new parallel FIR filter architectures, which are
beneficial to symmetric convolutions of odd length in terms of the
hardware cost. The proposed parallel FIR architectures exploit
the inherent nature of symmetric coefficients reducing half the
number of multipliers in the subfilter section at the expense of
increase in adders in preprocessing and postprocessing blocks.
Exchanging multipliers with adders is advantageous because
adders weigh less than multipliers in terms of silicon area, and in
addition, the overhead from the increase in adders in
preprocessing and postprocessing blocks stay fixed, not
increasing along with the length of the FIR filter, whereas the
number of reduced multipliers increases along with the length of
the FIR filter. For example, for a three-parallel 27-tap filter, the
proposed structure saves 8 multipliers at the expense of five
adders, whereas for a three-parallel 81-tap filter, the proposed
structure saves 26multipliers at the expense of five adders still.

Index TermsDigital signal processing (DSP), fast FIR
algorithms (FFAs), parallel FIR, symmetric convolution, very
large scale integration (VLSI).

I. INTRODUCTION
ALONG the explosive growth of multimedia application,
the demand for high-performance and low-power digital
signal processing (DSP) is getting higher and higher. The FIR
digital filter is one of the most widely used fundamental
devices performed in DSP systems, ranging fromwireless
communications to video and image processing. Some
applications need the FIR filter to operate at high frequencies
such as video processing, whereas some other applications
request high throughput with a low-power circuit such as
multiple-input multiple-output systems used in cellular
wireless communication. Furthermore, when narrow transition
band characteristics are required, the much higher order in the
FIR filter is unavoidable. In this brief, parallel processing in
the digital FIR filter will be discussed. Due to its linear
increase in the hardware implementation cost brought by the
increase in the block size L, the parallel processing technique
loses its advantage to be employed in practice. There have
been a few papers proposing past [1][10].In [1][4],
polyphase decomposition is mainly manipulated, where the


















small-sized parallel FIR filter structures are derived first and
then the larger block-sized ones can be constructed by
cascading or by iterating small-sized parallel FIR filtering
blocks.

Fast FIR algorithms (FFAs) introduced in [1][3] show that
they can implement an L-parallel filter using approximately
(2L 1) subfilter blocks, each of which is of length N/L. It
reduces the required number of multipliers to (2N N/L) from
L N. In [5][9], the fast linear convolution is utilized to
develop the small-sized filtering structures,and then a long
convolution is decomposed into several short convolutions.
However, in both categories of methods, when it comes to
symmetric convolutions, the symmetry of coefficients has not
been taken into consideration yet, which can lead to a
significant saving in hardware cost. Previously, we have
investigated the design for symmetric convolutions based on
even length [10]. In this brief, we will discuss symmetric
convolutions based on odd length and provide new parallel
FIR digital filter architectures consisting of advantageous
polyphase decomposition, which can further reduce amounts
of multipliers required in the subfilter section by exploiting
the inherent nature of the symmetric coefficients, compared
with the existing FFA fast parallel FIR filter structures. This
brief is organized as follows.

II. FFA

Consider an N-tap FIR filter that can be expressed in the
general formas.

y(n) = (n)x(n i),
N-1
=0
n =0,1,2, (1)
wherex(n) is an infinite length input sequence and h(i)
representsthe length-N FIR filter coefficients. Then, the
traditional L-parallel FIR filter can be derived using polyphase
decomposition as [3]

Area Efficient Parallel Fir Digital Filter
Structures For Symmetric Convolutions
Based On Fast Fir Algorithm
1
S.Tamilvanan,
2
R.Rajadurai
1,2
M.E Embedded System Technologies, S.A. Engineering College, Chennai-77

International Journal of Engineering Trends and Technology- Volume4Issue2- 2013

ISSN: 2231-5381 http://www.internationaljournalssrg.org Page 82

P
(Z
L
L-1
P=0
)Z
-P
=X
q
(Z
L
)
L-1
q=0
Z
-q
E

L-1
=0
(Z
L
)Z
-
(2)



Fig. 1. Two-parallel FIR filter implementation
using the FFA.


Fig. 2.Three-parallel FIR filter implementation using the FFA.

WhereX
q
(Z) = Z
-k
k=0
x(Ik +q),X
q
(Z) =
Z
-k
k=0
x(Ik +q),And
p
(Z) =
Z
-k
k=0
y(Ik +p) for p,q,r=0,1,2,,L-1
A. 2 2 FFA (L =2)

According to (2), a two-parallel FIR filter can be expressed
as [1], [3]

0
=E
0
X
0
+Z
-2
E
1
X
1
)

1
=E
0
X
1
+Z
-2
E
1
X
0
(3)
However, (3) can be written as

0
=E
0
X
0
+Z
-2
E
1
X
1

1
=(E
0
+E
1
)(X
0
+X
1
) E
0
X
0
E
1
X
1
(4)
The two-parallel (L =2) FIR filter implementation using the
FFA obtained from(4) is shown in Fig. 1.

B. 3 3 FFA (L =3)

By the similar approach, a three-parallel FIR filter using the


FFA can be expressed as [1], [3]
However, (3) can be written as

Y0=E
0
X
0
Z
-3
E
2
X
2
+x
2
[(E
1
+E
2
)(X
1
+X
2
)
E
1
X
1
]
1=[(E
0
+E
1
)(X
0
+X
1
) E
1
X
1
] (E
0
X
0
Z
-3
E
2
X
2
)

2
=[(E
0
+E
1
+E
2
)(X
0
+X
1
+X
2
)]
[(E
0
+E
1
)(X
0
+X
1
) E
1
X
1
]
[(E
1
+E
2
)(X
1
+X
2
) E
1
X
1
] (5)
The implementation obtained from(5) is shown in
Fig. 2.
III. PROPOSED STRUCTURES FOR SYMMETRIC
CONVOLUTIONS OF ODD LENGTH

To exploit the symmetry of coefficients, the main idea is to
manipulate the polyphase decomposition to earn as many
subfilter blocks as possible, which contain symmetric
coefficients so that half the number of multipliers within a
single subfilter block can be utilized for the multiplications of
whole taps.


Fig. 3A. Implementation of the proposed structure

A. 3 3 Proposed FFA (L =3)
International Journal of Engineering Trends and Technology- Volume4Issue2- 2013

ISSN: 2231-5381 http://www.internationaljournalssrg.org Page 83

The existing two-parallel FFA structure naturally has
benefitsto symmetric convolutions in odd length. When it
comes to a set of odd-length symmetric coefficients, two out
of three subfilters contain symmetric coefficients, i.e., H0 and
H1, shown in Fig. 1. However, the existing three-parallel FFA
structure is not as advantageous. In this section, new three-
parallel FIR filter structures are proposed, which enables more
multipliers sharing in the subfilter section and, therefore, can
save more hardware cost over the existing FFA.

1) Proposed Structure 3A, ((N mod 3) =0): From(5), it
can also be presented as (7). For a set of symmetric
coefficients in odd length N, when (N mod 3) equals zero, (7)
can earn
two more subfilter blocks containing symmetric coefficients
than (5). The implementation of the proposed three-parallel
FIRfilter based on (7) is shown in Fig. 3.An example is
demonstrated here for a clearer perspective.

Example 1: Consider a 27-tap FIR filter with a set of
symmetric coefficients as follows:

{ h(0), h(1), h(2), h(3), h(4), h(5),
h(6), h(7), h(8), h(9), . . . , h(26)}

where h(0)=h(26), h(1)=h(25), h(2)=h(24), h(3)=h(23),
h(4) =h(22), h(5) =h(21), . . . , h(12) =h(14), applying to
the proposed structure 3A, and then, we gain two more
subfilterblocks with symmetric coefficients as



Fig. 4.Subfilter block implementation with symmetric coefficients.





Fig. 5. Comparison of subfilter blocks between the existing FFA and the
proposed structure 3A.


TABLE I

COMPARISON OF PROPOSED AND THE EXISTI NG FFA STRUCTURES
NUMBER OF REQUIRED MULTIPLIERS (M.), REDUCED MULTIPLIERS
(R.M.), NUMBER OF REQUIRED ADDERS IN SUBFILTER SECTION (SUB.),
NUMBER OF REQUIRED ADDERS IN PRE/POSTPROCESSING BLOCKS
(PRE/POST.), NUMBER OF THE INCREASED ADDERS (I.A.)


In addition, the proposed and FFA structures are implemented
in Verilog HDL for an 81-tap linear-phase FIR filter with
word length of 32 bits. The synthesis results by Xilinx Design
Complier and the results are shown in Table II.





Advanced HDL Synthesis Report Table analysis:
L
Len
gth
Struc
ture
Used
Multi
pliers

Reduc
ed
Multi
pliers

Required
Adders
Incre
ased
Adde
rs
Subtr
actor
Pre
/
Pos
t
pro
cess
2
1
tap
FFA 3
- 2
5
3 Prop
osed
3 8
9
tap
FFA 27
6

18
45
27 Prop
osed
21 72
27
tap
FFA 81
8

54
135
81 Prop
osed
73 216
81
tap
FFA 243
24 162
405
243 Prop
osed
219 648
3
1
tap
FFA 3
1 2
5
3 Prop
osed
2 8
9
tap
FFA 27
7 16
45
27 Prop
osed
20 72
27
tap
FFA 81
11 52
135
81 Prop
osed
70 216
81
tap
FFA 243
23 190
405
243 Prop
osed
220 648

A comparison between the proposed and the existing FFA
International Journal of Engineering Trends and Technology- Volume4Issue2- 2013

ISSN: 2231-5381 http://www.internationaljournalssrg.org Page 84

structures with various lengths under different levels of
parallelismis presented in Table I.


TABLE II


SYNTHESIS RESULTS FOR AN 81-TAP LINEAR-PHASE
FIR DIGI TAL FILTER




TABLE III

Area Analysis Graph.


L Length Structure
Number
of Slices
Number
of Slice
Flip
Flops
Number
of 4 input
LUTs
L=2
1 tap
FFA 202 40 353
Proposed 860 45 1627
9 tap
FFA 1445 301 2706
Proposed 4603 333 8422
27 tap
FFA 4270 881 7998
Proposed 12875 950 23707
81 tap
FFA 12713 2631 23875
Proposed 37900 2859 69559
L=3
1 tap
FFA 287 71 528
Proposed 592 83 1152
9 tap
FFA 2133 552 3884
Proposed 4679 595 8720
27 tap
FFA 6277 1639 11441
Proposed 13837 1747 25764
81 tap
FFA 18583 4902 33895
Proposed 41244 5203 76770

Gragh.



SIMULATION RESULTS



Two Parallel Single TAF Filter





9 TAF FILTER





27 TAF FILTER



0 4000080000
FFA
FFA
FFA
FFA
1

t
a
p
9

t
a
p
27

t
a
p
81

t
a
p
1

t
a
p
9

t
a
p
27

t
a
p
81

t
a
p
L
=
2
L
=
3
Number of
bonded IOBs
Number of 4
input LUTs
Number of Slice
Flip Flops
International Journal of Engineering Trends and Technology- Volume4Issue2- 2013

ISSN: 2231-5381 http://www.internationaljournalssrg.org Page 85





81 TAF FILTER


IV.CONCLUSION

In this brief, we have presented new parallel FIR filter
structures, which are beneficial to symmetric convolutions of
odd length. Multipliers are the major portions in hardware
consumption for the parallel FIR filter implementation. The
proposed new structures exploit the nature of symmetric
coefficients of odd length and further reduce the amount of
multipliers required at the expense of additional adders. Since
multipliers outweigh adders in hardware cost, it is profitable
to exchange multipliers with adders. Moreover, the number of
increased adders stays still when the length of FIR filter
becomes large, whereas the number of reduced multipliers
increases along with the length of the FIR filter.




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