CSCC85 Summer 2004

Chapter 6 Interrupts

Introduction
An interrupt is the occurrence of an event that causes a temporary suspension of a program while the event is serviced by another program. Allow a system to respond asynchronously to an event and deal with the event while another program is executing. An interrupt-driven system gives the illusion of doing many things simultaneously by temporarily suspending execution of one program, executing another, then returning to the first program. Similar to a subroutine except that the interruption is a response to an event that occurs asynchronously with the main program. It is not known when the program will be interrupted.

Introduction
Interrupt service routine (ISR) or interrupt handler program that deals with the interrupt executes in response to the interrupt (generally performs an input or output operation to a device) when an interrupt occurs: 1)main program temporarily suspends execution and branches to the ISR 2)ISR executes, performs the operation and terminates with a return from interrupt instruction 3)main program continues where it left off main program operates at base-level, ISRs operate at interrupt-level

Introduction
time Main program

Base-level execution (foreground)

Main *

Main ** ISR * ISR **

Main * ISR

Main **

Interrupt-level execution (background)

* Interrupt ** Return from interrupt instruction

FIGURE 6-1
Program execution with and without interrupts

8051 Interrupt Organization

8051 has 5 interrupt sources: 2 external interrupts 2 timer interrupts 1 serial port interrupt all interrupts are disabled after a system reset and are enabled by software interrupts may occur simultaneously or an interrupt may occur while another is being serviced, so there is both a fixed polling sequence and a programmable two-level priority scheme to schedule the interrupts.

Enabling/Disabling Interrupts
individually enabled/disabled through bit-addressable SFR interrupt enable (IE) register at address 0A8H global enable/disable bit also available 2 bits must be set to enable any interrupt; the individual enable bit and the global enable bit Example: timer 1 interrupts are enabled as follows: SETB ET1 SETB EA ;enable Timer 1 interrupt ;set global enable bit

or could also be coded as SETB IE,#10001000B

Enabling/Disabling Interrupts

TABLE 6-1 IE (interrupt enable) register summary

Interrupt Priority
each interrupt source is individually programmed to one of two priority levels (high and low priorities) through the bitaddressable SFR interrupt priority (IP) at address 0B8H IP is cleared after system reset (lower priority default) allows an ISR to be itself interrupted by a new, higher priority interrupt (a high priority interrupt cannot be interrupted) main program executes at base level and can always be interrupted if two interrupts of different priority occur simultaneously, the higher priority interrupt will be serviced first if two interrupts of the same priority occur simultaneously, a polling sequence determines which is serviced first

Interrupt Priority

TABLE 6-2 IP (interrupt priority) register summary

Polling Sequence
if two interrupts of the same priority occur simultaneously, a fixed polling sequence determines which one is serviced first sequence is: external 0 Timer 0 external 1 Timer 1 serial port Timer 2 (8052 only)

8051 Interrupt Structure

IE Register
IT0 1 INT0 0 TF0 IT1 1 INT1 0 TF1 IE1 IE0

IP Register

High priority interrupt

Low priority interrupt

RI TI TF2 EXF2

Interrupt polling sequence

(8052 only) Individual interrupt enables Global enable

FIGURE 6-2

Overview of 8051 interrupt structure

Accept interrupt

Interrupt Flags
The flag bits that generate interrupts are:

Processing Interrupts
When an interrupt occurs and is accepted by the CPU, the main program in interrupted. The following actions accur: current instruction completes execution PC is saved on the stack current interrupt status is saved internally interrupts are blocked at the level of the interrupt PC is loaded with the vector address of the ISR ISR executes when ISR completes, a RETI (return from interrupt) instruction executes

Interrupt Vectors
interrupt vector the value loaded into the PC when an interrupt is accepted it is the address of the start of the ISR for the interrupting source External code memory
FFFF

Main program 0030 002F 0000 LJMP MAIN Reset and interrupt entry points

system reset vector (RST at address 0000H) is included in this table since it behaves like an interrupt

Interrupt Vectors
vectoring to an interrupt automatically clears the flag that caused the interrupt (done in hardware) exceptions are RI and TI for serial port interrupts (and TF2 and EXF2 for Timer 2 interrupts) since there are two possible sources for each of these interrupts these bits must be tested in the ISR to determine the source of the interrupt, and then the interrupting flag is cleared by software and a branch to the appropriate action occurs since the interrupt vectors are at the beginning of code memory, the first instruction of the main program is often a jump to skip over it. (eg. LJMP 0030H)

Program Design Using Interrupts

previous examples involving the timers and the serial port did not use interrupts instead they used wait loops to poll the timer overflow flags (TF0, TF1) or the serial port transmit/receive flags (TI or RI) continuously polling a flag consumes the CPU's valuable execution time, especially in cases where there are many input and output devices to contend with suggested framework for a self-contained program using interrupts:
ORG 0000H LJMP ... ORG 0030H MAIN: ... ;MAIN PROGRAM ENTRY POINT ;MAIN PROGRAM BEGINS MAIN ;RESET ENTRY POINT

Program Design Using Interrupts

Small Interrupt Service Routines (ISRs) since there are 8 bytes between each interrupt entry point, this may be enough memory for a small ISR Example: If Timer 0 was the only interrupt source used we could use the following framework:
ORG LJMP ORG ... RETI ... ... 0000H MAIN 000BH ;RESET ;Timer 0 entry point ;Timer 0 ISR begins ;Return to main program ;Main program

TOISR: MAIN:

Program Design Using Interrupts

Large Interrupt Service Routines if an ISR is longer than 8 bytes, it may be moved elsewhere in code memory or it may trespass on the entry point for the next interrupt Example: Using Timer 0 again, we could use the following framework:
ORG LJMP ORG LJMP ORG ... ... RETI 0000H MAIN 000BH TOISR 0030H ;RESET ;Timer 0 entry point ;past interrupt vectors ;Timer 0 ISR begins ;Return to main program

MAIN: TOISR:

Program Design Using Interrupts

Example: Square Wave Using Timer Interrupts Write a program using Timer 0 and interrupts to create a 10 kHz square wave on P1.0 Solution: ORG LJMP ORG CPL RETI ORG MOV MOV SETB MOV SJMP 0 MAIN 000BH P1.0 0030H TMOD,#02H TH0,#-50 TR0 IE,#82H $ ;reset entry point ;jump past interrupt vectors ;Timer 0 interrupt vector ;toggle port bit ;Main program entry point ;timer 0, mode 2 ;50 s delay ;start timer ;enable timer 0 interrupt ;do nothing

TOISR:

MAIN:

Program Design Using Interrupts

Example: Two Square Wave Using Timer Interrupts Write a program using interrupts to create a 7 kHz and 500 Hz square wave on P1.7 and P1.6 Solution:
ORG LJMP ORG LJMP ORG LJMP ORG MOV 0 MAIN 000BH T0ISR 001BH T1ISR 0030H TMOD,#12H ;reset entry point ;jump past interrupt vectors ;Timer 0 vector address ;Timer 0 vector address ;Main program entry point ;timer 0 = mode 2 ;timer 1 = mode 1 ;7 kHz using timer 0 ;start timer ;force timer 1 interrupt ;enable both timer interrupts ;do nothing ;toggle port bit

MAIN:

T0ISR: ;

MOV TH0,#-71 SETB TR0 SETB TF1 MOV IE,#8AH SJMP $ CPL P1.7 RETI continued on next page...

Program Design Using Interrupts

Example: Two Square Wave Using Timer Interrupts continued from previous slide...
T1ISR: CLR MOV MOV SETB CPL RETI END TR1 TH1,#HIGH(-1000) TL1,#LOW(-1000) TR1 P1.6 ;stop timer 1 ;1 ms high time (reload) ;1 ms low time ;start timer 1

143 s 71 s

8051 P1.7
2 ms 1 ms

P1.6