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GaN Power Transistor Modeling for High-Speed Converter Circuit Design

Akira Nakajima, Kazuto Takao, and Hiromichi Ohashi, Life Member, IEEE
AbstractA circuit simulator has been developed to design power losses of high-frequency power converters using GaN-based heterojunction eld-effect transistors (GaN-HFETs). The simulator is based on a high-accuracy equivalent model of GaN-HFETs with peculiar device physics and high-speed loss calculation methods. The simulated power losses were consistent with measured results in dcdc converters constructed by a GaN-HFET and a SiC Schottky diode with more than 93% accuracy. By utilizing the developed simulator, key requirements in heat-dissipation technologies, circuit parasitic inductances, and gate-drive technologies for next-generation converters are discussed. Index TermsGaN, heterojunction eld-effect transistor (HFET), power converters, semiconductor device modeling.

I. I NTRODUCTION HE OUTPUT power densities of electric power converters have linearly increased by two orders of magnitude over the last 30 years [1]. The power density increment has been mainly achieved by a switching frequency increment of semiconductor power devices to reduce sizes of passive components and power loss reduction to miniaturize heat sink volumes. From the trend, it is expected that high-density converters of more than 50 W/cm3 will be commercialized at around 2020 by further frequency increment and loss reduction. However, a higher switching frequency causes a larger switching loss in general. As a solution of the contradicting requirements, novel power devices using wide band-gap semiconductors, in particular, gallium nitride-based heterojunction eld-effect transistors (GaN-HFETs), are promising candidates as semiconductor switches in next-generation power converters. GaN has the high electric eld strength over 3 MV/cm, which is ten times larger than that of the Si and high-electron mobility more than 1400 cm2 /V s by utilizing the unique polarization properties. As a result, a low ON-resistance with maintaining
Manuscript received July 15, 2012; revised September 13, 2012; accepted October 12, 2012. Date of publication December 21, 2012; date of current version January 18, 2013. This work was supported by a Grant for Advanced Industrial Technology Development in 2011 under Project 11B06003d and a Low power loss nitride device project for communication network under Project P03033 from the New Energy and Industrial Technology Development Organization of Japan. The review of this paper was arranged by Editor N. Arora. A. Nakajima and H. Ohashi are with Advanced Industrial Science and Technology, Tsukuba 305-8568, Japan (e-mail: a-nakajima@aist.go.jp; h.oohashi@aist.go.jp). K. Takao was with Advanced Industrial Science and Technology, Tsukuba 305-8568, Japan. He is now with Corporate Research and Development Center, Toshiba Corporation, Kawasaki 212-8582, Japan (e-mail: kazuto.takao@toshiba.co.jp). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TED.2012.2226180

Fig. 1. (a) Schematic cross section of a typical device structure of GaNHFETs. There are two issues of GaN-HFETs: 1) electron traps cause the current collapse; and 2) punchthrough induces short-channel effects. (b) Equivalent circuit conguration of GaN-HFETs.

high switching speed over the tradeoff limitation of Si-based devices can be obtained in GaN-HFETs. On the other hand, to bring out intrinsic high performances of such wide band-gap devices, total design methodologies, including circuit, magnetic, noise, and thermal designs could play an important role to realize next-generation power converters. For example, as mentioned in this paper, power losses of highfrequency power converters using GaN-HFETs are signicantly inuenced by stray inductances in converter circuits and gatedrive conditions due to high-speed switching capabilities of GaN-HFETs. Recently, we have proposed an equivalent circuit model of GaN-HFETs for exact circuit simulation in power converters [2]. In this paper, we report more details of the equivalent circuit model and parameter extraction methodologies by taking into account peculiar device physics of GaN-HFETs and novel loss calculation methods with short computation time. In addition, we discuss some key issues in power converters using GaN HFETs from calculated results by the developed simulator. II. E QUIVALENT C IRCUIT M ODEL OF GaN HFETS Fig. 1(a) shows a simplied schematic of conventional GaN-HFETs. GaN power devices are generally fabricated in a several-micrometer-thick AlGaN/GaN layer structure on a heterogeneous substrate such as silicon, silicon carbide (SiC), and sapphire substrates. High-density 2-D electron gas (2DEG)

0018-9383/$31.00 2012 IEEE

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TABLE I C HARACTERISTICS AND G ATE -D RIVE C ONDITIONS OF M EASURED D EVICES

Fig. 3. (a) Measured Id Vds characteristics. (b) OFF-state leakage current of a GaN-HFET. Fig. 2. Gatedrain capacitance values of a GaN-HFET measured in dc and pulsed bias conditions. The inserted gure shows a comparison of measured capacitance values of a GaN-HFET and a Si-MOSFET in dc bias conditions.

over 1013 cm2 is generated at the AlGaN/GaN heterointerface automatically without intentional impurity doping by spontaneous and piezoelectric polarization effects. A 2DEG mobility reaches intrinsic bulk mobility of 1400 cm2 /V s due to low-impurity scatterings. As a result, a low area-specic ON -resistance can be obtained in a GaN-HFET. GaN-HFETs are kinds of n-channel lateral-type unipolar transistors. We have applied a commonly used equivalent circuit conguration shown in Fig. 1(b) as a GaN-HFET model. The equivalent model is constructed with four parameters of a gatesource capacitance Cgs , gatedrain capacitance Cgd , drainsource capacitance Cds , and current source Ich . Specic features of GaN-HFETs need to be claried to develop accurate equivalent models. We have measured commercially available GaN-HFETs and Si-MOSFETs shown in Table I and observed two peculiar futures or issues of GaNHFETs. One is well known that reversible 2DEG density degradation and recovery behaviors caused by a dc stress applied to the drainsource voltage, which is originated by electron traps at the AlGaN barrier surface and in the low-quality buffer of the epilayer/substrate interface, as illustrated in Fig. 1(a). These voltage stress effects are commonly observed in GaNHFETs and referred to as current collapse [3]. This device phenomenon induces the ON-resistance increment observed in pulsed measurements after applying a dc voltage stress in comparison with a resistance measured in simple dc bias conditions [4]. In addition, we have found that the current collapse enhances breakdown voltage [5] and reduces device capacitance values, as described in the succeeding discussion. Fig. 2 shows the measured gatedrain capacitance values Cgd in dc and pulsed bias conditions after applying dc stress voltages

Vst of 44 and 85 V. As shown in Fig. 2, the measured Cgd characteristics depend on the Vst . The inserted graph in Fig. 2 is a comparison of the GaNHFET and Si-MOSFET capacitance values measured in dc bias conditions. The measured Cgd of the GaN-HFETs was one order of magnitude smaller than the Si device capacitance. A transistor switching speed is mainly restricted by a Miller capacitance Cgd . The low Cgd characteristic of the GaN-HFET indicates high switching-speed capabilities of the devices. The other feature of GaN-HFETs is the drain-current characteristics with short-channel effects. Fig. 3(a) shows the measured Id Vds characteristics of the GaN-HFET. The sourcegate distance and the gate length are 1.2 and 0.8 m, respectively. The drain current is strongly depending on the Vds unless in the saturation region. Unlike Si devices, gate regions of GaN-HFETs are generally fabricated on a nondoped or high-resistive GaN layer and not p-type, as illustrated in Fig. 1(a). Therefore, conventional GaN-HFETs are vulnerable to punchthrough effects between the source and drain regions. These effects are particularly signicant in GaN-HFETs with a short gate length [6]. In next-generation GaN power devices, some technologies to prevent short-channel effects could become important to minimize channel resistance. For example, Mg, Fe, and C doping techniques in a GaN epilayer under gate regions have been reported [7], [8]. These impurities act as shallow or deep acceptors and enhance carrier connement at AlGaN/GaN interfaces. However, their effects to the current collapse and channel mobility are still not clear [9], [10]. In addition, insertion of an AlGaN layer under gate regions has been proposed to the enhanced carrier connement [11]. Fig. 3(b) shows an OFF-state drain leakage characteristic of the GaN-HFET measured by a curve tracer. Although the GaN-HFETs show the unsaturated Id Vds characteristics in the ON -state, the OFF-state leakage current was less than 0.1 mA and an OFF-state power loss can be negligible.

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Fig. 4. Equivalent circuit of a dcdc converter (chopper) with key stray parameters.

To reect the current collapse and short-channel effects in the equivalent circuit model illustrated in Fig. 1(b), we have extracted the model parameters of Cgs , Cgd , and Ich after applying a stress voltage Vst , which is corresponding to an OFF-state drainsource voltage in circuit simulations. In addition, the unsaturated drain-current characteristics due to shortchannel effects are taken into account in the current source Ich . III. C IRCUIT S IMULATION M ETHOD Original circuit simulation programs have been developed to evaluate power losses in converters using GaN-HFETs based on the equivalent GaN device model described in the previous section. The equivalent parameter values are individually tabulated and directly inputted into the circuit simulator as look-up tables. In the developed simulator, loss calculation methods are simplied and specialized for each converter circuit topologies. As an example, a loss calculation method in hard-switching dcdc choppers is given as follows. Fig. 4 shows an equivalent circuit of a dcdc chopper with key parasitic parameters; an equivalent resistance Rs1 and inductance Ls1 of the input decoupling capacitor, stray inductances (Ls2 , Ls3 and Ls4 ) of the circuit board and semiconductor device packages, a stray capacitance Cs1 of the free-wheeling diode, stray capacitance values (Cs2 , Cs3 , and Cs4 ) of the main switch, and an internal resistance Rs2 of the gate driver. The total circuit loss Ptotal is given by a sum of conduction losses and switching losses, i.e., Ptotal = Pswitch + Pdiode + Pstray + f (Eon + Eo + Egate ) (1)
Fig. 5. Schematic switching waveforms of drain current id , drainsource voltage vds , and diode voltage vdi during (a) turn-on and (b) turn-off periods.

The conduction losses of Pswitch , Pdiode , and Pstray can be directly calculated from the resistances and the output current IOUT by the Ohms law. An important challenge is accurate evaluation of the switching losses in a short computation time. Fig. 5 shows the schematic switching waveforms during the turn-on and turn-off periods. As illustrated in Fig. 5(a), the Eon is divided into two parts given by Eon = Eon-t + Eon-r (2)

where Eon-t is a time-dependent turn-on energy during t = t1 to t2 , and Eon-r is a residual resonance energy after t = t2 . In the developed simulator, switching waveforms are numerically calculated only in t1 t2 and t3 t4 to minimize the calculation time. From the calculated waveforms, the Eon-t is evaluated by
t2

Eon-t =
t1

id (t) vds (t)dt.

(3)

The Eon-r is the residual energy excessively absorbed by the diode capacitance Cdi and the stray parameters Cs1 and Ls . It can be analytically estimated by
VIN

where Pswitch , Pdiode , and Pstray are conduction losses of the main switch, the diode and the parasitic resistances, respectively; f is the switching frequency; and Eon , Eo , and Egate are the turn-on energy, the turn-off energy, and the gate-drive energy of the main switch, respectively.

Eon-r =
Vdi2

(Cdi + Cs1 )(VIN Vdi )dVdi + 1 Ls (IOUT Id2 )2 2 (4)

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Fig. 6.

Measured system.

where Vdi2 and Id2 are a diode voltage and a drain current at t = t2 . In a similar manner, the turn-off energy is calculated by Eo = Eo -t + Eo -r (5)

where Eo -t is the time-dependent turn-off energy, and Eo -r is the residual resonance energy. They are given by
t4

Eo -t =
t3

id (t) vds (t)dt (Coss + Cs2 + Cs3 )VIN dVds

(6)

VIN

Eo -r =
Vds4

1 2 Ls I d 4 2

(7)
Fig. 7. (a) (Plots) Measured and (lines) simulated switching losses of GaNHFETs with the changing output current values. (b) Switching loss comparison between a GaN-HFET and a Si-MOSFET.

where Vds4 and Id4 are a drain voltage and a drain current at t = t4 . Finally, the gate loss is evaluated using Egate = |Vgh Vgl | Qgate (8)

where Qgate is the gate charge, and Vgh and Vgl are the ONstate and the OFF-state output voltages of the gate driver, respectively. IV. E XPERIMENTAL V ERIFICATION Switching losses of power converters using the GaN-HFETs were experimentally measured and compared with simulated results to verify accuracy of the equivalent circuit model and the loss calculation methods. The device characteristics and the gate-drive conditions are summarized in Table I. A circuit topology is the hard-switching dcdc chopper, as illustrated in Fig. 4. A SiC Schottky barrier diode was used as a freewheeling diode. Fig. 6 shows a photograph of our experimental setup. The circuit parameters of the input voltage VIN , the output current IOUT , the external gate resistance Rg,ex , and the stray inductance Ls2 are adjustable in the measurement system. In this paper, VIN was xed at 40 V, and switching losses were measured by the changing of IOUT , Rg,ex , and Ls2 . The parasitic parameter values were measured using a LCR meter; Rs1 = 0.4 , Cs2 = 24 pF, Cs3 = 0.03 pF, and Cs4 = 21 pF, which include the capacitance values of the measurement probes. For the circuit simulation, the measured parasitic parameters were directly inputted into the simulator. The parasitic parameters of Rs2 , Cs1 , and Ls3 could not be measured in our experimental system and are assumed as tting parameters in the circuit simulations. Fig. 7(a) shows the measured and simulated switching losses at Ls2 = 40 nH and 140 nH with the changing output current

values from 0.5 to 4.0 A. As shown in Fig. 7(a), the measured switching losses are affected by the stray inductance values and Eon-t and Eo -t became smaller and larger at the higher inductance of 140 nH, respectively. Fig. 7(b) shows the measured and simulated switching losses with changing of the external gate resistance. As shown in Fig. 7(a) and (b), the simulated results based on the equivalent GaN-HFET model and the calculation methods well reproduce the measured results for the wide current and gate resistance ranges. The simulation accuracy was more than 93% in all the measured conditions. The measured and simulated switching losses in a dcdc chopper with the Si-MOSFET are also plotted in Fig. 7(b). Detail simulation methods of Si-MOSFETs have been previously reported [12]. Although the GaN-HFET shows six to eight times smaller switching losses than the Si-MOSFETs losses in the same Rg,ex condition, the losses strongly depend on the drive condition. These results imply that high-speed gate-drive technologies with low-output impedances are also important to realize ultralow loss converters using GaN devices. V. O PTIMIZATION OF H IGH -F REQUENCY C ONVERTER Power converters using GaN-HFETs can be designed with stray parameters and drive condition effects by using the developed simulator. As an example, in this nal section, we have evaluated the effects in a next-generation dcdc converter with a high-switching frequency of 10-MHz using a 600-V class GaN-HFET. We have designed high-voltage GaN-HFETs virtually by using a commercially available TCAD simulator and made

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Fig. 9. (a) Simulated conversion efciencies depending on current density by changing a gate resistance. (b) Optimized values at the maximum efciencies. Ls1 + Ls2 and Ls3 are assumed at 2 nH and 0 nH, respectively.

Fig. 8. (a) Schematic of a 600-V class GaN-HFET designed by TCAD simulations. (b) Extracted ON-state and (c) OFF-state Id Vds characteristics. (d) Capacitance characteristics of the GaN-HFET by TCAD.

their equivalent circuit models. Fig. 8(a) shows a schematic structure of a simulated GaN-HFET rated 600 V. The layer structures consist with an undoped-Al0.2 Ga0.8 N layer, a

3-m-thick undoped GaN layer, and an AlN buffer layer on a conductive Si substrate. In this simulation, we have assumed no electron traps in the devices. The physical parameters are assumed to be as follows: the impact ionization coefcient of GaN is 2.9 108 exp(3.4 107 /E) [13], the polarization charge density is 1.1 1013 cm2 at the AlGaN/GaN heterointerface [14], and the 2DEG mobility is the intrinsic bulk mobility of 1400 cm2 /V s [15]. Fig. 8(b) and (c) shows the extracted Id Vds , the OFFstate breakdown, and the capacitance characteristics by TCAD simulations. The gatesource threshold voltage is 6 V, the breakdown voltage is over 600 V, and the ON-resistance is 50 m with a 0.8-mm2 chip size. The extracted values are inputted into the developed circuit simulator as an equivalent model of the GaN-HFET. Circuit simulations are performed in a hard drive dcdc chopper circuit illustrated in Fig. 4 at VIN = 300 V, Vgh = 0 V, Vgl = 10 V, and a duty ratio of 0.5. In these calculations, to understand the effects of gate-drive conditions and stray inductances, we have assumed simplied circuit conditions; a free-wheeling diode is an ideal diode with a constant junction capacitance of 10 pF and the stray inductance Ls4 is zero, and the stray capacitance values (Cs1 , Cs2 , Cs3 , and Cs4 ) and resistances (Rs1 and Rs2 ) are zero. First, gate resistance effects to total circuit losses are simulated at a low stray inductance condition with Ls1 + Ls2 = 2 nH and Ls3 = 0 nH. Fig. 9(a) shows the simulated conversion efciencies with changing current density (= IOUT /chip

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rating and short-circuit capability of semiconductor devices are limited by an allowable chip temperature. The simulated results indicate that novel heat-dissipation technologies with a low thermal impedance are required to realize such high-efciency power converters using GaN devices. Then, stray inductance effects are evaluated at the optimized condition of Rg,ex = 1 and IOUT = 12 A. Fig. 10(a) shows the simulated total switching energy Esw , which is a sum of Eon , Eo , and Egate . As shown in this gure, Esw is undulated depending on the stray inductance values due to interactions between the devices and the stray inductances. In particular, the common source inductance Ls3 signicantly effects to the total switching loss. Only a small Ls3 of 0.5 nH increased the switching loss in four times than that in the ideal condition at Ls3 = 0 nH. As a result, total conversion efciencies shown in Fig. 10(b) are signicantly depending on the stray inductance Ls3 . Although the switching loop inductance Ls1 + Ls2 has little effect to Esw , the surge voltage Vsrg to the GaN-HFET during turn-off is increased depending on the switching loop inductance, as shown in Fig. 10(c). In the simulated condition, the surge voltage reached the voltage rating of 600 V at Ls1 + Ls2 = 15 nH. VI. S UMMARY We have developed the circuit simulator specialized to evaluate power losses of high-frequency power converters using GaN-HFETs. The developed simulator is based on the highaccuracy equivalent model of GaN-HFETs and the parameter extraction methods reecting the current collapse and shortchannel effects. In addition, novel loss calculation methods are proposed for high-speed loss evaluation. The calculated losses of the developed simulator well reproduced the measured results in the dcdc converters using the commercially available GaN-HFETs rated 180 V in more than 93% accuracy. The 10-MHz dcdc converter using the 600-V class GaNHFET is designed by utilizing the developed simulator. These results indicate that high-power and high-speed gate driving, stray inductances reduction, and advanced heat-dissipation technologies beyond conventional technologies are required for realization of next-generation converters using GaN devices.
Fig. 10. (a) Simulated switching loss. (b) Conversion efciency. (c) Surge voltage at Rg,ex = 1 and IOUT = 12 A.

ACKNOWLEDGMENT size). There is an optimum current density to achieve the maximum efciency depending on the external gate resistance Rg,ex . The evaluated maximum efciencies and the optimum current densities are plotted in Fig. 9(b). As shown in this gure, the conversion efciency and optimized current density strongly depend on the gate resistance. When Rg,ex was less than 1 , high conversion efciencies more than 98% were estimated. At Rg,ex = 1 , the optimum current density was 1630 A/cm2 (IOUT = 12 A). In this condition, the peak gate current of (Vgh Vgl )/Rg,ex reaches to 10 A, which is comparable with the output current of 12 A in the main circuit. In addition, an evaluated heat density in the GaN device chip was 3390 W/cm2 , which is one order of magnitude higher than that of conventional Si-IGBTs. In real applications, a current The authors would like to thank Dr. M. Shimizu and K. Owada of the National Institute of Advanced Industrial Science and Technology for the fruitful discussions. R EFERENCES
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Akira Nakajima received the Ph.D. degree in electronics from Toyohashi University of Technology, Japan, in 2004. He is with the Energy Technology Research Institute, National Institute of Advanced Industrial Science and Technology, Japan.

Kazuto Takao received the Ph.D. degree in energy science from Toyama University, Toyama, Japan, in 2002. He is currently with the Electron Devices Laboratory, Corporate Research and Development Center, Toshiba Corporation, Kawasaki, Japan.

Hiromichi Ohashi (LM12) received the Ph.D. degree in electronics from Tohoku University, Sendai, Japan. He is with the Energy Technology Research Institute, National Institute of Advanced Industrial Science and Technology, Tsukuba, Japan.