Design of a CDMA System in FPGA Technology

S. M. Bererber, C. Wang and K. K. Wei

Department of Electrical and Computer Engineering
University of Auckland
Auckland, New Zealand
s.berber@auckland.ac.nz, jwan132@ec.auckland.ac.nz and kwei005@ec.auckland.ac.nz


AbstractThis paper presents the design and implementation of
a chaos-based code division multiple access (CDMA) system in
FPGA (field programmable gate array) technology. A chaos-
based CDMA system uses chaotic sequences as spreading codes
to encode each users message. The users message can again be
separated by the orthogonal property of chaotic sequences at the
receiver. Chaos-based communication systems offer higher
security than conventional CDMA systems. The system is
implemented in Altera Cyclone EP1C20 Nios II Development
Board. This paper also presents a system performance analysis
by obtaining BER (bit error rate) results from the prototype,
computer software simulation and theoretical calculation. The
effects of changing the number of users, spreading factor and the
inclusion of FIR (finite impulse response) filters on the system
performance have been investigated. Real-time transmission of
music signals is demonstrated using the prototype implemented
in Altera APEX20KE DSP Development Board.
Keywords- Bit error rate (BER), code division multi-access,
chaos, field programmable gate arrays.
I. INTRODUCTION
Over the past five to ten years, communication systems
have been developing rapidly especially in the wireless and
cellular network arena [1]. As user demand grows,
conventional communication systems such as time-division-
multiple-access (TDMA), frequency-division-multiple-access
(FDMA) and space-division-multiple-access (SDMA) are
becoming inadequate for some application in todays
communication requirements. Consequently, a new system
called code-division-multiple-access (CDMA) is proposed to
replace the aforementioned systems. This new system utilises
the spread spectrum technique where the message signals can
occupy both the time and frequency domains simultaneously,
thus the system capacity is significantly increased. CDMA
system also offers mitigation to multi-path fading, reduction in
frequency planning and signal quality sharing between users
[1], [2]. FPGA (field programmable gate arrays) nowadays
offer fast code evaluation speed over a PC-based environment.
This allows the generation of BER results in a fast and efficient
way. Also, it allows the prototyping of a realistic CDMA
system. The BER results of the hardware are compared against
the ones obtained from software simulation and the theory. The
objective in this project is to firstly develop a transceiver
structure for the CDMA system based on chaos-phase-shift-
keying (CPSK) modulation scheme in FPGA. Secondly, to
evaluate the system performance by examining the BER curves
under various scenarios. Finally, we are to demonstrate real-
time signal transmission which includes voice and image
transmission.
II. BACKGROUND THEORY OF CDMA
In a direct sequence scheme, the original message symbol
(+1 or -1) is multiplied by sequence of codes. These are
referred to as the spreading codes. Depending on the type of
modulation method, different types of spreading codes are
used. Next, all user encoded messages s
n
(t) are summed up as
s(t) and transmitted through the channel. In our project, we
have included two finite impulse response (FIR) filters at the
transmitter and receiver respectively (Fig. 1). The purpose of
those will be discussed later in Section III. Once the corrupted
composite signal x(t) has reached the receiver, the receiver
decodes the signal into binary sequences.

Figure 1. Overall system schematic.
A. Transmitter
In the CPSK scheme, the spreading sequences are chaotic,
noise-like and non-periodic [3]. Subsequently, the modulated
message signal will also appear chaotic. This contrasts with the
conventional CDMA system, where Walsh functions are used.
The chaotic encoding scheme provides a safer way of
information transfer in a CDMA system compared with Walsh
functions [2], [4].
The modulation process uses the Polar Non Return Zero
(NRZ) coding system. Each user is assigned a different chaotic
sequence which is intended to separate between user messages.
Depending on the initial conditions, each chaotic sequence will
appear differently from one another. The number of chaotic
samples taken during one binary symbol (+1, -1) transmission



m1(t)
m2(t)
mn(t)
m1(t)
m2(t)
mn(t)
AWGN
c1(t)
c2(t)
cn(t)
c1(t)
c2(t)
cn(t)
s(t)
x(t)
n(t)
y1(t)
y2(t)
yn(t)
s1(t)
s2(t)
sn(t)
Transmitter Channel Receiver User
messages
.
.
.
.
.
.
.
.
.
.
.
.
~
~
~
~
FIR FIR
Estimated
user
messages
1550-2252/$25.00 2007 IEEE 3061
period is called the spreading factor. Since chaotic sequences
are sensitive to initial conditions, theoretically there are an
infinite number of different chaotic sequences possible, which
implies that the system is able to accommodate an infinite
number of users. However, inter-user (symbol) interference
increases as the number of users increases, thus the retrieved
signal quality degrades. As a result, infinite number of users is
practically unachievable. For a sequence to be chaotic, it must
be noise-like, non-linear, non-periodic, deterministic, bounded
and sensitive to initial conditions [1]. In our project we have
selected two chaotic generation methods, namely, Logistic and
Piecewise [1].The Logistic method can be described by the
following mathematical expression,
) ( 2 1 ) 1 (
2
n x n x = + (1)
for Piecewise,

+
= +
) 1 ) ( (
) 1 ) ( (
) 1 (
n Bx A
n Bx A
n x
for
for
1 ) ( 0
0 ) ( 1
<
<
n x
n x
(2)
where A and B are parameters which affect the range and
randomness. A was chosen to be 125/128 and B is 2 for the
sequence to appear chaotic [5].
The feasibility of these chaotic generation methods is
examined by their autocorrelation and the cross-correlation
functions. The autocorrelation tells us the degree of similarity
that a function maps on top of itself when a replica is passed
through [2]. The cross-correlation function tells us the
similarity between two different functions. At the receiving
end, we want the maximum autocorrelation to occur when we
multiply the chaotic sequence with the received sequence,
provided the same initial condition is given at the receiver.
Conversely, the minimum cross-correlation anywhere else, is
ideally zero (Fig. 2).
B. Channel
The channel is modelled with an additive white Gaussian
noise (AWGN) model. This model assumes the power spectral
density of the noise is constant and its amplitude follows a
Gaussian distribution [6]. To compute the AWGN model in
practice, the Box-Muller method in conjunction with the
central limit theorem is used [5].
C. Receiver
At the receiver, the corrupted composite signal s(t) (see Fig.
1) is multiplied by the exact spreading code generated at the
transmitter. The product of this produces the decoded signal.
By the aforementioned autocorrelation principle, the product is
a maximum only when the original chaotic sequence is
multiplied with itself. Thus, the original user messages could
be recovered. However, since the demodulation process is done
by multiplying the chaotic chips c
n
(t) with the received
composite signal chips x(t), we need to accumulate all the
immediate products together until the spreading factor is
reached. In a physical sense, a complete binary symbol is
received. To look at the demodulation mechanism from another
perspective, we are essentially calculating the energy of a bit.
When the accumulator has finished collecting all the
intermediate products together, the energy for a binary symbol
is received. The energy of that binary symbol is then compared
with a predetermined threshold value, in our case, zero. Since
the chaotic sequence is inverted if a bit 0 was sent, the product
will be a negative value after multiplying the received signal
with the original chaotic sequence. Therefore, the accumulated
energy will appear negative, which is less than the threshold
value, thus we can deduce that the user message sent was a bit
0. It is important to note that the transmitter and receiver must
be properly synchronised. Otherwise, proper demodulation
would not be possible. In this project, we have assumed perfect
synchronisation between the transmitter and receiver.

Figure 2. Autocorrelation function for Piecewise mapping (top) and its
cross-correlation function (bottom) (Adapted from [5]).
III. FIR FILTER DESIGN
A finite impulse response can be thought of as an infinite
impulse response being windowed, leaving the centre region
with the two tails cut off as shown in Fig. 3. The aim of
incorporating this filter into our system design is to firstly
reduce the transmission bandwidth at the transmitter so it uses
less channel resources. Secondly, it is desirable to reduce the
level of noise presented at the receiver.
At the transmitter, this filter shapes the rectangular pulses
into smoothed waveforms (Fig. 4). By smoothing the sharp
edges of the rectangular pulses, the bandwidth is significantly
reduced. At the receiver, we sample the received chips at time
instances which correspond to the original rectangular pulses to
recover the original chip code.
In this project we have designed our FIR filters to have 24
filter taps which means that there are 24 points to represent the
finite impulse response (Fig. 3). Each tap corresponds to a filter
coefficient which approximates the ideal filter response. A
n, time index
n, time index
a
m
p
l
i
t
u
d
e

a
m
p
l
i
t
u
d
e

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higher number of taps indicates a closer approximation of the
ideal filter response, which also implies higher complexity. The
filter coefficients were calculated by the following formula [7]:

) (
)) ( sin(
] [
2
2
L
L
d
n
n
n h

(3)
where n is the n
th
tap coefficient of the filter and L is the total
number of taps.

Figure 3. Impulse response for truncated precision and without truncation.

Figure 4. Original PN code and shaped PN code.
IV. HARDWARE IMPLEMENTATION
The target FPGA device is the Altera Cyclone EP1C20
Nios II Development Board. The Altera Cyclone device is
chosen for this project because system performance analysis
tools can be developed with ease by using the Nios II processor.
Furthermore, system-on-a-programmable-chip (SOPC) builder
and Ethernet interface are available with Nios II Development
boards [5]. The hardware is designed in Altera Quartus II using
Verilog HDL, VHDL and schematic design entry. The
complexity of the prototype depends on the hardware resources
that are available on the FPGA device. Some hardware devices,
such as the Stratix family, have DSP (digital signal processing)
blocks that can be implemented into efficient multipliers and
adders, and thus avoid the implementation of these functional
blocks using logic elements [8]. Cyclone does not have DSP
blocks, but it has M4K blocks that can be used to implement
soft multipliers.
A. CPSK Transceiver
The main functional blocks of a CPSK system have already
been implemented by the previous Part 4 Project students who
worked in this topic, and these include chaotic sequence
generators, AWGN noise generator and receiver structure. The
functional blocks are modified to include low pass FIR filters
into the CDMA system. Table I summarises the major
functional blocks in the transceiver structure, the number of
logic elements required by each functional block and their
corresponding maximum clock speed. These functional blocks
are synthesised in both Cyclone device and Stratix device to
show how hardware resources are utilised in different FPGA
devices. Note how DSP blocks in the Stratix device
significantly reduce the number of logic elements.
TABLE I. HARDWARE RESOURCE UTILISATION IN CYCLONE EP1C20
DEVICE AND STRATIX EP1S25 DEVICE
Cyclone Stratix
Functional
blocks LE
Max.
clock
speed
(MHz)
LE
Max.
clock
speed
(MHz)
DPS
blocks
( /80)
WGN generator 1393 40 1269 48.31 4
Correlation
demodulator
1961 61.64 575 77.33 8
Piecewise
chaotic
sequence
generator
1855 50.72 132 62.64 9
Logistic
sequence
generator
294 30.84 185 44.92 16
FIR filter 1570 27.77 630 30.61 56
B. FIR Filter
A low pass FIR filter with 24 signal taps and a sampling
rate of four times faster than the chip rate was initially
developed. A study has also been carried out to investigate the
effect that limited precision in representing filter coefficients in
FPGA has on the filter characteristics. The method used here is
to find the mean square error between the theoretical filter
coefficients and the coefficients truncated to certain precision.
The mean squared error can be calculated by

[ ]

=

0 k
2
0 s
03 . 0 ) ( h ) - T h( k k
(4)
where the tap spacing is T
s
= T
c
/4, h(k) is the ideal filter
coefficient, h
0
(k) is the approximated filter coefficient, and
and may be selected to minimise the mean square error [7]. In
the case where the value of and are chosen to be ones for
simplicity, it is found that at least 8-bit precision is required to
meet the mean square error criterion.
However the FIR filter requires a large number of logic
elements. As a result the CDMA system with the inclusion of
FIR filters exceeded the hardware capacity of the FPGA device
therefore the FIR filter is redesigned. The complexity of FIR
filter is reduced down to only having nine signal taps as shown
in Fig. 5. The filter coefficients are represented with a precision
of 8 bits, with one extra bit allocated to sign bit. Fixed point
arithmetic involving multiplication and addition was
implemented using wizard generated components provided by
T
c


a
m
p
l
i
t
u
d
e

n, time index
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the Altera Megafunctions to make the best utilisation of
hardware resources on the Cyclone device. One disadvantage
of this is that the hardware design is not portable for
implementation into non-Altera FPGA devices. The results of
multiplying the sample values with the filter coefficients are
also truncated to whole numbers. This is done again to simplify
the FIR filter structure and to make the input/output of the FIR
filter compatible with the rest of the transceiver structure.

Figure 5. Basic structure of FIR filter implemented in FPGA.

Figure 6. Music demonstration setup.
C. Design for Music Transmission
The CPSK system is implemented in Altera APEX20KE
DSP development board to demonstrate real-time transmission
of audio signals. The APEX20KE board has two built-in 10 bit
ADC (analog to digital converter) and two 10 bit DAC (digital
to analog converter). This allows a two-user CDMA system to
be implemented. The author also looked at the possibility of
implementing the music demonstration in a newer FPGA
device called Stratix EP1S25 DSP Development Board. It is
found that the device has two levels of transformers between
the analog input port and the ADC device. Thus the board can
only accept with the signals higher than 1MHz and is not
suitable for converting audio signals. External ADC would
have to be constructed to perform this conversion if one wishes
to implement music demonstration onto the Stratix EP1S25
device.
The music demonstration setup is shown in Fig. 6. The two
analog inputs can be connected to any music sources, and in
the case shown in Fig. 6 are an MP3 player and a computer
source. The two analog outputs are connected to two separate
speakers so that the original music signals can be heard in
different speakers. The implemented system runs at a clock
speed of 20MHz and a transmission bit rate of 200kbps when a
spreading factor of 100 is used. Because the CDMA system
transmits the bits serially and it takes 10 bits for one sample to
be completely transmitted, the sampling rate is reduced down
to 20 kHz. The implemented system also has adjustable noise
levels that can be programmed by the user to show how signal
quality is affected by different noise levels.
V. PERFORMANCE
The system performance is evaluated by viewing at the bit
error rate (BER) curves. The BER is defined as the total
number of error bits received over the total number of bits sent:

sent bits of number total
received bits error of number total
BER


=
(5)
As the Eb/No increases, the noise level decreases, therefore
the BER curve decreases which means we have better signal
quality.
A. Addition of FIR Filters
System performance is also evaluated with the
exclusion/inclusion of two low pass FIR filters as shown in Fig.
1. The result is provided in Fig. 7.

Figure 7. Effect of FIR filters on BER curves for one and two-user CPSK
systems (Logistic mapping method 2).
Due to time limitations, only experimental results are available.
The experimental results show that system performance
improves when low pass FIR filters are included. For a one-
user system the improvement is significant and for a two-user
system the improvement is very small. FIR filters remove the
noise power that is not in the base-band frequency range,
therefore possibly improve the system performance. The
performance of the system with filters should be evaluated
when proper up/down conversion devices have been included
into the system.
B. Investigation of Spreading Factor
Fig. 8 shows the system performance with the spreading
factors 32, 64, 100 and 128. It is clearly shown that as the
spreading factor increases, the BER decreases which means
that the system performs better. This is because as the
spreading factor increases, the more samples there are in a bit,
which can represent the energy of a bit more precisely.
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However, large spreading factor means slow transmission rate
for the system.
C. Improved Gaussian-Approximation BER
The improved Gaussian-Approximation BER formula [9] is
given below,

( )
) (
1
2 ) (
1
2
1
1
1
1
2
1
2
) (
) (
) ( 1
1
)
) 1 (
(
2
1
g
g
o
k
g
k
g
dx
x
N
x
N
erfc p

(
(
(
(
(
(

|
|
|
|
|
|
.
|

\
|
+

(6)
where g denotes the g
th
user, N is the total number of users
in the system,
2
is the spreading factor and
k
x
is the k
th

chaotic sample. This formula takes account of all the initial
conditions from -1 to 1 and calculates the energy of all possible
chaotic sequences for that mapping method. This formula
provides a more accurate estimation of the exact BER curve
especially when the spreading factor is low (Fig. 9).
This formula reduces the exact BER formula from
1
2
N
N
dimensional integral to a 1-dimensional, which can be
computed quite easily on a PC using software packages such as
Matlab [9].

Figure 8. Four users Piecewise mapping at different spreading factors.

Figure 9. System performance for 2 and 4 users Logistic mapping.
VI. CONCLUSIONS
It is concluded that a transceiver structure of the CDMA
system using CPSK modulation scheme was implemented in
FPGA using the Cyclone EP1C20F400C7 development board.
It was shown that the use of DSP blocks can significantly
reduce the number of logic elements which can be used to
further expand system functionalities. Therefore, it is suggested
that a hybrid hardware prototype including DSP blocks and
FPGA would be an ideal hardware platform for implementing
the system. Also, it is desirable to incorporate soft-core design
into the hardware design to allow for logic elements reduction.
The addition of FIR filters provides a better system
performance, however, because as inter-user interference
increases, the system performs decreases. Therefore,
mechanisms which minimise inter-user interference should be
investigated. The performance of FIR filters should be
evaluated through proper up/down conversion devices. As the
spreading factor increases, the system performs better with
compensated transmission rate and bandwidth requirement.
Real time signal transmission was successfully implemented
using the prototype. Finally, synchronisation between the
transmitter and the receiver is to be investigated.
ACKNOWLEDGMENT
The authors would like to thank their project supervisor, Dr
Stevan Berber, their second examiner, Dr Morteza Biglari-
Abhari and the PhD student Gobindar Sandhu for their
guidance, support and contribution to this project. The author
would also like to thank Jee-Hoon Yang for his help in
clarifying technical issues in this project.
REFERENCES
[1] Lau, F.C.M. and Tse, C. K. (2003) Chaos-based digital communication
systems. Springer Verlag, Berlin.
[2] V.K., Smolik, K. F. and Wilkes, J.E. (1997) Applications of CDMA in
Wireless/Personal Communications. Prentice Hall PTR.
[3] Sandhu, G. S. and Berber, S., Investigation on Operations of a Secure
Communication System based on the Chaotic Phase Shift Keying
Scheme, Proceedings of the Third International Conference on
Information Technology and Applications, vol.2, pp: 584-587, July
2005.
[4] Abel, A. and Shwarz, W., Chaos Communications Principles,
Schemes and System Analysis, Proceedings of the IEEE, vol. 90, No 5,
pp: 691-710, 2002.
[5] Yang, J. H. (2005) A Chaos-Based Multi-User Transceiver Prototyping
Based on FPGA. Part IV Project Final Report, Department of Electrical
and Computer Engineering, The University of Auckland.
[6] Haykin, S. (2001) Communication Systems. Fourth edition. John Wiley
& Sons, New York.
[7] Lee, J. S. and Miller, L. E., (1998) CDMA systems engineering
handbook. Artech House Publishers, Boston.
[8] (2004) Implementing High Performance DSP Functions in Stratix &
Stratix GX Devices. Altera Corporation.
[9] Sandhu, G. S. and Berber, S. M. (2005) Operations and Bit Error Rate
Performance of a Chaos-Based Communication System under the
Influence of AWGN. School of Engineering Report No. 624, The
University of Auckland.
4 users,
spreading factor
= 40
2 users,
spreading
factor = 100
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