HDL Butterworth Filter

This example illustrates how to generate HDL code for a 5th order Butterw orth filter. The cutoff-frequency for this filter is very low relative to the sample rate, leading to a filter that is difficult to make practical. Also, small input (8-bit) and output (9-bit) w ord sizes cause the quantized filter to require scaling to be realizable. Design the Filter Use the CD sampling rate of 44.1 kHz and a cut-off frequency of 500 Hz. First, create the filter design object, then create the double-precision filter. Convert it from the default structure (DF2SOS) to the desired structure, DF1SOS. Finally, examine the response in log frequency using fvtool. F s =4 4 1 0 0 ; F n =F s / 2 ; F 3 d b= 5 0 0 ; f i l t d e s=f d e s i g n . l o w p a s s ( ' n , f 3 d b ' ,5 ,F 3 d b ,F s ) ; H d=d e s i g n ( f i l t d e s , ' b u t t e r ' ) ; H d=c o n v e r t ( H d ,' d f 1 s o s ' ) ; f v t o o l ( H d ,' F s ' ,F s ,' F r e q u e n c y S c a l e ' ,' l o g ' ) ;

Create the Quantized Filter Set the filter object to fixed-point mode to quantize it. Assume 8-bit fixed-point input and output data w ith 12-bit coefficients and 20-bit adders and states. Check the response w ith fvtool. H d . a r i t h m e t i c H d . I n p u t W o r d L e n g t h H d . I n p u t F r a c L e n g t h H d . O u t p u t W o r d L e n g t h H d . O u t p u t M o d e H d . O u t p u t F r a c L e n g t h H d . C o e f f W o r d L e n g t h H d . A c c u m W o r d L e n g t h H d . N u m S t a t e W o r d L e n g t h H d . D e n S t a t e W o r d L e n g t h H d . C a s t B e f o r e S u m H d . R o u n d M o d e H d . O v e r f l o w M o d e =' f i x e d ' ; =8 ; =7 ; =9 ; =' S p e c i f y P r e c i s i o n ' ; =7 ; =1 2 ; =2 0 ; =2 0 ; =2 0 ; =f a l s e ; =' n e a r e s t ' ; =' w r a p ' ;

f v t o o l ( H d ,' F s ' ,F s ,' F r e q u e n c y S c a l e ' ,' l o g ' ) ;

Requantize the Filter In the plot above, fvtool show s that the quantized passband is approximately 2 dB low er than the desired response. Adjust the coefficient w ord length from 12 to 16 to get the quantized response closer to the reference double-precision response and zoom in on the passband response. The quantized filter is now just over 0.1 dB low er than the reference filter. H d . C o e f f W o r d L e n g t h=1 6 ; f v t o o l ( H d ,' F s ' ,F s ,' F r e q u e n c y S c a l e ' ,' l o g ' ) ; a x i s ( [ 01 . 011 ] ) ;

Exam ine the Scale Values A key step for hardw are realization of the filter design is to check w hether the scale values are reasonable and adjust the scale value if needed. First, examine the quantized scale values relative to the input specification--an 8-bit value w ith fraction length of 7 bits. Since the first tw o scale values are smaller than the input settings, most of the input values are quantized aw ay. To correct this, the filter needs to be scaled. s c a l e s=H d . s c a l e v a l u e s. *2 ^ H d . I n p u t F r a c L e n g t h %N o ws c a l et h ef i l t e ru s i n gt h ef r e q u e n c yd o m a i ni n f i n i t yn o r m . s c a l e ( H d , ' L i n f ' ) ; %A f t e rs c a l i n g ,t h es c a l ev a l u ea r ea l lo n ei nt h i sc a s e . s c a l e s=H d . s c a l e v a l u e s s c a l e s= 0 . 1 5 8 9 0 . 1 5 3 6 4 . 4 0 4 3 1 2 8 . 0 0 0 0

s c a l e s=

1 1 1 1

Generate HDL Code from the Quantized Filter Starting w ith the correctly quantized filter, generate VHDL or Verilog code. You have the option of generating a VHDL or Verilog test bench to verify that the HDL design matches the MATLAB filter. Create a temporary w ork directory. Generate VHDL code for the filter and open the generated file in the editor. To generate Verilog instead, change the value of the property 'TargetLanguage', from 'VHDL' to 'Verilog'. w o r k i n g d i r=t e m p n a m e ; g e n e r a t e h d l ( H d , ' N a m e ' ,' h d l b u t t e r ' ,' T a r g e t L a n g u a g e ' ,' V H D L ' , . . . ' T a r g e t D i r e c t o r y ' ,w o r k i n g d i r ) ; e d i t ( f u l l f i l e ( w o r k i n g d i r ,' h d l b u t t e r . v h d ' ) ) ; # # #S t a r t i n gV H D Lc o d eg e n e r a t i o np r o c e s sf o rf i l t e r :h d l b u t t e r # # #S t a r t i n gV H D Lc o d eg e n e r a t i o np r o c e s sf o rf i l t e r :h d l b u t t e r # # #G e n e r a t i n g :< a h r e f = " m a t l a b : e d i t ( ' C : \ T E M P \ R 2 0 1 3 a d _ 4 7 0 _ 3 8 8 8 \ t p 8 a 8 b 8 3 f e _ b 7 a 9 _ 4 2 a a _ a 8 0 8 _ 8 6 3 b 4 2 9 e 1 7 b 1 \ h d l b u t t e r . v h d ' ) " > C : \ T E M P \ R 2 0 1 3 a d _ 4 7 0 _ 3 8 8 8 \ t p 8 a 8 b 8 3 f e _ b 7 a 9 _ 4 2 a a _ a 8 0 8 _ 8 6 3 b 4 2 9 e 1 7 b 1 \ h d l b u t t e r . v h d < / a > # # #S t a r t i n gg e n e r a t i o no fh d l b u t t e rV H D Le n t i t y # # #S t a r t i n gg e n e r a t i o no fh d l b u t t e rV H D La r c h i t e c t u r e # # #F i r s t o r d e rs e c t i o n ,#1 # # #S e c o n d o r d e rs e c t i o n ,#2 # # #S e c o n d o r d e rs e c t i o n ,#3 # # #H D Ll a t e n c yi s2s a m p l e s # # #S u c c e s s f u lc o m p l e t i o no fV H D Lc o d eg e n e r a t i o np r o c e s sf o rf i l t e r :h d l b u t t e r

Generate a Test Bench from the Quantized Filter Since the passband of this filter is so low relative to the sampling rate, a custom input stimulus is a better w ay to test the filter implementation. Build the test input w ith one cycle of each of 50 to 300 Hz in 50 Hz steps. Generate a VHDL test bench to verify that the results match the MATLAB results exactly. After generating the test bench, open the generated file in the editor. u s e r s t i m=[ ] ; f o rn=[ 5 0 ,1 0 0 ,1 5 0 ,2 0 0 ,2 5 0 ,3 0 0 ] u s e r s t i m=[u s e r s t i m ,s i n ( 2 * p i * n / F s * ( 0 : F s / n ) ) ] ; e n d g e n e r a t e h d l ( H d ,' N a m e ' ,' h d l b u t t e r ' , . . . ' T a r g e t L a n g u a g e ' ,' V H D L ' , . . . ' T a r g e t D i r e c t o r y ' ,w o r k i n g d i r ,. . . ' G e n e r a t e H D L T e s t b e n c h ' ,' o n ' ,. . . ' T e s t B e n c h U s e r S t i m u l u s ' ,u s e r s t i m ) ; e d i t ( f u l l f i l e ( w o r k i n g d i r ,' h d l b u t t e r _ t b . v h d ' ) ) ; # # #S t a r t i n gV H D Lc o d eg e n e r a t i o np r o c e s sf o rf i l t e r :h d l b u t t e r # # #S t a r t i n gV H D Lc o d eg e n e r a t i o np r o c e s sf o rf i l t e r :h d l b u t t e r # # #G e n e r a t i n g :< a h r e f = " m a t l a b : e d i t ( ' C : \ T E M P \ R 2 0 1 3 a d _ 4 7 0 _ 3 8 8 8 \ t p 8 a 8 b 8 3 f e _ b 7 a 9 _ 4 2 a a _ a 8 0 8 _ 8 6 3 b 4 2 9 e 1 7 b 1 \ h d l b u t t e r . v h d ' ) " > C : \ T E M P \ R 2 0 1 3 a d _ 4 7 0 _ 3 8 8 8 \ t p 8 a 8 b 8 3 f e _ b 7 a 9 _ 4 2 a a _ a 8 0 8 _ 8 6 3 b 4 2 9 e 1 7 b 1 \ h d l b u t t e r . v h d < / a > # # #S t a r t i n gg e n e r a t i o no fh d l b u t t e rV H D Le n t i t y # # #S t a r t i n gg e n e r a t i o no fh d l b u t t e rV H D La r c h i t e c t u r e # # #F i r s t o r d e rs e c t i o n ,#1

# # #S e c o n d o r d e rs e c t i o n ,#2 # # #S e c o n d o r d e rs e c t i o n ,#3 # # #H D Ll a t e n c yi s2s a m p l e s # # #S u c c e s s f u lc o m p l e t i o no fV H D Lc o d eg e n e r a t i o np r o c e s sf o rf i l t e r :h d l b u t t e r # # #S t a r t i n gg e n e r a t i o no fV H D LT e s tB e n c h # # #G e n e r a t i n gi n p u ts t i m u l u s # # #D o n eg e n e r a t i n gi n p u ts t i m u l u s ;l e n g t h2 1 6 6s a m p l e s . # # #G e n e r a t i n gT e s tb e n c h : < a h r e f = " m a t l a b : e d i t ( ' C : \ T E M P \ R 2 0 1 3 a d _ 4 7 0 _ 3 8 8 8 \ t p 8 a 8 b 8 3 f e _ b 7 a 9 _ 4 2 a a _ a 8 0 8 _ 8 6 3 b 4 2 9 e 1 7 b 1 \ h d l b u t t e r _ t b . v h d ' ) " > C : \ T E M P \ R 2 0 1 3 a d _ 4 7 0 _ 3 8 8 8 \ t p 8 a 8 b 8 3 f e _ b 7 a 9 _ 4 2 a a _ a 8 0 8 _ 8 6 3 b 4 2 9 e 1 7 b 1 \ h d l b u t t e r _ t b . v h d < / a > # # #C r e a t i n gs t i m u l u sv e c t o r s . . . # # #D o n eg e n e r a t i n gV H D LT e s tB e n c h Generate HDL Code and Test Bench Using FDHDLTool HDL code and its test bench can optionally be generated using the FDHDLTOOL command that opens the dialog that lets you customize and generate Verilog or VHDL code and test benches for a copy of the quantized filter. The GUI is customized to filter 'Hd' in such a w ay that only the relevant w idgets are available for setting. To generate HDL and testbench you should first go to the w orking directory by cd(w orkingdir) and then call the FDHDLTOOL command. f d h d l t o o l ( H d ) You can modify the default settings and click Generate to generate HDL and/or testbench. ModelSim Sim ulation Results The follow ing display show s the ModelSim HDL simulator after running the VHDL test bench. Compare the ModelSim result w ith the MATLAB result below .

x r a n g e=( 0 : l e n g t h ( u s e r s t i m )-1 ) ; y=f i l t e r ( H d ,u s e r s t i m ) ; s u b p l o t ( 2 , 1 , 1 ) ;p l o t ( x r a n g e ,u s e r s t i m ) ; a x i s ( [ 0l e n g t h ( u s e r s t i m )1 . 11 . 1 ] ) ; t i t l e ( ' H D LB u t t e r w o r t hf i l t e ri nS t i m u l u s . ' ) ; x l a b e l ( ' S a m p l e# ' ) ; s u b p l o t ( 2 , 1 , 2 ) ;p l o t ( x r a n g e ,y ) ; a x i s ( [ 0l e n g t h ( u s e r s t i m )1 . 11 . 1 ] ) ; t i t l e ( ' H D LB u t t e r w o r t hf i l t e ro u tR e s p o n s e . ' ) ; x l a b e l ( ' S a m p l e# ' ) ;

Conclusion You designed a double-precision Butterw orth filter to meet the given specification. You then quantized the filter and discovered problems. Requantizing the coefficients and scaling the filter corrected these problems. You then generated VHDL filter code and VHDL test bench. You can use the ModelSim HDL Simulator, to verify these results. You can also experiment w ith VHDL and Verilog for both filters and test benches.