IRFP460, SiHFP460

Vishay Siliconix

Power MOSFET
PRODUCT SUMMARY
VDS (V) RDS(on) () Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 10 V 210 29 110 Single
D

FEATURES
500 0.27

Dynamic dV/dt Rating Repetitive Avalanche Rated Isolated Central Mounting Hole Fast Switching Ease of Paralleling Simple Drive Requirements Lead (Pb)-free Available
Available

RoHS*
COMPLIANT

TO-247

DESCRIPTION
G

S D G S N-Channel MOSFET

Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The TO-247 package is preferred for commercial-industrial applications where higher power levels preclude the use of TO-220 devices. The TO-247 is similar but superior to the earlier TO-218 package because its isolated mounting hole. It also provides greater creepage distances between pins to meet the requirements of most safety specifications.

ORDERING INFORMATION
Package Lead (Pb)-free SnPb TO-247 IRFP460PbF SiHFP460-E3 IRFP460 SiHFP460

ABSOLUTE MAXIMUM RATINGS TC = 25 C, unless otherwise noted

PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque VGS at 10 V TC = 25 C TC = 100 C SYMBOL VDS VGS ID IDM EAS IAR EAR PD dV/dt TJ, Tstg LIMIT 500 20 20 13 80 2.2 960 20 28 280 3.5 - 55 to + 150 300d 10 1.1 UNIT V

A W/C mJ A mJ W V/ns C lbf in Nm

TC = 25 C

for 10 s 6-32 or M3 screw

Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 50 V, starting TJ = 25 C, L = 4.3 mH, RG = 25 , IAS = 20 A (see fig. 12). c. ISD 20 A, dI/dt 160 A/s, VDD VDS, TJ 150 C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91237 S-81360-Rev. A, 28-Jul-08 www.vishay.com 1

IRFP460, SiHFP460
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER Maximum Junction-to-Ambient Case-to-Sink, Flat, Greased Surface Maximum Junction-to-Case (Drain) SYMBOL RthJA RthCS RthJC TYP. 0.24 MAX. 40 0.45 C/W UNIT

SPECIFICATIONS TJ = 25 C, unless otherwise noted

PARAMETER Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Forward Turn-On Time IS ISM VSD trr Qrr ton MOSFET symbol showing the integral reverse p - n junction diode
D

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

VDS VDS/TJ VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf LD LS

VGS = 0 V, ID = 250 A Reference to 25 C, ID = 1 mA VDS = VGS, ID = 250 A VGS = 20 V VDS = 500 V, VGS = 0 V VDS = 400 V, VGS = 0 V, TJ = 125 C VGS = 10 V ID = 12 Ab Ab

500 2.0 13

0.63 -

4.0 100 25 250 0.27 -

V V/C V nA A S

VDS = 50 V, ID = 12

VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5

4200 870 350 18 59 110 58 5.0 13

210 29 110 nH ns nC pF

VGS = 10 V

ID = 20 A, VDS = 400 V see fig. 6 and 13b

VDD = 250 V, ID = 20 A , RG = 4.3 , RD = 13 , see fig. 10b

Between lead, 6 mm (0.25") from package and center of die contact

570 5.7

20 A 80 1.8 860 8.6 V ns C

TJ = 25 C, IS = 20 A, VGS = 0

Vb

TJ = 25 C, IF = 20A, dI/dt = 100 A/sb

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 s; duty cycle 2 %.

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Document Number: 91237 S-81360-Rev. A, 28-Jul-08

IRFP460, SiHFP460
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 C, unless otherwise noted

ID, Drain Current (A)

ID, Drain Current (A)

15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V

Top

VGS

150 C

101 4.5 V

101 25 C

100
91237_01

20 s Pulse Width TC = 25 C 100 101

100 4
91237_03

20 s Pulse Width VDS = 50 V 5 6 7 8 9 10

VDS, Drain-to-Source Voltage (V)

Fig. 1 - Typical Output Characteristics, TC = 25 C

VGS, Gate-to-Source Voltage (V)

Fig. 3 - Typical Transfer Characteristics

ID, Drain Current (A)

101

VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V Top

RDS(on), Drain-to-Source On Resistance (Normalized)

3.5 3.0 2.5 2.0 1.5 1.0 0.5

ID = 20 A VGS = 10 V

4.5 V

100 100
91237_02

20 s Pulse Width TC = 150 C 101

0.0 - 60 - 40 - 20

0 20

40 60 80 100 120 140 160

VDS, Drain-to-Source Voltage (V)

91237_04

TJ, Junction Temperature (C)

Fig. 2 - Typical Output Characteristics, TC = 150 C

Fig. 4 - Normalized On-Resistance vs. Temperature

Document Number: 91237 S-81360-Rev. A, 28-Jul-08

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IRFP460, SiHFP460
Vishay Siliconix

10 000

8000

6000

Ciss

4000 Coss

ISD, Reverse Drain Current (A)

Capacitance (pF)

VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd

102

150 C 25 C VGS = 0 V 0.8 1.0 1.2 1.4 1.6 1.8 2.0

2000

Crss 0 100
91237_05

101

101 0.6
91237_07

VDS, Drain-to-Source Voltage (V)

VSD, Source-to-Drain Voltage (V)

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

20

VGS, Gate-to-Source Voltage (V)

ID = 20 A VDS = 400 V VDS = 250 V

103
5

Operation in this area limited by RDS(on)

ID, Drain Current (A)

16

102
5

12 VDS = 100 V 8

10 s 100 s

10
5

4
For test circuit see figure 13
2

1 ms TC = 25 C TJ = 150 C Single Pulse 1

2 5

10 ms 102
2 5

0 0
91237_06

40

80

120

160

200
91237_08

10

103

QG, Total Gate Charge (nC)

VDS, Drain-to-Source Voltage (V)

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 8 - Maximum Safe Operating Area

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Document Number: 91237 S-81360-Rev. A, 28-Jul-08

IRFP460, SiHFP460
Vishay Siliconix
RD VDS VGS D.U.T. + - VDD 10 V
Pulse width 1 s Duty factor 0.1 %

20

RG

ID, Drain Current (A)

16

12

Fig. 10a - Switching Time Test Circuit

8 VDS 4 90 %

0 25
91237_09

50

75

100

125

150 10 % VGS td(on) tr td(off) tf

TC, Case Temperature (C)

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 10b - Switching Time Waveforms

Thermal Response (ZthJC)

0 - 0.5

0.1 0.2 0.1 0.05 0.02 0.01 PDM Single Pulse (Thermal Response) t1 t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC 10-5 10-4 10-3 10-2 0.1 1 10

10-2

10-3

91237_11

t1, Rectangular Pulse Duration (S)

Fig. 11a - Maximum Effective Transient Thermal Impedance, Junction-to-Case

L Vary tp to obtain required IAS RG VDS tp VDD D.U.T IAS 10 V tp 0.01 IAS
Fig. 12b - Unclamped Inductive Waveforms

VDS

+ -

V DD

VDS

Fig. 12a - Unclamped Inductive Test Circuit

Document Number: 91237 S-81360-Rev. A, 28-Jul-08

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IRFP460, SiHFP460
Vishay Siliconix

2400

EAS, Single Pulse Energy (mJ)

2000 1600 1200 800 400 0 VDD = 50 V 25 50 75 100

ID 8.9 A 13 A Bottom 20 A Top

125

150

91237_12c

Starting TJ, Junction Temperature (C)

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

10 V QGS

QG

QGD

VG

Charge

Fig. 13a - Basic Gate Charge Waveform

Current regulator Same type as D.U.T.
50 k
12 V

0.2 F 0.3 F

D.U.T. VGS
3 mA

VDS

IG ID Current sampling resistors

Fig. 13b - Gate Charge Test Circuit

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Document Number: 91237 S-81360-Rev. A, 28-Jul-08

IRFP460, SiHFP460
Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

D.U.T.

Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer

+ +

RG

dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test

+ VDD

Driver gate drive P.W. Period D=

P.W. Period VGS = 10 V*

D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt

VDD

Re-applied voltage Inductor current

Body diode forward drop

Ripple 5 %

ISD

* VGS = 5 V for logic level devices

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91237.

Document Number: 91237 S-81360-Rev. A, 28-Jul-08

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Package Information
www.vishay.com

Vishay Siliconix

TO-247AC (High Voltage)

4 B 3 R/2 Q 2xR (2) 1 5 L1 C L See view B 2 x b2 3xb 0.10 M C A M 2x e b4 A1 Planting Lead Assignments 1. Gate 2. Drain 3. Source 4. Drain D DE E C C (c) c1 (b, b2, b4) View B (4) Section C - C, D - D, E - E (b1, b3, b5) Base metal C A 4 E1 0.01 M D B M View A - A 2 3 4 D D Thermal pad 4 E E/2 S A2 A D2 4 D1 A 7 P k M DBM A (Datum B) P1

MILLIMETERS DIM. MIN. MAX. A 4.58 5.31 A1 2.21 2.59 A2 1.17 2.49 b 0.99 1.40 b1 0.99 1.35 b2 1.53 2.39 b3 1.65 2.37 b4 2.42 3.43 b5 2.59 3.38 c 0.38 0.86 c1 0.38 0.76 D 19.71 20.82 D1 13.08 ECN: X13-0103-Rev. D, 01-Jul-13 DWG: 5971

INCHES MIN. MAX. 0.180 0.209 0.087 0.102 0.046 0.098 0.039 0.055 0.039 0.053 0.060 0.094 0.065 0.093 0.095 0.135 0.102 0.133 0.015 0.034 0.015 0.030 0.776 0.820 0.515 -

DIM. D2 E E1 e k L L1 N P P1 Q R S

MILLIMETERS MIN. MAX. 0.51 1.30 15.29 15.87 13.72 5.46 BSC 0.254 14.20 16.25 3.71 4.29 7.62 BSC 3.51 3.66 7.39 5.31 5.69 4.52 5.49 5.51 BSC

INCHES MIN. MAX. 0.020 0.051 0.602 0.625 0.540 0.215 BSC 0.010 0.559 0.640 0.146 0.169 0.300 BSC 0.138 0.144 0.291 0.209 0.224 0.178 0.216 0.217 BSC

Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Contour of slot optional. 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body. 4. Thermal pad contour optional with dimensions D1 and E1. 5. Lead finish uncontrolled in L1. 6. P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154"). 7. Outline conforms to JEDEC outline TO-247 with exception of dimension c. 8. Xian and Mingxin actually photo.

Revision: 01-Jul-13

Document Number: 91360 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant. Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards.

Revision: 02-Oct-12

Document Number: 91000