An Analog Floating-Gate Memory in a Standard Digital Technology

Tor Sverre Lande', Htzssan Ranj bar', Mohammed Ismai12 and Yngvar Berg'
1 . Dept. of InfoTmatics, University of Oslo, OSLO, NORWAY 2 . Dept. Elec. Eng., Ohio State Univ., USA and on leave at The Helsinki Univ. of Technology, Finland

E-mail: bassenQif i .uio .no

Abstract
I n this paper we present a simple CMOS analog memory structure using the floating gate of a MOS transistor. The structure is based o n a special but simple layout which allows significant tunneling at relatively low voltage levels. The programming of the m e m ory is achieved using the standard Fowler-Nordheim tunneling and is implemented in a standard digital CMOS process with only one polysilicon layer. A simple on-chip memory driver circuit is also presented. Experimental results f r o m test chips fabricated in a standard %micron CMOS process show sia: orders of magnitude dynamic range in current f o r subthreshold operation.

1: Introduction
A basic function offered by a single MOS transistor is that of an analog memory [12]. The gate voltage may be stored for many years on the gate capacitance when the gate terminal is left floating. Floating-gate MOS transistors are becoming important elements in contemporary analog VLSI signal processing. They find applications in areas such as long-term nonvolatile storage of neural network model parameters 1121-131, on-chip analog trimming [4][9] and signal conditioning for integrated sensors [Ill. In recent years, a floating-gate MOS transistor is typically fabricated in a standard or specialized doublepoly CMOS process where the floating gate is the first polysilicon layer. In industrial floating-gate systems an ultrathin layer of silicondioxide is used. Several methods have been reported for injecting charge onto, or removing charge from a floating gate. One of the best w a s presented by C. Diorio [6] using tunneling to remove charge and hot carrier injection for adding charge. The claimed resolution of more than 14 bit

using only a fewp W of power for programming is taking analog non-volatile memory another leap forward. Several other reported programming devices are using tunneling injectors in double-poly CMOS process [SI[13] and fairly high resolution and remarkably long retention time have been demonstrated. The major problem with tunneling structures is the high (> 20V) voltage required. High-voltage drivers are area-consuming and the switching of high voltages may affect the surrounding circuits severly. An alternative is short-wave UV-light (UV-C) making silicondioxide slightly conductive without any high voltages 1 1 1 . Besides the inconvenience with short-wave UVlight, optical shielding must be used and the passivation layer should not absorb the UV-light (no nitride). The challenge of making a versatile analog memorystructure in standard digital CMOS technology still remains. Double polysilicon must be avoided and high voltages reduced as much as possible. In large analog VLSI systems even low-precision analog memory structures may be attractive, particularly if they are simple and occupy a small chip area. Furthermore, analog design solutions in standard digital technologies should allow the implementation of low-cost mixedsignal VLSI systems. In this paper we discuss the implementation of a simple analog floating gate memory based on the standard Fowler-Nordheim [7] tunneling in a standard singlepolysilicon (digital) CMOS process. The basic structure is discussed first followed by a description of the on-chip memory drivers. The complete analog memory is then presented together with experimental results from test chips fabricated in a 2-micron CMOS process.

2: The Analog Memory Structure

The principle of operation is the same as reported earlier by Lazzaro et al. [8] and shown in figure 1. The

1086-1947196$5.000 1996 IEEE Proceedings of MicroNeuro '96

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Figure 1. Two capacitors are connected to the floating gate. As indicated there is one cou pling capacitor ten times the size of the tun neling capacitor. TI is a small Ptype readout transistor, T2 the tunneling structure based on a N type transistor while T 3 is a large cou pling capacitor realized with Ptype transistor with source and drain connected to the well.

floating gate of a MOS-transistor has two floating capacitors connected, one approximately ten times the size of the other. The small capacitor is used for tunneling while the large one is a bootstrap capacitor. The standard way of making floating capacitors in CMOS is done with an extra polysilicon layer. We are limited to a single polysilicon layer and are using the capacitor made up by the MOS-transistor. The smallest capacitor, C,unnel,is where the Fowler-Nordheim tunneling takes place. Both adding charge t o or removing charge from the floating gate is done through the Ctunnei. The large bootstrap capacitor, Cleve), dominates the actual potential of the floating gate. The potential on the input of Cleuel will appear on the floating gate scaled down by the total load capacitance (capacitive division). Adding charge is simply done by applying a large positive potential over the Ctunnel capacitor ('up'terminal) while keeping the 'down'-terminal of the Clcurl capacitor grounded. Removing charge is symmetric, ie. by raising the floating gate potential through the Clcurlcapacitor ('down'-terminal) while keeping the input side of Crunnel grounded.

Figure 2. The tunnelingstructure is simply a metalpoly contact with a channel under neath or a MOS transistor with a stacked con tact. Phis is an intended violation of the design rules lowering the tunnelingvoltage. In a) the silicon structure is shown where the small gateactive overlap capacitance en sures charge transport between the floating gate and the active. In b) the actual layout is show, while the symbo! used is shown is c).

2.1:

Tunneling structure

The thinnest oxide in a standard digital CMOS process is found in the gate of the MOS-transistor. Carley [4] suggested using the MOS transistor as a tunneling structure. Although the nominal tunneling voltage of the gate-active structure is 25V, the two extra corners in Carley's structure are claimed t o reduce the tunneling voltage t o 17-18V due t o field enhancement. More recent results [6] indicate no field enhancement due to corners simply because in fabrication all corners are rounded. The charge transport takes place along

the edge of the polysilicon and increasea linearly with the length of the edge. In Carley's experiments a MOS transistor with the well connected together with the source/drain active area is used. Although no experimental results were shown, Carley mentions the rather remarkable fact that the well-potential did not affect the tunneling mechanism of the MOS structure for voltages less than 20V. This observation is supporting the assumption that the field enhancement is happening along the edges. The major charge transport goes between the active and the polysilicon gate due to the source/drain - gate overlap. Virtually no charge is transported between the well and the gate. A close to perfect tunneling structure can be made as a MOS-device in the substrate. Eliminating the well makes the structure small with virtually no coupling capacitance (only the source/drain - gate overlap). In order to make our structure as small as possible with maximum edge, a 'stacked contact' was added on top of the gate. Although this 'hack' is not allowed according to the design-rules, it is known to work with a possible threshold shift during annealing of the metalcontacts. The tunneling structure is shown in figure 2 and as shown in figure 3 already at 14 - 15V significant tunneling occurs leaving good margins for the estimated breakdown voltage of 28 V between active and substrate. These results are better than expected and cannot only be explained by the increase poly-edge length. Disregarding the field-enhancement in the corners we end up with the stacked contact as a possible explanation. The threshold-shift introduced is actu-

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Figure 3. The output current as a function of the applied voltage over the tunneling struc ture. A constant programming puls of one second duration was used.
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Figure 5. The IV characteristicso f the N type LDD MOS.

Figure 4. A ratiologic style high voltage driver is realized in standard digital CMOS with a Ntype LDD MOS transistor as pull down and a lateral PNP bipolar transistor as pullup.

ally enhancing our tunneling-structure. These effects should be carefully studied, but extend the scope of this article. The capacitor is implemented by a well-poly (gate) capacitor where the well is on the driven side. A significant load capacitance is added to the driving side by the well-substrate capacitance, but the filtering effect is attractive avoiding silicon dioxide degradation.

3: The high-voltage drivers

Before we proceed t o the the analog memory circuit, we need voltage-drivers giving at least 20V output. Lazzaro et al. [8] are using both P-type and Ntype LDD (Lightly Doped Drain) MOS structures in a cross-quad arrangement. We are using a simpler struc-

ture as shown in figure 4. As suggested by Lazzaro we are using a pulldown N-type LDD MOS transistor with the heavy doped drain substituted by a lightly doped well increasing the drain resistance of the MOStransistor. A lightly doped drain-material will add a significant output-resistance t o the device, but leads t o good high-voltage properties. It is not possible t o make small LDD MOS devices since there is no selfalignment. Both theoretical studies and practical experiments confirm the high-voltage properties of this LDD MOS structure handling 60V without breaking down [6]. In a digital CMOS process no lightly doped diffusion is available within a well (the PBASE layer in MOSIS is not considered to be a standard feature). An alternative is t o apply a lateral PNP bipolar with the well as base and two active areas as collector and emitter. Although this structure has a low gain (2 - 4) and a significant base-current, we achieve a resistive pullupelement by applying a suitable base-voltage. Measured characteristics of the N-type LDD MOS are shown in figure 5 while the PNP bipolar characteristics are shown in figure 6. Although the lateral bipolar is working properly the power consumption is higher than desired through a fairly high base-current. Other structures using well-resistors might be considered. In figure 7 the output of the high-voltage buffer is measured as a function of the 5V input pulse. As expected the switching characteristics are not excellent (7b and 7c), but in this context a sloppy flank is desirable avoiding overshoot and silicondioxide 'wear-out'.

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12

14

16

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Figure 8. The complete analog memory struc ture consist of two highvoltage drivers con and the Cleve[.The read nected to the Ctunnel out transistor is a Ptype MOS device with a currentmirror amplifying the current with a factor of 100.

Figure 6. The I V characteristics of the lateral bipolar.

4: The complete analog memory

As shown in figure 8 the analog memory circuit contains two high-voltage drivers connected t o the Ctunne[ and the Cleve,capacitors. The stored analog value may be read by a MOS-transistor (floating-gate). In order to avoid tunneling in the readout transistor, both the source and the drain potentials must be higher than the substrate voltage ( G n d ) . A well transistor with source connected to V d d is adequate and the stored voltage may be read out as a current sink. A typical working voltage on the floating gate is approximately one diode-offset (% 0.7V) below V d d . In order to shift the drain-potential of the readout transistor, an extra bias-transistor is inserted between readout transistor and the diode-load in the current-mirror. This biastransistor is also used as a current-limiter when the stored analog value is close to Gnd. The output of the circuit is a current amplified with an amplification factor of 100 through the current-mirror. The programming is 'inverted-digital' with V d d to both the 'tune-up' and the 'tune-down' knobs as the initial state. Applying Gnd to the 'tune-up' input adds charge to the floating gate while applying Gnd to the 'tune-down' input removes charge from the floating gate. By adding a simple switch to the diode in the current-mirror (see figure 8)' the readout current my be 'latched' or stored while the floating gate is programmed. In this way the output-current is always valid (although sampled). In figure 9 both tuning-up and tuning-down of the

Figure 7. In a) the measured highvoltage out put is shown as afunction of a 5V input pulse. In b) and c) the rising and falling edges of the highvoltage pulse are shown.

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5: Conclusions
A simple analog floating gate memory is shown t o work in standard digital CMOS. A novel layout utilizing the thin gate-oxide between the sourcejdrain diffusion and the polysilicon gate proves a usable tunneling structure. High-voltage drivers are designed with a LDD MOS pulldown and a lateral PNP bipolar. The new structure should find useful applications in modern analog and mixed-signal VLSI systems. Future work should improve the high-voltage drivers and investigate further the fundamental physical mechanisms involved in the novel tunneling structure presented.

6: Acknowledgements
Figure 9. Since the intended application is small currents, programming of the analog memory is shown for subthreshold currents. One second programming pulses are ap plied to the knobs. The measurements are scaled down by the amplification factor in the currentmirror showing a close to exponential dependence over six orders of magnitude
Chris Diorio at California Institute of Technology has contributed with valuable corrections and Professor Carver Mead at CalTech pointed out the problem of the leaky metal-contacts and threshold shifting. We would like t o thank the research council of Norway and the Office of International Affairs (OIA) at The Ohio State University for supporting this work. Also thanks to A. Motamed for his help in preparing the final version of the paper.

analog memory are shown. With a n estimated potential of 4 . 3 V on the floating gate tuning up the gate 17.5V while tuning down only required required E 14.5V. At the moment this asymmetry is not fully understood. For each applied pulse, the current was measured showing a close to exponential increase in current as a function of the number of pulses applied. The aimed application was subthreshold circuits and as expected we achieved a measured dynamic range of more than six orders in current. The circuit should work properly above threshold as well. Although we have not done any experiments on charge retention of the floating gate, the thicker gateoxide compared t o the ultrathin oxide used in EEPROMs should give a charge loss of less than 0.1% in ten years [4]. The stacked contact may reduce the retention time, but this is not known at the moment of writing. Even with a reduced retention time the memory structure is usable in neural network configurations where 'forgetting-dynamics' is required. Another disadvantage of this simple memory structure might be the low programming speed. Faster programming could be achieved with a higher programming voltage since the tunneling current will increase exponentially with the applied voltage.

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