An Improved Low-Power Low-Noise Dual-Chopper Amplifier

for Capacitive CMOS-MEMS Accelerometers

Hongzhi Sun, Fares Maarouf, Deyou Fang, Kemiao Jia, and Huikai Xie
Department of Electrical & Computer Engineering, University of Florida, Gainesville, FL 32611, USA

Abstract
This paper reports an improved low-power low-noise dual-
chopper amplifier (DCA) for capacitive CMOS-MEMS
accelerometers. The new DCA employs an on-chip band-gap
voltage reference to reduce the number of bonding pads and the
complexity of the external circuits. The temperature drifting of
the first-stage gain is reduced by using PMOS instead of NMOS
as an active load. A prototype DCA with a three-axis
accelerometer has been fabricated using the TSMC 0.35 m
technology. The number of required bonding pads is reduced
from 21 to 14, and the temperature sensitivity is reduced from
1.210
-3
/ to 5.410
-4

Key Words: CMOS-MEMS Accelerometer, Three-Axis

Accelerometer, Dual-Chopper Amplifier, Low Power, Low
Noise
I. Introduction
Micromachined accelerometers have broad applications in
automotive, biomedical, space, and military industry due to
their small size and low cost [1]. Recently three-axis
accelerometers have drawn great attention since they have much
smaller package sizes than those assembled by multiple single-
axis accelerometers [2-5]. Although there are many different
acceleration sensing mechanisms, capacitive sensing is always
preferred because of its advantages of low power, high
sensitivity, good temperature stability, and good CMOS
compatibility [6-7]. However, micromachined capacitive
accelerometers often have very small sensing capacitance and
thus are prone to electronic noises. Therefore designing low-
noise interface circuits is very crucial to achieve high
resolutions [8, 9]. Many circuit architectures have been
proposed for MEMS capacitive accelerometers, such as
switched capacitors (SC) [9, 10], continuous-time current
sensing (CTC) [11], and continuous-time voltage sensing (CTV)
[12, 13]. CTV sensing is believed to have the best noise
performance [8].
For portable devices, low power consumption is critical. A
dual-chopper amplifier (DCA) has been proposed to achieve
low power and low noise at the same time by applying a two-
stage amplifier architecture based on CTV sensing with chopper
stabilization [14]. The DCA architecture will be discussed in
Section II. Although low power and low noise were achieved in
[14], the circuit had large temperature variations. It also needed
a large number of bonding pads, occupying too much CMOS
chip area.
This paper presents an improved low-power, low-noise
DCA for CMOS-MEMS accelerometers. There are two major
improvements. First, a band-gap voltage reference is
implemented on chip to provide temperature-insensitive
modulation signals. The other major change is to replace the
NMOS with PMOS as the active load in the first stage of the
DCA, resulting in significantly reduced temperature drifting of
the overall gain. Section III gives the circuit design and analysis
of the band-gap reference and first stage of the DCA.
Experimental results are given in section IV.
II. Principle of the DCA
The architecture of the DCA [14] is shown in Fig. 1, which
employs two fundamental chopping clocks
H
and
L
. A
nested-chopper amplifier reported in [15] used a similar
architecture to reduce offset. The frequencies of the clock
signals are chosen such that f
B
<<f
L
<<f
H
, where f
B,
is the
bandwidth of the accelerometer, ranging from 1 kHz to 10 kHz.
The modulation signal is generated by an exclusive OR
operation of
H
and
L
, and the amplitude of the modulation
signal is controlled by two reference dc levels. The DCA
consists of two amplification stages. The first stage A
1
is an
open-loop, high-bandwidth amplifier. The gain of this stage is
designed to be small so that the high modulation frequency can
be used to minimize the 1/f noise and at the same time low
power and good linearity can be obtained. The input capacitance
of A
1
is optimized to maximize the signal-to-noise ratio. The
output signal of A
1
is filtered by an active low-pass filter before
the second stage A
2
. A
2
is a low-bandwidth amplifier with a
capacitive feedback configuration, yielding a moderate gain and
good linearity with low power consumption. The signal is
finally buffered and low-pass filtered by external circuits.
The input-referred noise of DCA can be as low as
16nV/ Hz at 20 Hz with power dissipation of only 1mW, and
the measured noise floor is 50g/ Hz down to 5Hz [14].
1075 978-1-4244-1908-1/08/$25.00 2008 IEEE.
Proceedings of the 3rd IEEE Int. Conf. on
Nano/Micro Engineered and Molecular Systems
January 6-9, 2008, Sanya, China

Figure 1 (a) Architecture of the dual-chopper amplifier; (b)
Schematic of A
1
; and (c) Schematic of A
2
.
III. Analysis and Circuits Design
(a)
3.1 Improvement on first stage of DCA
The first improvement is made on the first stage of the
DCA which is an amplifier with a small gain. The schematic of
the previous design is shown in Fig. 1(b), where two diode-
connected NMOS transistors (M5 and M6) work as the active
loads. The gain of this stage can be derived as following:
C I I g g r g A
m m out m
= = = =
5 1 5 5 1 1 5 1 5 1 1
/ 2 / 2 / | | (1)
where g
m1
and g
m5
are the transconductance of M
1
and M
5
,
respectively, is the carrier mobility, =C
ox
W/L and C is a
constant related with the ratios of the transistor sizes and static
currents. Since the mobility of electrons and holes have
different dependences on temperature, the factor
5 1
/
in
Eq. (1) varies with temperature [16], which causes the
temperature drifting of the signal gain of A
1
.
(b)
(c)
The temperature dependence of the gain of A
1
can be
reduced effectively by replacing NMOS with PMOS as the
active loads. Thus both M1 (M2) and M5 (M6) are NMOS, so
the temperature dependences of the carrier mobility of M1 (M2)
and M5 (M6) cancel each other, and make the gain of A
1

temperature-independent. Fig. 2 shows the simulation result of
the temperature dependence of the gain of A
1
with the improved
design compared to the previous design, where the temperature
sensitivity is reduced from 1.110
-3
/C down to 2.810
-4
/C,
which is a significant improvement.
Temperature (C)
L
i
n
e
a
r

G
a
i
n


Figure 2 Simulation results of the temperature dependence of
the gain of A
1
.
1076
3.2 Band-gap Voltage Reference
The capacitive sensing accelerometer integrated with the
interface circuits is based on a capacitive divider, in which a
rotor finger is placed in between two stator fingers, as shown in
Fig. 3. The rotor finger is attached on the proof mass and it
moves when an external acceleration is applied. The paired
comb finger configuration can form a fully-differential
capacitive bridge. The parasitic capacitance due to interconnect
and input capacitance of interface circuits should be taken into
account, which is labeled C
P
in Fig. 3.

Figure 3 Principle of capacitive acceleration sensing.

From Fig. 3, the sensing voltage V

sense
can be expressed as
the following equation:
m
p
p
p
m
p
sense
V
x
x
C C
C
x
x
C C
C
V
C
x x
x C
x x
x C
x x
x C
x x
x C
V
2
0 0
0
0
0
0
0 0
0
0 0
0
0 0
0
0 0
) (
2
1
2
2
A
+

A
+
=
+
A +

A
A +

A
=
, (2)
where C
0
and x
0
are the capacitance and comb-finger gap at zero
acceleration, respectively, V
m
is the modulation signal, and x is
the acceleration-induced displacement of the rotor fingers. Since
the displacement is typically very small, the higher-order term
can be neglected. Therefore, Eq. (2) can be simplified as
m
p
sense
V
x
x
C C
C
V
0 0
0
2
2 A
+
=
, (3)
or
m
p
sense out
AV
x
x
C C
C
V A V
0 0
0
2
2 A
+
= =
, (4)
where A (= A
1
A
2
) is the total gain of the DCA. The sensing
signal is linearly proportional to the amplitude of the
modulation signal. So in order to achieve good temperature
performance, both V
m
and A must be insensitive to temperature
change. Since the modulation signal is obtained by chopping
two reference dc voltages, as shown in Fig. 1(a), it is important
to make the voltage references stable to temperature variations.
A band-gap voltage reference that is temperature-insensitive is
implemented on chip, whose schematic is shown in Fig. 3.

Figure 4 Schematic of Band-Gap Voltage Reference

Here exist the following equations:

2
1 0
1 Q
be
beQ beQ
Q
I
R
V
R
V V
I =
A
=

=
(5)
be beQ Q beQ ref
V K V KRI V V A + = + =
2 2 2
(6)
0
1
1
0
ln
SQ
SQ
Q
Q
b
be
I
I
I
I
q
T k
V = A
(7)
where V
beQ0
, V
beQ1
and V
beQ2
are the base-emitter voltages of
bipolar transistors Q
0
, Q
1
and Q
2
, respectively, R and KR are
the load resistors with K a constant that determines the
temperature compensation, I
Q1
and I
Q2
are the static currents
flowing through M
1
and M
2
, respectively, k
b
is the Boltzmanns
constant, and T is the absolute temperature. Note that V
beQ2
has
a negative temperature coefficient (around -2mv/C) and V
be
is
proportional to absolute temperature (PTAT). According to
Eq. (2), if a proper value of K is chosen, the temperature
variations of V
beQ2
and V
be
will cancel each other, so V
ref
can be
made independent of temperature to the first order. In this
design, K is chosen to be approximately 6.
The comparison of the overall gain between this design
and the previous design is shown in Fig. 5. When chopping at
x x
x C
A
0
0 0
x x
x C
A +
0
0 0
x x
x C
A
0
0 0
x x
x C
A +
0
0 0
rotor
stator
stator
1077
the double frequencies of 1 MHz and 20 kHz, the overall dc
gain of the DCA was around 45 dB for both designs, but the
temperature sensitivity of the improved design is reduced to
6.910
-4
/C in the range of 20-100, compared to 1.210
-3
/C
for the previous design.

Figure 5 Simulated temperature sensitivity of the overall gain.
IV. Experimental Results
A monolithic three-axis CMOS-MEMS accelerometer with
the improved interface circuits has been fabricated in a TSMC
0.35m 4-metal 2-poly technology followed by a post-CMOS
micromachining process [5]. A microscopic photo of a released
die is shown in Fig. 6, where the die size is 3mm by 3mm. One
lateral dual-axis accelerometer and one z-axis accelerometer are
integrated on the same chip.

Figure 6 Die micrograph of the chip.
The output circuit was
m

The temperature dependence of the overall gain is measured

Figure 8 Measured temperature dependence of the overall gain.
of the band-gap voltage reference
easured in the temperature range of 20-100C. The
measurement result is shown in Fig. 7. The reference voltage
only changes 18 mV or 1.5% over the 80C temperature span,
corresponding to a temperature sensitivity of 2.110
-4
V/C.

Temperature (C)
O
v
e
r
a
l
l

L
i
n
e
a
r

G
a
i
n

O
u
t
p
u
t

v
o
l
t
a
g
e

(
V
)


Figure 7 Voltage output of the band-gap voltage reference
Temperature (C)
circuit.

in the range of 20-100C, and the results are shown in Fig. 8. It
can be observed that the gain is increased from 134.2 to 142.1,
as the temperature changes from 20C to 100C, corresponding
to a temperature sensitivity of 7.410
-4
/C. This result is close
to that from the simulation in Section III.
O
v
e
r
a
l
l

L
i
n
e
a
r

G
a
i
n

Temperature (C)
1078
The accelerometer was tested on a LDS V-408 shaker with
a PCB Piezotronics 356A16 reference accelerometer. For a
200 Hz 0.4 g acceleration generated by the shaker, the response
waveform and spectrum of the x-axis output of the x-y
accelerometer on the chip are shown in Fig. 9 and Fig. 10,
respectively. The accelerometer with the improved DCA design
achieves the sensitivity of 230 mV/g and a noise floor of
100 g/Hz.
0.4-g 200-Hz acceleration excitation.

gure 10 Output spectrum of the MEMS accelerometer with a

0.4-g 200-Hz acceleration excitation with 0.4-g 200 Hz.
When operated at 3.3V, the circuit for each axis drew a
current of 350 A, corresponding to a power consumption of
1.2 mW.
V. Conclusions
An on-chip band-gap voltage reference has been implemented
and the first stage of the DCA has been modified to reduce its
temperature sensitivity and external circuit complexity. A
single-chip three-axis accelerometer with the improved DCA
design has been fabricated and characterized. The testing results
show that the new design has reduced the temperature
sensitivity by a factor of 5. The pads necessary for the function
has been reduced by 1/3 (from 21 to 14).
Acknowledgement
U
Research Foundation.
Yazdi, F. achined
Inertial Sens f the IEEE, 86 (8),
[5] H. Qu, D. Fang, and H. Xie, Single-Crystal Silicon
Based S Integrated
Accelerom the Third IEEE
d, Digitally Force-Balanced
Accelerometer with
Circuitry, Pro lid State Sensor and
[7]
Survey. Weinheim, Germany: Wiley,
[8] A Low-Noise
Low-Offset Capacitive Sensing Amplifier for a 50-
g/Hz Monolithic CMOS MEMS Accelerometer,

Figure 9 Output waveforms of the MEMS and reference
accelerometers with a
Fi
This project was partially supported by the NASA/UCF-
F Space Research Initiative and the University of Florida

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