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Semiconductor Assembly Process

Wafer Backgrind
Wafer Backgrind is the process of grinding the backside of the wafer to the correct wafer thickness prior to assembly. It is also referred to as 'wafer thinning.' Wafer backgrinding has not always been necessary, but the drive to make packages thinner and thinner has made it indispensable. Most package types in the semiconductor industry today would require a wafer thickness ranging from 8 mils to 20 mils. Wafers normally undergo a cleaning and surface lamination process prior to the actual backgrinding process. Surface lamination involves the application of a protective tape over the surface of the wafer to protect it from mechanical damage and contamination during backgrinding. The surface-laminated wafers are then loaded into cassettes that will go into the cassette holder of the backgrinding machine. The machine picks up the wafer from its backside (untaped side) with a robotic arm, which positions the wafer for backgrinding. The backgrinding process is automatically accomplished by a grinding wheel, following a precise set of parameters to ensure proper backgrinding. To remove debris from the wafer while backgrinding, the wafer is usually washed continuously with D/I water while undergoing backgrinding. Once the wafer has been background, the wafer is returned to the cassette, and the cycle is repeated for the next wafer. Parameters set for backgrinding include spindle speed, spindle coolant water temperature and flow rate, D/I water temperature, initial and final wafer thickness, and feed speeds.

Common Wafer Backgrind-related Failure Mechanisms:


Die Cracking/Chipping - occurrence of fracture or chip-out anywhere in the die. Common Causes in the context of Backgrind: incorrect backgrind parameters resulting in excessive stresses on the wafer Die Scratching - inducement of any mechanical damage on the die, as when an operator scratches a die with tweezers due to mishandling. Common Causes: insufficient operator training, disorderly workplace, use of improper tools Die Metallization Smearing - depression or deformation of any metal line on the die surface. Common Causes: foreign materials on the backgrind tape, wafer mishandling Die Corrosion - corrosion of the metallic parts of the die as a result of prolonged exposure to water during backgrinding

Die Preparation
Die preparation is the process by which the wafer is singulated into individual dice in preparation for assembly. Die preparation consists of two major steps, namely, wafer mounting and wafer saw. Wafer mounting is the process of providing support to the wafer to facilitate the processing of the wafer from Wafer Saw through Die Attach. During wafer mounting, the wafer and a wafer frame are simultaneously attached on a wafer ordicing tape. The wafer frame may be made of plastic or metal, but it should be resistant to warping, bending, corrosion, and heat. The dicing tape (also referred to as a wafer film) is just a PVC sheet with synthetic adhesive on one side to hold both the wafer frame and the wafer. Typically measuring 3 mils thick, it should be flexible yet tough and strong, and with low impurity levels as well. Using a special wafer mounting machine, wafer mounting consists of the following steps: 1) frame loading; 2) wafer loading; 3) application of tape to the wafer and wafer frame; 4) cutting of the excess tape; and 5) unloading of the mounted wafer.

Fig. 1. Photos of wafers mounted on wafer frames

Fig. 2. Wafer films for mounting wafers on wafer frames

During wafer mounting, the following concerns must be prevented: wafer cracking or breakage, bubble trapping on the adhesive side of the tape, scratches on the active side of the wafer, and non-uniform tape tension which can result in tape wrinkles. Wafer saw follows wafer mounting and is the step that actually cuts the wafer into individual dice for assembly in IC packages. The wafer saw process consists of the following steps: 1) the frame-mounted wafer is automatically aligned into position for cutting; 2) the wafer is then cut thru its thickness according to the programmed die dimensions using a resin-bonded diamond wheel (see Fig. 3) rotating at a very high rpm; and 3) the wafer goes through a cleaning process using high pressure DI water sprayed on the rotating workpiece and then dried by air-blowing.

Fig. 3. Photos of Wafer Saw Blades

Kerf width is defined as the average width of the cutline plus the error attributed to microchipping. The singulated dice may be left attached to the wafer tape for pick-and-place during die attach or may be individually kept in waffle packs for future assembly. Important parameters for consideration during wafer saw include the following: cut mode (direction and manner of cutting), feed speed (speed at which the wafer is being introduced to the blade), spindle rev (speed of revolution of the cutting wheel), blade height, and cutting water flow. Important

parameters for the washing step include the following: wash time, wash rpm, DI water pressure, dry time, dry rpm, and temperature and air flow rate.

Common Die Preparation-related Failure Mechanisms:


Die Lifting - detachment of the die from the die pad or cavity. Wafer backside contamination during die preparation may inhibit good adhesion between the die backside and the die attach material. Other Common Causes of Die Lifting:contamination on the die pad or cavity, excessive die attach voids, incomplete die attach coverage, inadequate die attach curing Die Cracking - occurrence of fracture anywhere in the die. Incorrect wafer saw and washing parameters can result in microcracks in the wafers, which can propagate into larger die cracks during later stages of the assembly process.Other Common Causes of Die Cracking: excessive die attach voids, die overhang or insufficient die attach coverage, excessive die ejection force on the wafer tape Die Scratching - inducement of any mechanical damage on the die, as when an operator scratches a die with tweezers due to mishandling. Die scratches can also result from mishandling of wafers during the die preparation process. Other Common Causes of Die Scratching: insufficient operator training, disorderly workplace, use of improper tools Die Metallization Smearing - depression or deformation of any metal line on the die surface. Common Causes: dirty or worn-out die attach pick-and-place tool, wafer mishandling Die Corrosion - corrosion of the metallization and other components of the die. Common Causes: corrosive contaminants on the wafer tape or rinsing water Die Contamination - contamination of the die surface with silicon dust or foreign material that may be attached either by electrostatic, mechanical, or chemical means. Common Causes: contaminated rinsing water; static charge

Die Attach Process


Die Attach (also known as Die Mount or Die Bond) is the process of attaching the silicon chip to the die pad or die cavity of the support structure (e.g., the leadframe) of the semiconductor package. There are two common die attach processes, i.e., adhesive die attach and eutectic die attach. Both of these processes use special die attach equipment and die attach tools to mount the die. Adhesive Die Attach Adhesive die attach uses adhesives such as polyimide, epoxy and silver-filled glass as die attach material to mount the die on the die pad or cavity. The adhesive is first dispensed in controlled amounts on the die pad or cavity. The die for mounting is then ejected from the wafer by one or more ejector needles.

Fig. 1. Two examples of die attach machines

While being ejected, a pick-and-place tool commonly known as a 'collet' then retrieves the die from the wafer tape and positions it on the adhesive. All of the above steps are done by special die attach equipment or 'die bonders' (see Fig. 1). The mass of epoxy climbing the edges of the die is known as the die attach fillet. Excessive die attach fillet may lead to die attach contamination of the die surface. Too little of it may lead to die lifting or die cracking. Another critical aspect of adhesive die attach is the ejection of the die from the wafer tape during the pick-and-place system's retrieval operation. The use of inappropriate or worn-out ejector needle and improper ejection parameter settings can cause die backside tool marks or microcracks that can eventually lead to die cracking.

Fig. 2. Photo showing the D/A adhesive as the grainy material between the die and the die pad

See also: Die Attach Failures Eutectic Die Attach Eutectic die attach, which is commonly employed in hermetic packages, uses a eutectic alloy to attach the die to the cavity. A eutectic alloy is an alloy with the lowest melting point possible for the metals combined in the alloy. The Au-Si eutectic alloy is the most commonly used die attach alloy in semiconductor packaging. A gold preform is placed on top of the cavity while the package is being heated. When the die is mounted over this gold preform, Si from the die backside diffuses into the gold preform, forming Au-Si alloy. As more Si diffuses into the gold preform, the Si-to-Au ratio of the alloy increases, until such time that the eutectic ratio is achieved. The Au-Si eutectic alloy has 2.85% of Si and melts at about 363 degrees C. Thus, the die attach temperature must be reasonably higher than this temperature to achieve the eutectic melting point. At this point, the alloy melts, attaching the die to the cavity. To optimize the die attachment, the operator 'scrubs' the die into the eutectic alloy for even distribution of the die attach alloy. Eventually the diffusion of silicon atoms into the gold preform exceeds the eutectic

limit, and the die attach alloy begins to solidify once again. The package is then allowed to cool down to completely solidify the eutectic alloy and complete the die attach process. Aside from the Au-Si alloy, semiconductor assembly may employ other metal alloys for eutectic die attach. Table 1 lists some of the other alloys used in eutectic die attach preforms. Table 1. Compositions and Melting Points of some Eutectic Die Attach Preforms
Composition 80% Au, 20% Sn 92.5% Pb, 2.5% Ag, 5% In 97.5% Pb, 1.5% Ag, 1% Sn 95% Pb, 5% Sn 88% Au, 12% Ge 98% Au, 2% Si 100% Au Temperature (deg C) Liquidus 280 300 309 314 356 800 1063 Solidus 280 309 310 356 370 1063

Effects of Die Attach Voids Regardless of die attach process, the presence of voids in the die attach material affects the quality and reliability of the device itself. Large die attach voids result in low shear strength and low thermal/electrical conductivity, and produce largedie stresses that may lead to die cracking. Small voids provide sufficient shear strength and electrical/thermal conductivity, while 'cushioning' large dice from stresses. Total absence of voids may mean high strength, but it may also induce large dice to crack. The strength of die attachment is measured using the die shear test.

Figure 3. X-ray photo of large epoxy die attach voids; Au-Si eutectic voids are more visible during x-ray inspection because of the higher density of Au-Si

Common Die Attach-related Failure Mechanisms:


Die Lifting - detachment of the die from the die pad or cavity. Common Causes: contamination on the die pad or cavity, die backside contamination, excessive die attach voids, incomplete die attach coverage, inadequate die attach curing Die Cracking - occurrence of fracture anywhere in the die. Common Causes in the context of Die Attach: excessive die attach voids, die overhang or insufficient die attach coverage, insufficient bond line thickness, excessive die ejection force on the wafer tape, absence of die attach voids Adhesive Shorting - electrical shorting between exposed metal lines, bond pads, bonds, or wires as a result of adhesive accidentally dripping on the surface of the die (sometimes called 'epoxy on die'). Common Causes: incorrect die attach material viscosity, incorrect adhesive dispensation

Bond Lifting - lifting of the first or second bond from the die or leadfinger, respectively. From the die attach process point of view, this is often due to resin bleeding of the die attach material into the bond pads or leadfingers, inhibiting good intermetallic formation. See also Wirebonding. Die Scratching - inducement of any mechanical damage on the die, as when an operator scratches a die with tweezers due to mishandling. Common Causes: insufficient operator training, worn-out or contaminated pick-and-place tool, disorderly workplace, use of improper tools Die Metallization Smearing - depression or deformation of any metal line on the die surface. Common Causes: dirty or worn-out die attach pick-and-place tool, wafer mishandling

Die Shear Testing - Mil-Std-883 Method 2019


Die Shear Testing is the process of determining the strength of adhesion of a semiconductor die to the package's die attach substrate (such as the die pad of a lead frame or the cavity of a hermetic package), by subjecting the die to a stress that's parallel to the plane of die attach substrate, resulting in a shearing stress between: 1) the die-die attach material interface; and 2) the die attach material-substrate interface. The general purpose of die shear testing is to assess the over-all quality of the die attach process, including the integrity of the materials and the capabilities of the processes used in mounting the die (and other elements, if any) to the package substrate. Mil-Std-883 Method 2019 is the most widely-used industry standard for performing this test. A typical die shear tester consists of: 1) a mechanism that applies the correct load to the die with an accuracy of +/- 5% of full scale or 50 g, whichever tolerance is greater; 2) a die contact tool which makes the actual contact with the full length of the die edge to apply the force uniformly from one end of the edge to the other; 3) provisions to ensure that the die contact tool is perpendicular to the die attach plane; 4) provisions to ensure that the fixture holding the die may be rotated with respect to the contact tool so that the die edge and contact tool may always be aligned in parallel to each other; and 5) a binocular microscope (10X min magnification) and lighting system to facilitate the observation of the die and contact tool while the test is being performed. The force applied to the die during die shear testing must be sufficient to shear the die from its mounting or twice the lower specification limit for the die shear strength, whichever occurs first. The direction of the applied force must be perpendicular to the die edge and parallel to the die attach or substrate plane. After the initial contact has been made and the application of force starts, the relative position of the tool must not change vertically, i.e., it must be prevented from contacting either the die attach material or the substrate. Failures from die shear testing include: 1) failure to meet the specified die shear strength requirements; 2) a separation that occurs at less than 1.25X the minimum die shear strength and evidence of less than 50% adhesion of the die attach material; and 3) a separation that occurs at less than 2X the minimum die shear strength and evidence of less than 10% adhesion of the die attach material. The mode of separation must also be classified into and recorded as any of the following: 1) shearing of the die itself with silicon remaining; 2) separation of the die from the die attach material; and 3) separation of both the die and die attach material from the package substrate. The die shear strength requirements are plotted in Figure 2019.4 of Mil-Std-883 Method 2019.

Wirebonding Process
Wirebonding , or wire bonding, is the process of providing electrical connection between the silicon chip and the external leads of the semiconductor device using very fine bonding wires. The wire used in wirebonding is usually made either of gold (Au) or aluminum (Al), although Cu wirebonding is starting to gain a foothold in the semiconductor manufacturing industry. There are two common wirebonding processes: Au ball bonding and Al wedge bonding. During gold ball wire bonding, a gold ball is first formed by melting the end of the wire (which is held by a bonding tool known as a capillar y) through electronic flame-off (EFO). This free-air ball (Fig. 1a) has a diameter ranging from 1.5 to 2.5 times the wire diameter. Free air ball size consistency, controlled by the EFO and the tail length, is critical in good bonding. For a discussion on how the melting of the wire affects grain size distribution and wire strength, see: Grain Size Distribution in Gold Ball Bonds. The free-air ball is then brought into contact with the bond pad. Adequate amounts of pressure, heat, and ultrasonic forces are then applied to the ball for a specific amount of time, forming the initial metallurgical weld between the ball and the bond pad as well as deforming the ball bond itself into its final shape (Fig. 2).

Fig 1a. Photo of a free-air ball prior to ball bond formation

Fig 1b. Wire loop formed to connect the die to the lead finger

The wire is then run to the corresponding finger of the leadframe, forming a gradual arc or "loop" (Fig. 1b) between the bond pad and the leadfinger. Pressure and ultrasonic forces are applied to the wire to form the second bond (known as awedge bond, stitch bond, or fishtail bond and shown in Fig. 3), this time with the leadfinger. The wirebonding machine orwirebonder (see Fig. 5) breaks the wire in preparation for the next wirebonding cycle by clamping the wire and raising the capillary. During aluminum wedge wire bonding, a clamped aluminum wire is brought in contact with the aluminum bond pad.Ultrasonic energy is then applied to the wire for a specific duration while being held down by a specific amount of force, forming the first wedge bond (Fig. 4) between the wire and the bond pad. The wire is then run to the corresponding lead finger, against which it is again pressed. The second bond is again formed by applying ultrasonic energy to the wire. The wire is then broken off by clamping and movement of the wire. Because it is non-directional, gold ball bonding is much faster than aluminum wedge bonding, which is why it is extensively used in plastic packaging. Unfortunately, gold ball bonding on Al bond pads can not be used in hermetic packages, primarily because the high sealing temperatures (400-450 deg C) used for these packages tremendously accelerate the formation of Au-Al intermetallics that can lead to early life failures. Gold ball bonding on gold bond pads, however, may be employed in hermetic packages. Unlike Al-Al ultrasonic wedge bonding, Au-Al thermosonic ball bonding requires heat to facilitate the bonding process. The Al bond pad is harder than the Au ball bond, making good bonding between them through purely ultrasonic means impossible without causing wire, bond pad, or silicon substrate damage. The application of thermal energy to the Al bond pads 'softens' them, promoting the inter-diffusion of Au and Al atoms that ultimately form the Au-Al bond. Heat application also improves bonding by removing organic contaminants on the bond pad surface.

Fig 2. Photo of a gold ball bond (1st bond) on the bond pad

Fig 3. Photo of a gold wedge/stitch bond (2nd bond) on the leadfinger

Fig 4. Photo of an aluminum wedge bond (first bond) on the bond pad

Common Wirebonding-related Failure Mechanisms:


Ball Bond Lifting - detachment of the ball bond from the silicon chip; also refers to non-sticking of the ball bond to the bond pad. Common Causes: contamination on the bond pad, incorrect wirebond parameter settings, instability of the die during bonding, bond pad corrosion, excessive bond pad probing, Kirkendall voiding, intermetallic spiking due to the Devaney mechanism, excessive thermal stress resulting in excessive intermetallic formation, bond pad metallization/barrier metallization lifting, cratering. Wedge Bond Lifting - detachment of the wedge bond from the silicon chip, bonding post, or leadfinger; non-sticking of the wedge bond to the bond pad, post, or leadfinger. Common Causes: contamination on the bond pad or leadfinger, incorrect parameter settings, instability of the die or leadframe during bonding, bond pad or leadfinger corrosion, excessive bond pad probing See separate article on wedge lifting. Ball Bond Neck Break - breakage of the wire at the neck of the Au ball bond. Common Causes: incorrect wirebond parameter settings, incorrect wire looping, die-to-package delamination, excessive wiresweeping during mold, excessive die overcoat, 'bamboo' grain structure due to excessive thermal treatment Wedge Bond Heel Break - breakage of the wire at the heel of the Al wedge bond. Common Causes: incorrect wirebond parameter settings, incorrect wire looping, leadfinger-to-package delamination, excessive wiresweeping during mold Midspan Wire Break - breakage along the span of the wire. Common Causes: wire nicks or damage, wire corrosion, tight wire looping, excessive wiresweeping, electrical overstress Bond-to-Metal Shorting - electrical shorting between the bond and a metal line on the die. Common Causes: incorrect wirebond parameter settings, incorrect bond placement, insufficient bond pad-to-metal distance Bond-to-Bond Shorting - electrical shorting between two bonds. Common Causes: incorrect wirebond parameter settings, incorrect bond placement, insufficient bond pad-to-bond pad distance Wire-to-Wire Shorting - electrical shorting between two wires. Common Causes: incorrect wire looping, excessive wiresweeping, insufficient wire-to-wire distance Cratering - silicon damage under the bond pad, the worst of which is when a chunk of silicon is completely detached from the active circuit. Common Causes: incorrect wirebond parameter settings, excessive bond pad probing

Common Causes of Wire Bonding Failures


Wire bond failures comprise a major concern of any semiconductor manufacturing company. Common causes of wire bond failures include the following: 1) Voiding in the Bonds Atomic interdiffusion between different metals is a natural phenomenon in a wirebond metallurgical system. If left unchecked, however, this can lead to voids in the bond that can result in significant degradation of the bond's mechanical strength and electrical conductivity. Voiding is generally caused by unequal diffusivities exhibited by the different metals used in the wire bond, a phenomenon known as 'Kirkendall Effect.' In gold ball bonding, for example, the rates of diffusion of gold atoms from the gold ball into the aluminum bond pad and the aluminum atoms from the bond pad into the gold ball bond are unequal. Voiding failures from such interdiffusion process can be accelerated by long exposure to high temperatures and the presence of contaminants. Halogen contaminants can also cause voiding failures. For instance, aluminum bromide formed from free bromine can volatilize, creating voids within the bonds. 2) Presence of Contaminants The presence of halogen contaminants on the bond pads can cause the bond pads to corrode in the presence of moisture. Corrosion per se is a major cause of bond failure as the bond and wire are eaten away. The formation of corrosion byproducts are harmful too, especially if already present at the time of bonding, since these can impede the sticking of the bonds onto the bond pads. The presence of other types of contaminants on the bond pad such as unetched glass or silicon dust also impede proper bond formation between the wire and the bond pad. Contaminants on the lead fingers where second bonds are formed likewise cause weak bonds, or even non-sticking. Such contaminants include residual plating bath components as well as metallic impurities. Organic contaminants in raw leadframes are a common issue too. 3) Looping Problems Correct wire looping is important during wirebonding. Lack of adequate wire looping can result in excessive stresses at the bond neck or heel, which can lead to neck and heel breaks when the device is subjected to thermo-mechanical stresses. Excessive wire looping, on the other hand, can result in sagging wires and wire sweeping, both of which can cause wire shorting. Voiding is generally caused by unequal diffusivities exhibited by the different metals used in the wire bond, a phenomenon known as 'Kirkendall Effect.'. In gold ball bonding, for example, the rates of diffusion of gold atoms from the gold ball into the aluminum bond pad and the aluminum atoms from the bond pad into the gold ball bond are unequal. Voiding failures from such interdiffusion process can be accelerated by long exposure to high temperatures and the presence of contaminants. 4) Bond Placement/Geometry Problems The bond must be placed well within the bond pad. A bond that is partially positioned outside the open window of the bond pad can result in weak bonding or, worse, shorting with an active metal or another bond. Inferior bond geometry as characterized by under- or over-sized bonds and/or incorrect aspect ratio can also lead to weak bonds. 5) Bonding Site/Substrate Issues

Aside from surface contamination, there are other wire bonding site or substrate problems that can lead to bonding failures. Common bonding site/substrate issues include: 1) excessive probe digging on bond pads; 2) lifting of the bond pad metal; 3) voids in the silver plating of the lead fingers; 4) silicon nodules on the bond pad; and 5) silicon damage beneath the bond pad which can lead to cratering (cratering, by the way, is generally attributed to fractures caused by overbonding). 6) Equipment-related Problems Equipment-related issues that can cause wirebond failures include: 1) incorrect parameter settings; 2) incorrect equipment set-up; 3) calibration issues; 4) dirty, damaged, or worn-out capillaries/bonding tools; 5) excessive vibrations; 6) reverse motion/looping control problems.

Die Overcoat
Die Overcoat is the process of applying a pliant but moisture-resistive material over the surface of the die for the purpose of minimizing package stresses on the surface of the die and providing additional protection against corrosion. Silicone materials are very effective for this purpose. Die coating may be selective or non-selective. Selective die coating, as the name implies, dispenses overcoat material on certain areas of the die only. Non-selective or full die coating covers the entire surface of the die with overcoat material. The amount of overcoat material dispensed on the die surface should be calculated properly, as excess overcoat material that rise above the ball bond may exert tremendous shearing stresses on the wire, resulting in neck breaks. Die coating entails assembly expenses, so it must be avoided whenever possible. Better die lay-outing, fab processing methods, and circuit designs can make a device less sensitive to package stresses, allowing the elimination of die coating during assembly. Common Die Overcoat-related Failure Mechanisms: Die Stressing - generation of excessive package stresses on the die which may result in electrical failure; this mechanism is alleviated by die overcoating Die Scratch - inducement of any mechanical damage on the die, as when an operator scratches a die with tweezers due to mishandling. Common Causes: insufficient operator training, disorderly workplace, use of improper tools Die Metallization Smearing - depression or deformation of any metal line on the die surface. Common Causes: dirty or worn-out die attach pick-and-place tool, wafer mishandling Die Corrosion - corrosion of the metal lines of the die, often due to the presence of corrosive contaminants and moisture on the die surface Neck Breaking - breakage of the bond wire at the ball bond neck. In the context of die coating, it is usually caused by excessive overcoat material which can exert tremendous shearing stresses at the neck.

Molding/Plastic Encapsulation
Molding is the process of encapsulating the device in plastic material. Transfer molding is one of the most widely used molding processes in the semiconductor industry because of its capability to mold small parts with complex features. In this process, the molding compound is first preheated prior to its loading into the molding chamber. After pre-heating, the molding compound is forced by a hydraulic plunger into the pot where it reaches meltingtemperature and becomes fluid. The plunger then continues to force the fluid molding compound into the runners of the mold chase. These runners serve as canals where the fluid molding compound travels until it reaches the cavities, which contain the leadframes for encapsulation. In conventional flow chambers, the cavities are filled up in a 'christmas tree' fashion, i.e., cavities that are nearer the cull get filled up first. The highest filling velocity is experienced by the first cavity. However, the filling velocity decreases as the first cavity is filled. Subsequent cavities are filled with increasing velocities until the last cavity, which ends up with the second highest filling velocity, next only to the first cavity. As such, the first and last cavities are most prone to wiresweeping and die paddle shift.

Figure 1. Examples of Mold Chases

Figure 2. Examples of Molds

Figure 3. Example of an Automold System

Common Molding-related Failure Mechanisms:


Package cracking - occurrence of fracture anywhere in the package Package stress-related electrical failure - non-conformance to electrical specifications due to component degradation caused by stresses on the die surface Wiresweeping - swaying or movement of the wires during molding along the direction of mold flow which may result in broken wires or wire shorting Package Voids and Pits - imperfections on the package surface (pits) or body (voids) characterized by vacancies of plastic material Incomplete Filling - insufficient encapsulation resulting when the molding compound fails to fill up the cavity during molding Blistering - appearance of blisters on the package surface Package Delamination - any disbonding between the molding compound and another material of the package Excessive Flashes - presence of unacceptable amounts of plastic on the edges of the package after molding Solder Voids - exposure of any part of the lead base metal resulting when excess flashes that covered the leads duringleadfinish are removed Mark Permanence Failure - inability of the entirety of an ink mark to remain on the package

Sealing/Hermetic Encapsulation
Sealing is the process of encapsulating a hermetic package, usually by capping or putting a lid over the base or body of the package. The method of sealing is generally dependent on the type of package. Ceramic DIPs, or cerdips, are sealed by topping the base of the package with a cap using seal glass. Other ceramic packages such as sidebrazed packages, LCC's, and PGA's are sealed by covering the package with a combo lid through solder sealing. A sealing furnace (see Fig. 1) is used to expose the packages to the high temperatures needed to achieve proper sealing. Seal glass, like any glass, is a supercooled liquid which exhibits tremendous viscosity when cooled below its glass transition temperature. A seal glass may be classified as vitreous or devitrifying. Vitreous glass are relatively transparent and can be reworked repeatedly without degradation in its properties. Devitrifying glass can no longer be reworked after crystallizing upon cooling. Fillers are added to seal glass to control the thermal expansion of the glass. A typical cerdip glass sealing process consists of the following steps in its sealing profile: 1) organic burn-off/ougassing; 2) glass densification or softening of glass; 3) glass profile formation (around 350 deg C); 4) chemical bonding between glass and ceramic (around 420 deg C); 5) annealing; and 6) cooldown. Cooldown is more critical than heat-up because this affects the final properties of the glass more greatly.

Welding is used to join the metal header and metal cap of metal cans. A specially-designed welding machine is used to deliver the high currents needed to weld the metal header and metal cap at their interface. Figure 2 shows an example of a lid welding machine. Common Sealing-related Failure Mechanisms: Seal Cracking; Package Cracking; Soft Errors; Pits and Voids;Incomplete Weld

Fig. 1. A Sealing Furnace

Fig. 2. A Lid Welding Machine

Marking
Marking is the process of putting identification, traceability, and distinguishing marks on the package of an IC. The device name, company logo, date code, and lot id are examples of information commonly marked on the IC's package. Some marks are put on the package during Assembly and some marks are put on the package during Test.

There are two common marking processes, namely, ink marking and laser marking. The most common ink marking process for semiconductor products is pad printing. Pad printing consists of transferring an ink pattern from the plate, which is a flat block with pattern depressions that are filled with ink, to the package, using a silicone rubber stamp pad. Silicone rubber repels ink, making the transfer of the ink pattern clean and efficient. It is also resilient and elastic, making it possible to print even on uneven surfaces.

Fig. 1. Photos of Silicone Rubber Pads used for Ink Marking

Simply put, the pad printing process can be broken down into the following steps: a) the stamp pad passes over the surface of the ink; b) the surface ink sticks to the pad; c) the pad is applied to the surface for marking; and d) the ink sticks to the marking surface as the pad lifts. Ink marking is usually punctuated by ink curing.

Aside from mark quality, mark permanence is a critical aspect of IC package marking. Mark permanence failures can be due to a lot of things such as use of inappropriate ink, use of improperly prepared ink, inadequate ink curing, and marking surface contamination. Good wetting of the ink on the marking surface is necessary for good marking. For wetting to occur, the surface tension of the ink must be less than the surface tension of the marking surface. Thus, a careful review and interpretation of the surface tension data of the ink to be used and those of the intended marking surface is needed to ensure good ink marking.

Laser marking, as the name implies, refers to the process of engraving marks on the marking surface using a laser beam. There are many types of lasers, but the ones used or in use in the semiconductor industry include the CO2 laser, the YAG laser, and diode lasers. In the semiconductor industry, lasers can also be used in micromachining, surface processing, trimming, welding, and cutting.

Figure 2. Example of a Laser Marker

Common marking failure attributes include the following: 1) missing mark; 2) missing character; 3) misoriented mark; 4)wrong mark format; 5) misplaced mark; 6) mark permanency failure; and 7) inadequate mark contrast.

Marking Failures
Marking Failures refer to the various ways in which the marking on a device package fails to meet its required visual/physical and chemical specifications. The more commonly encountered marking failure attributes encountered in the industry are presented below. The ability of a package to be marked in accordance with applicable specifications is known as 'markability.' Poor markability is the condition wherein the package is difficult or impossible to mark correctly and/or the mark on the package exhibits insufficient permanence. Ink markability problems are often due to the inability of the ink to adhere to the surface of the package. Laser markability problems are often due to improper branding equipment set-up, but may sometimes be due to textural problems on the surface of the package as well. Poor adhesion of ink marks or brands on the package is usually caused by the presence of a thin film or layer ofcontaminants or foreign material on the package surface. For instance, packages with excessive amounts of mold release agent on their surfaces are likely to exhibit poor markability. It may also be due to the use of an incorrect, incompatible, or expired ink. Common marking failure attributes which are applicable to both ink and laser marking include the following: 1) missingmark, wherein the entire mark is absent from the package; 2) incomplete mark or missing character, wherein only a part of the mark is absent from the package; 3) misoriented mark, wherein a mark appears in incorrect orientation with respect to the package; 4) misplaced mark, wherein a mark is in incorrect location with respect to the package; 5)wrong format, wherein a mark has a different style or character arrangement than what is prescribed; and 6) poor mark contrast. The term 'illegible mark' is also widely used in the semiconductor industry, but this term can often be described more specifically as either an incomplete mark or as a mark with poor contrast. Mark permanency failure, or the failure of a package to retain the quality of its ink mark over a prescribed period of time, is also a critical failure attribute of the ink marking process. The mark permanency test (MPT), which is described by Mil-Std-883 Method 2015, is performed to test the mark permanency of a sample. The MPT subjects the package marking to a set of chemicals which, under normal circumstances, should not be able to erase the mark or a part thereof. Poor laser markability is usually caused by incorrect laser branding settings. Packages with textural problems or defects may likewise exhibit poor contrast after laser marking. For example, reworked packages that have undergone sand blasting generally exhibit marks with poor legibility.

DTFS
Deflash/Trim/Form/Singulation (DTFS) consists of the four steps indicated in its name. These steps are defined below. 1. Deflash - removal of flashes from the package of the newly molded parts.. Flashes are the excess plastic material sticking out of the package edges right after molding. 2. Trim - cutting of the dambars that short the leads together. 3. Form - forming of the leads into the correct shape and position. 4. Singulation - cutting of the tie bars that attach the individual units to the leadframe, resulting in the individual separation of each unit from the leadframe.

Figure 1. Examples of TFS Equipment

Common DTFS-related Failure Mechanisms: Package Cracking - occurrence of fracture anywhere in the package, often due to excessive mechanical stresses imparted by the DTFS process to the package. Die Cracking - occurrence of fracture anywhere in the die. In the context of DTFS, die cracking is commonly caused by excessive mechanical stresses imparted by the DTFS process to the package, which may be transmitted to the die. In some cases, the package will withstand these stresses but the die will not.

Lead Finish
Lead finish, or 'leadfinish', is the process of applying a coat of metal over the leads of an IC to: 1) protect the leads against corrosion; 2) protect the leads against abrasion; 3) improve the solderability of the leads; and 4) improve theappearance of the leads. There are two widely used leadfinish techniques in the semiconductor industry, namely, platingand coating. Further, there are two types of plating, i.e., pure metal plating such as tin plating and alloy plating such as tin/lead plating. Coating is the process of depositing a filler metal (usually solder) over a surface, achieving metallurgical bonding throughsurface wetting. The filler metal should have a melting temperature below 315 degrees Celsius for the process to be classified as coating. The driving force for a solder coating process is surface tension, i.e., wetting of the surface to be coated by the solder must be achieved. A solder diffusion layer grows at the surface-solder interface as solder spreads through the surface during the coating process. Tin plating is a form of pure metal electroplating, which is the process of depositing a coating of metal on a surface by passing a current through a conductive medium, or electrolyte. An electroplating system has four (4) components: 1) the cathode, which is the surface to be coated; 2) the anode, which is the source of coating metal; 3) the electrolyte, the aqueous medium through which the metal ions from the anode transfer to the cathode; and 4) the power source, which supplies the current or energy needed for the plating process.

The cathode, which is the material to be plated, is the electrode where electrons are consumed or where 'reduction'occurs. The anode, which serves as source material for the plating, is the electrode where oxidation occurs, i.e., where electrons and metal ions are released. +2 0 Example of reduction: Sn + 2e => Sn 0 +2 Example of oxidation: Sn => Sn + 2e The energy needed for the plating process to occur is known as the electrochemical potential or voltage. This voltage is the total of three voltages: the reversible potential, the overpotential, and the ohmic potential. If the applied voltage is less than the electrochemical potential, the process of plating will not occur. Solder plating is a form of alloy plating. An alloy is composed of at least two elements, at least one of which is a metal. An alloy has better properties than its component metals: it is harder, more corrosionresistant, has better solderability and better appearance.

Fig. 1. Example of an Electroplating Machine for Lead Finish

Common Lead Finish-related Failure Mechanisms/Attributes: Lead Corrosion - corrosion of the leads due to imperfections in the lead finish Poor Solderability - insufficient wetting of the solder often caused by contaminants, excess additives, and inadequate plate thickness Tin Whiskers - formation of very thin extrusions of tin material from the lead finish that can result in electrical shorts between adjacent pins; observed in pure tin plating or alloy systems with a high content of tin Other Lead Finish Failure Attributes: Solder Dullness, Solder Roughness, Pitting, Tarnishing, Blistering, Dendrites, Nodules, Graininess, Deposits, Burns

Lead Finish Troubleshooting Guides


Tin plating and solder plating are two common lead finish processes used in semiconductor manufacturing. The following tables serve as quick references for troubleshooting problems related to these processes. Table 1 is a troubleshooting guide for tin plating processes, while Table 2 is intended to help with solder plating processes. Table 1. Troubleshooting Guide for Tin Plating Problem
Formation of Dendrites

Cause(s)
Insufficient amount of brightener/ additives/replenishment chemicals Insufficient amount of acid

Remedy
Add more brightener/ additives/replenishment chemicals Add more acid (usually sulfuric acid)

Formation of Nodules Graininess Burning Blistering Pitting

Presence of solids in bath Insufficient replenishment of additive chemicals Insufficient amount of metal High plating current Inadequate or poor cleaning Insufficient replenishment of additive chemicals Insufficient replenishment of additive chemicals Insufficient amount of acid Insufficient amount of metal High plating current High plating voltage High plating current Organic contamination

Filter the bath Add more replenishment chemicals Add stannous sulfate Decrease the plating current Perform proper cleaning Add more replenishment chemicals Add more replenishment chemicals Add more acid (usually sulfuric acid) Add stannous sulfate Decrease the plating current Decrease the plating voltage Decrease the plating current; add anode Conduct carbon treatment

Reduced Throwing Power

Gassing Anode Polarization Formation of Brittle Deposits

Table 2. Troubleshooting Guide for Solder Plating Problem Cause(s)


Organic contamination Inadequate plating thickness Poor Solderability Metallic contamination (Cu > 50 mg/l) Excessive additive content Br > 20 mg/l High metal content Low CD Dullness High bath temperature Insufficient amount of acid Cl > 150 mg/l Insufficient amount of additives Over-all Dullness Low plating current High bath temperature I > 5 mg/l Insufficient amount of additives Poor Throwing Power High metal content for current used Insufficient amount of acid Low Cathode Efficiency Pitting in High Current Areas Tarnishing Anode Polarization Low metal content for current used Insufficient amount of acid Insufficient amount of additives Low metal content for current used Improper rinsing Low plating thickness Pre-plate contamination

Remedy
Perform carbon treatment Increase the plating thickness Subject the bath to dummy plating Dilute the bath or perform carbon treatment Dilute the bath Adjust the bath; use inert anode Cool the bath to 65 deg F Add more acid Dilute the bath Increase additive content Increase the plating current Cool the bath to 65 deg F Dilute the bath Increase additive content Adjust the current; dilute the bath Add more acid Adjust the current; increase the metal content Add more acid Increase additive content Increase the metal content Perform post-rinsing Increase plating thickness Eliminate pre-plate contaminants

Presence of sludge in the bath or basket Filter the bath; clean the anodes

Insufficient amount of additives Burning High plating current Low metal content Presence of stannic tin in the bath Cloudy/Turbid Solution Presence of chlorides or sulfates in the bath Presence of stannic tin in the bath Roughness Presence of insolubles in the bath Presence of lead precipitates in the bath Foaming High additive content Incorrect bath Sn/Pb Ratio Problems Poor bath agitation Presence of nitrates in the bath

Increase additive content Decrease the plating current Increase the metal content Subject the bath to appropriate treatment Filter the bath and eliminate the source of chlorides and sulfates Subject the bath to appropriate treatment Filter the bath Filter the bath and eliminate the source of precipitates Perform carbon treatment Adjust the bath composition Increase bath agitation Dilute the bath and eliminate the source of nitrates

Flip-Chip Assembly
The term flip-chip refers to an electronic component or semiconductor device that can be mounted directly onto a substrate, board, or carrier in a face-down manner. Electrical connection is achieved through conductive bumps built on the surface of the chips, which is why the mounting process is face down in nature. During mounting, the chip is flippedon the substrate, board, or carrier, (hence the name flip-chip), with the bumps being precisely positioned on their target locations. Because flip chips do not require wirebonds, their size is much smaller than their conventional counterparts. The flip-chip concept is not new, having been around as early as the 1960s when IBM used them for their mainframes. Since then, various companies have developed the flip-chip for use in thousands of different applications, taking advantage of the size and cost benefits offered by this assembly method. Flip chips have likewise eliminated performance problems related to inductance and capacitance associated with bond wires.

Fig. 1. Structure of a Flip Chip BGA The flip chip is structurally different from traditional semiconductor packages, and therefore requires an assembly process that also differs from conventional semiconductor assembly. Flip chip assembly consists of three major steps: 1) bumping of the chips; 2) face-down attachment of the bumped chips to the substrate or board; and 3) under-filling, which is the process of filling the open spaces between the chip and the substrate or board with a non-conductive but mechanically protective material. Given the many different materials and technologies used in the bumping, attachment, and underfilling steps, the flip chip now comes in a vast array of variants.

Flip-chip Bumping Physically, the bump on a flip-chip is exactly just that a bump formed on a bond pad of the die. Bumps serve various functions: 1) to provide an electrical connection between the die and the board or substrate; 2) to provide thermalconduction from the chip to the board or substrate, thereby helping dissipate heat from the flip chip; 3) to act as spacerfor preventing electrical shorts between the die or chip circuit and the board or substrate circuit; and 4) to providemechanical support to the flip-chip. There are many known processes for flip-chip bumping. Solder bumping consists of placing underbump metallization (UBM) over the bond pad by sputtering, plating, or a similar means. This process of putting UBM removes the passivating oxide layer on the bond pad and defines the solder-wetted area. Solder may then be deposited over the UBM by a suitable method, e.g., evaporation, electroplating, screenprinting, needle-depositing, etc. This entire process of solder bumping is done at wafer level. Solder-bumped wafers are sawn into individual flip-chips that get mounted on a board or substrate by subjecting the assembly to a temperature thats high enough to melt the solder, forming the interconnection. Another type of flip-chip bumping is whats known as plated bumping. Plated bumping removes the oxide layer on the Al bond pad through wet chemical cleaning processes. Electroless nickel plating is then employed to cover the Al bond pad with a nickel layer to the desired plating thickness, forming the foundation of the bump. An immersion gold layer is then added over the nickel bump for protection. Stud bumping is another flip-chip bumping process. This technique is very similar to gold ball bonding in the sense that it starts by melting the end of the wire to form a free-air ball or sphere, which is then attached to the bond pad. Unlike wirebonding though, the wire is broken off the ball bond after the latter has been attached to the bond pad. Gold stud-bumped flip chips may be mounted on a board or substrate using conductive adhesives or by thermosonic gold-to-gold interconnection. Adhesive bumping is a flip-chip bumping process that stencils electrically conductive adhesive over an underbump metallization placed over the bond pad. The stenciled adhesive serves as the bump after it has been cured. Mounting of adhesive-bumped flip-chips also uses conductive adhesives.

Fig. 2. Example of a Solder Bump Structure Flip-Chip Underfilling The open spaces between the flip chip surface and the board or substrate is filled with a non-conductive adhesiveunderfill material to protect the bumps and the flip chip surface from moisture, contaminants, and other environmental hazards. More importantly, this underfill material mechanically locks the flip chip surface to the board or substrate, thereby reducing the differences between the expansion of the flip chip and the substrate. This prevents the bumps from being damaged by shear stresses caused by differences between the thermal expansions of the chip and the substrate. Flip-chip underfilling is achieved by needle dispensation (Fig. 5) along the edges of the flip-chip. Capillary action then draws the dispensed underfill inwards, until the open spaces are filled. Thermal curing is then performed to form the permanent bond.

Fig. 3. Photos of an underfill dispensing machine (left) and an underfill dispensing tool (right)

Tape Automated Bonding (TAB)


Tape Automated Bonding, or simply TAB, is the process of mounting a die on a flexible tape made of polymer material, such as polyimide. The mounting is done such that the bonding sites of the die, usually in the form of bumps or balls made of gold or solder, are connected to fine conductors on the tape, which provide the means of connecting the die to the package or directly to external circuits. Sometimes the tape on which the die is bonded already contains the actual application circuit of the die. The TAB bonds connecting the die and the tape are known as inner lead bonds (ILB), while those that connect the tape to the package or to external circuits are known as outer lead bonds (OLB). The tape used in Tape Automated Bonding is usually single-sided, although two-metal tapes are also available. Copper, a commonly-used metal in tapes, can be electrodeposited on the tape or simply attached to the tape using adhesives. The metal patterns of the circuit are imaged onto the tape by photolithography. Standard sizes for polyimide tapes include widths of 35 mm, 45 mm, and 70 mm and thicknesses between 50 to 100 microns. Since the tape is in the form of a roll, the length of the circuit is measured in terms of sprocket pitches, with each sprocket pitch measuring about 4.75 mm. Thus, a circuit size of 16 pitches is about 76 mm long.

Fig. 1. Example of TAB devices

To facilitate the connection of the die bumps or balls to their corresponding leads on the TAB circuit, holes are punched on the tape where the die bumps will be positioned. The conductor traces of the tape are then cantilevered over the punched holes to meet the bumps of the die. There are two common methods of achieving a bond between the gold bump of the die and the lead of a TAB circuit: 1) single-point thermosonic bonding; and 2) gang or thermocompression bonding. Single-point bonding, as the name implies, connects each of the die's bond site individually to its corresponding lead on the tape. Heat, time, force, and ultrasonic energy are applied to the TAB lead,

which is positioned directly over the gold bump, forming intermetallic connections between them in the process. Single-point bonding is a more time-consuming process than gang bonding. Gang bonding employs a specially designed bonding tool to apply force, temperature, and time to create diffusion bonds between the leads and bumps, all at the same time. Without the use of ultrasonic energy, this type of bonding is simply referred to as 'thermocompression' bonding. Gang bonding offers a high throughput rate, and is therefore preferred to single-point bonding. After gang bonding, the die, bonds, tape leads, and part of the tape are covered with an encapsulant, which provides mechanical and chemical protection to the circuit after its curing. The die is then electrically tested, after which the useable part of the tape is punched from the frame for assembly into the final application.

Fig. 2. Examples of Tape Automated Bonding Equipment

Tape Automated Bonding offers the following advantages: 1) it allows the use of smaller bond pads and finer bonding pitch; 2) it allows the use of bond pads all over the die, not just on the die periphery, and therefore increases the possible I/O count of a given die size; 3) it reduces the quantity of gold needed for bonding; 4) it limits variations in bonding geometry; 5) it has a shorter production cycle time; 6) it results in better electrical performance (reduced noise and higher frequency); 7) it allows the circuit to be physically flexible; and 8) it facilitates multi-chip module manufacturing. Tape Automated Bonding, on the other hand, has the following disadvantages: 1) time and cost of fabricating the tape; 2) the need to 'tailor-fit' the tape pattern after each die; and 3) capital expense for TAB equipment since TAB manufacturing requires a set of machines different from those used by conventional processes. Thus, Tape Automated Bonding is a better alternative to conventional wirebonding if very fine bond pitch, reduced die size, and higher chip density are desired. It is also the technique of choice when dealing with circuits that need to be flexible, such as those that experience motion while in operation, e.g., printers, automotive applications, folding gadgets, etc. Tape Automated Bonding is generally more costeffective for use in high-volume production, since returns on the time and cost of developing the tape will be maximized under this situation.