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02-08-12, 10:37
#1
R1kky
Newbie level 3
could you, please, help me with several questions regarding std cells & libraries. 1. what it (std cells libraries) can be (i.e. classification on vt,coarse-grain, fine-grain etc) my suppose - vt could be high or low, also as mentioned coarse- or fine- grain, what else? 2. what track is? my suppose - tracks mean routing resources, track is the path in which wires can pass through. One track is approximately the minimum spacing between metal1 and metal2 via in a technology node . Track is generally used as a unit to define the height of the std cell. For example, a 12 track cell will be taller than a 9 track cell, a 12 track std cell will be taller, that means more metal1 routing space is available within the cell, hence cells will be faster. where as in a 9 track cell, the cell will be compact, but speed is less compared to 12 track. 3. how many metal level using in std cells? my suppose - 2 or 3 levels 4. what groups of std cells libraries consist? (for example, filler my suppose - even don't know, as told there A standard cell library is a collection of low-level logic functions such as AND, OR, INVERT, flipflops, latches, and buffers. These cells are realized as fixed-height, variable-width full-custom cells. The key aspect with these libraries is that they are of a fixed height, which enables them to be placed in rows, easing the process of automated digital layout. The cells are typically optimized fullcustom layouts, which minimize delays and area. A typical standard-cell library contains two main components: Library Database - Consists of a number of views often including layout, schematic, symbol, abstract, and other logical or simulation views. From this, various information may be captured in a number of formats including the Cadence LEF format, and the Synopsys Milkyway format, which contain reduced information about the cell layouts, sufficient for automated "Place and Route" tools. Timing Abstract - Generally in Liberty format, to provide functional definitions, timing, power, and noise information for each cell. A standard-cell library may also contain the following additional components: A full layout of the cells Spice models of the cells Verilog models or VHDL Vital models Parasitic Extraction models DRC rule decks An example is a simple XOR logic gate, which can be formed from OR, INVERT and AND gates. so from that i can point only "logical elements group", what else? thanks in advance.
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02-08-12, 11:58
#2
soloktanjung
Full Member level 6
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The number of metal layers depend on the foundry and the technology (45 nm, 65 nm). I have used 130 nm technology with 6 metal layers. Thank you.
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02-08-12, 12:10
#3
R1kky
Newbie level 3
The number of metal layers depend on the foundry and the technology (45 nm, 65 nm). I have used 130 nm technology with 6 metal layers. Thank you.
thanks for answer, is it correct, that used number of levels of metal for whole SoC and for stnd cell libs is the same number or it differs?
03-08-12, 12:01
#4
soloktanjung
Full Member level 6
that used number of levels of metal for whole SoC and for stnd cell libs is the same number or it differs?
I dont quite understand your question. In my design, I have a logic + memory block both using 130 nm and 6 metal layers in one die. Thank you.
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06-08-12, 08:41
#5
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1/18/13
oratie
Full Member level 3
06-08-12, 11:51
#6
soloktanjung
Full Member level 6
Usually, the std cell library contains only Metal1, sometimes it may contain M2. I never saw more than 2 metal layers in the std. cell library.
08-08-12, 07:46
#7
jeet_asic
Full Member level 3
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08-08-12, 07:58
#8
oratie
Full Member level 3
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08-08-12, 08:09
#9
jeet_asic
Full Member level 3
Sorry , my bad. But i didn't get this line. Sir can you elaborate this little more.
08-08-12, 08:37
#10
Somashekhar
Member level 1
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