A FAMILY OF ISOLA

CAPACITORS FO
Paulo C. V. Luz, Marcelo R. Cose
Abstract This paper presents a
electronic systems to supply power lig
(LEDs) for street lighting system a
systems are analyzed aiming to reduce
de circuit, to eliminate electrolytic ca
them for film capacitors. The film capa
due to their long lifetime, compatible w
This is possible through control techn
keeping an appropriate relationshi
current distortion and the acceptable r
current. The integration of the powe
made to increase the system reliabilit
number of controlled switches. T
designed to supply 32 power LEDs c
and supplied with 700 mA, resultin
systems aim to high power factor and
distortion (THD) of the input curren
IEC 61000-3-2 standard.

Keywords Isolated driver, long life
street lighting.
I. INTRODUCTION
The LEDs are very attractive to street
to their characteristics, like high luminou
lifetime. These devices have also other
to lighting system, like high color render
and easy dimming, when compared to lig
on discharge lamps [1-3].
The lighting systems with power ov
proposed circuits, need to comply with
standard, which limits the level of harm
input current [4]. An efficient way to
factor correction is using DC/DC conver
system designed to supply the LEDs t
shown in Figure 1, where the power fact
and the power control (PC) stages ar
represented by blocks.
Conventional drives to supply LED
capacitors, because it is necessary to filt
absorbed by the mains to supply the P
capacitors limit the circuit lifetime
capacitors present lifetime around 10,0
LEDs lifetime can reach 80,000 hours [
the goal is to decrease the converter ca
substitute the electrolytic capacitors for
with longer lifetime.

ATED INTEGRATED DRIVERS W
OR LIGHT SYSTEM BASED ON PO

etin, Priscila E. Bolzan, Thiago Maboni, Rica
IEEE
Group of Intelligence in Lighting GEDRE
Federal University of Santa Maria - UFSM
paulocesarluz@gedre.ufsm.br


family of isolated
ght emitting diodes
applications. These
the capacitances of
pacitors or replace
acitors were chosen
with LEDs lifetime.
niques applications,
ip between input
ripple of the output
er system stages is
ty by reducing the
The systems were
connected in series
ng in 70 W. The
low total harmonic
t, according to the
etime, power LEDs,
N
t lighting system due
us efficacy and long
good characteristics
ing index, small size
ghting systems based
ver 25 W, like the
the IEC 61000-3-2
monic content in the
perform the power
rters [2, 3, 5-7]. The
to street lighting is
tor correction (PFC)
re static converters
Ds use electrolytic
ter the pulsed power
PC stage. But these
e. The electrolytic
00 hours, while the
[2]. For that reason,
apacitances value to
another technology
Fig. 1. System
The power stages integ
decrease the number of
command drivers, increasing
applied integration technique
II. INTEGRATE
The developed topologi
between the PFC stage and t
analyzed separately and con
analysis of each stage is prese
A. PFC stage
Static converters are
conduction mode (DCM) t
stage, because that the conve
a resistance for the mains. T
converters were evaluated to
shown in Figure 2, with the
output voltage waveforms.
(a) Bu
(b) Bo
(c) Buck-
Fig. 2. PFC converters anal
WITH REDUCED
OWER LEDS
ardo N. do Prado, Member,
m to supply the LEDs
gration is proposed aiming to
controlled switches and their
g the system reliability [8]. The
e is proposed by Wu [9].
ED CONVERTERS
ies are a result of integration
the PC stage. Each stage can be
ntains one static converter. The
ented below.
working in discontinuous
to the power factor correction
erter has the same behavior than
he Buck, Boost and Buck-Boost
o work in the PFC stage and are
input current, input voltage and
uck-PFC

ost-PFC

Boost-PFC

lyzed and their main waveforms
The Buck converter presents the step-
which means that it has input current o
voltage is bigger than the output voltage
distortion of the input current. For that
voltage of the PFC stage has a maximum
IEC 61000-3-2 standard. Considering t
220 V
RMS
/60 Hz (mains), the maximum o
V [10].
The input current distortion of Boo
dependent of the output voltage. Th
presents a minimum output voltage to
factor correction. Considering the
220 V
RMS
/60 Hz, the minimum output vo
The Buck-Boost converter presents u
and it has no limit of output voltage to at
the other hand, the output voltage o
inverted when compared with the i
characteristic can be a limiting factor in th
B. PC stage
The Flyback converter is used to p
because they offer electric isolation betw
and output. This converter was chose
simplicity and lower number of comp
compared with other topologies, like the
and Push-Pull converter.
It is not indicated to operate the F
continuous conduction mode (CCM)
overvoltage characteristic in the contro
was analyzed and designed to operat
conduction mode (DCM). The convert
mode can also results in a lower out
shown in [11].
C. Integrated Topologies
With the PFC and PC stages ope
switching frequency and same duty c
integrated. The PFC circuits were inte
circuit, resulting in three different topolo
the common point between the switche
switch of the integrated topology w
overvoltage (OV) or overcurrent (OC)[
switch receives the sum of voltages from
the OC the switch receives the sum of
stages [13]. The integration between
Flyback converter (BuFly) results in an O
shown in Figure 3. The other two i
Flyback (BoFly) and Buck-Boost-Flybac
in an OC characteristic. They are shown i
Fig. 3. Buck-Flyback (BuFly) OV

-down characteristic,
only when the input
e. This implicate in a
t reason, the output
m value to attend the
the input voltage of
output voltage is 130
ost converter is also
he Boost converter
o ensure the power
input voltage of
ltage is 410 V [10].
unitary power factor
ttend the standard. In
of this converter is
nput voltage. This
he project.
power control stage,
ween the system input
en also because its
ponents, when it is
e Forward converter
Flyback converter in
) because of the
olled switch, then it
te in discontinuous
er operation in this
tput capacitance, as
erating in the same
cycle, they can be
grated with the PC
ogies. Depending on
s of each stage, the
will be subject to
[12]. In the OV the
m both stages, and in
f currents from both
the Buck and the
OV characteristic, as
integrations, Boost-
ck (BuBoFly), result
in Figure 4.

V Integration
(a) Boost-Fl
(b) Buck-Boost-F
Fig. 4. OC
III. DESIGN O
Each converter of each st
a non-integrated converter.
converter in cascade.
A. Duty cycle (D)
The maximum duty cycl
first point to be defined. The
bus voltage and it needs be
power factor correction (in
and not generate overvoltag
duty cycle for each converter
BuFly, BoFly and BuBoFly,
B
BuFly
in
V
D
V
=
(
Bus
BoFly
B
V
D
V
=

(
PK
BuBoFly
in
V
D
V
=
Where V
Bus
is the bus vol
voltage.
B. Inductor of the PFC stage
The inductor of the PFC
input power definition (4).
0
1 R
n
T
R
i
= P p
T

Where T
R
is the ma
instantaneous input power o
calculated by (5).
( ( ) )
in
=V t p t
Where V
in
(t) and I
in
(
instantaneous values in the sy
lyback (BoFly)

Flyback (BuBoFly)

C Integrations
OF TOPOLOGIES
tage operates in the same way as
Thus it is possible design the
le of the circuit must to be the
duty cycle value depends of the
defined such that to ensure the
the Buck and Boost converter)
ge in the switch. The maximum
r is defined in (1), (2) and (3), to
respectively.
PK
Bus
n
V

(1)
)
PK
in
Bus
V
(2)
)
Bus
Bus
V
V +

(3)
ltage and V
inPK
is the mains peak
e
C stage can be calculated by the
( ) t dt p
(4)
ains period and p(t) is the
of the converter and it can be
) (
in
I t (5)
(t) are voltage and current
ystem input.
It is possible replace the I
in
(t) value b
by switching period (T
S
), of the input
converter. Thus the inductances of the
BuBoFly can be calculated by the equati
and (8), respectively.
I
Bu
=

Bu
2
P
n
.
I
S
I
R
_ |I
n
(t). (I
n
(t)
t
Bu2
t
Bu1
I
Bo
=

Bo
2
P
n
.
I
S
I
R
_ _I
n
(t). _1 +
I

I
n
(t)
T
R
2
0
I
BuBo
=

BuBo
2
P
n
.
I
S
I
R
_ I
n
(t)
T
R
2
0
Where T
S
is the switching period and
conduction angles of Buck converter, calc
1
arcsin
2
PK
Bus
in
R
Bu
V
=
V
T
t

and
2 Bu
t =
C. Flyback coupling
The inductance value of the PC stag
using the same definition of average pow
in the inductor of PFC stage. Where p(t)
Flyback converter input power, given by
( )
Bus P s Fl T y
=V iL t p (t)
Where <iL
P
(t)>
Ts
is the average v
period of primary winding current in the
shown in (11).
2
( )
2
S
P Ts Bus
P
D T
iL t V
L

Thus, the equation (12) defines th
inductance of Flyback converter.
2
2
0
2
S
P Bus
D T
L =V
P

Where Po is the output power of the c
The equation of the processed energy
be used to calculate the secondary windin
2
0
1 1
2
PK
S S
S
P L iL
T
=
Where iLs
PK
is the peak current in the
and can be calculated by (14).
0
2
(1 )
PK
S
OFF
I
iL
D D

=


Where D
OFF
is defined to ensure
discontinuous conduction mode of the Fly
Thus, the secondary winding inducta
converter can be calculated by (15)
transformation ratio is given by (16).

by the average value,
current in the PFC
e BuFly, BoFly and
ion shown in (6), (7)
- I
Bus
)]Jt (6)
n
(t)
) +I
Bus
]_ Jt
(7)
)
2
Jt
(8)
d t
Bu1
and t
Bu2
are the
culated in (9).
1
2
R
Bu
T
t (9)

ge can be calculated
wer that was applied
), in this case, is the
(10).
(10)
value for switching
e Flyback converter,
(11)
he primary winding
(12)
converter.
y by the coupling can
ng inductance, (13).
(13)
e secondary winding
(14)
e the operation in
yback converter.
ance of the Flyback
and the coupling
I
S
=
P
0
I
S
2
. _
1 -
P
S
L
n =
L
D. Output capacitor (C
out
)
To calculate the capacitor
is divided in two parts. The
(Io
HF
), produced by the swi
frequency (Io
LF
) produced
in two times the mains frequ
Figure 5.
Fig. 5. Current

Thus, it is possible write t
0 0
HF
I I = +
0 0
LF LF
V I =
0 0
HF HF
V I =
Where Vo
HF
and Vo
L
and low frequency and R
L
model. Therefore it is consi
(C
out
) is responsible to the
(C
Bus
) is responsible for the ri
From the capacitor br
calculate the capacitor value
02
01
0
1
HF
t
out
t
C =
V

Where iC
o
(t) is the outp
(21). The time between t
o1
e
maximum variation of volt
words it is all the time in
negative). Those times are ca
iC
0
(t) = iI
S
t
01
= . I
S

and
02
t
Where iL
S
(t) is the secon
output current and V
out
is the
-
0PP
Io
] (15)

(16)
r, the ripple in the output current
e first one is in high frequency
itching. The second one is in low
by the ripple in the bus voltage,
uency. The ripple is shown in the
t ripple in the LEDs
the following equations:
0
LF
I
(17)
LEDs
R
(18)
LEDs
R
(19)
LF
are the voltage ripple in high
LEDs
is resistance of the LEDs
idered that the output capacitor
Io
HF
filter and the bus capacitor
ipple in 120 Hz.
ranch equation is possible to
by the equation (20).
0
( ) iC t dt
(20)
put capacitor current, given by
t
o2
is the time in that occurs the
tage in the capacitor, in other
n that the iC
o
(t) is positive (or
alculated by (22).
S
(t) - I
0

(21)
2
Bus S out
S
out out
V D T I
= L
V n V

(22)
ndary winding current, I
O
is the
e converter output voltage.
E. Bus capacitor (C
Bus
)
The same equation idea of the output capacitor can be
applied to the bus capacitor. The equation is shown in (23).
C
Bus
=
1
I
Bus
_ iC
Bus
(t)Jt
t
b2
t
b1
(23)
Where iC
Bus
(t) is the bus capacitor current, given by (24),
(25) and (26) for each one the integrated topology, BuFly,
BoFly and BuBoFly, respectively.
( ) ( )
S S
Bu Bu T P T
iC (t)= iL t iL t
(24)
( ) ( )
S S
Bo Bo T P T
iC (t)= iD t iL t
(25)
( ) ( )
S S
BuBo BuBo T P T
iC (t) = iD t iL t
(26)
Where <iL
Bu
(t)>
Ts
, <iD
Bo
(t)>
Ts
and <iD
BuBo
(t)>
Ts
are the
average values for switching period of the Buck inductor,
Boost diode and Buck-Boost diode, respectively.
The integration limit of equation (23) represents the range
of greater voltage variation in the capacitor.
The ripple in the bus voltage (V
Bus
) is calculated in
function of the low frequency current ripple in the LEDs, as
shown in (27).
0
0
( )
LF
b
Bus
V V
V
V
G s

=
(27)
Where G
VoVb
(s) is the Flyback converter transfer
function, it relates the output voltage variations and
disturbances in the bus voltage, it is given by (28).
0
2
2 2
2
( )
1
2
b
S
P out
V V
Bus S
LED out out out P
D T
n L C
G s
V D T
s
R C V C L

=

+ +




(28)
The bus voltage ripple is found considering the ripple of
output voltage sinusoidal with double of mains frequency
and amplitude Vo
LF
/2.
F. Project results and simulation
The topologies were designed to supply 32 power LEDs
connected in series and its nominal current is 700 mA,
resulting in approximately 70 W. The maximum ripple of the
LEDs current was defined 50%. The input voltage is
220 V
RMS
/60 Hz. The main parameters are shown in Table I.

TABLE I
Results of calculated projects
BuFly BoFly BuBoFly
VBus (V)
90 450 400
Duty (%)
28 28 40
L (H)
212 856 677
LP (mH)
0.055 1.38 2.23
NP/NS
0.42 4.24 3.19
CBus (F)
100 10 13
Cout (F)
10 1 1
All topologies were simulated to verify the projects. The
main results are shown in Table II. It is possible to see that
all the topologies have high power factor (PF) and low total
harmonic distortion (THD) in the input current. All the
topologies also meet the IEC 61000-3-2 standard.

TABLE II
Main simulation results
BuFly BoFly BuBoFly
VDSnax (V)
473 934 765
IsRMS (A)
1.84 0.55 0.94
IsPico (A)
6.22 2.15 3.29
ILEDs (mA)
700 700 700
ILEDs (%)
47 62 48
THD (%)
19.3 21.8 1.21
FP (%)
98.1 97.6 99.9

IV. REDUCTION OF THE CAPACITANCES
The capacitors can be decrease through the control
techniques of output current of the converters, because the
ripple can be corrected by the control law and not only
through these components. It is possible through the high
control speed and the high gain associated with the
undulation frequency. But if the control law be very fast, the
equivalent resistance of the PFC converter, shown in (29),
can change a lot inside the same period of the mains, losing
the linearity and increase the input current distortion,
described by (30).
R
PPC
=
2 I
S

2

(29)
Where R
PPC
is the equivalent resistance of the converter,
I is the PFC converter inductance and
S
is the switching
frequency.
i
n
(t) =
I
n
(t)
R
PPC
(30)
Where i
n
(t) is the converter input current and I
n
(t) is
the main voltage.
For this reason it is necessary have a strict relation
between the acceptable current ripple in the LEDs, control
speed and input current harmonic distortion, aiming to obtain
low values of capacitance.
The higher capacitor of the topologies is the bus one, due
the input pulsed power and the continuous voltage required
in the output PFC converter. This way, the control technique
need be able to decrease the undulation associated to this
capacitor, i.e. in 120 Hz
A PI controller was analyzed for the topologies, because
it can offer zero error in permanent regime to the average
value for the control variable.
An evaluation of the controller behavior was done, where
the PI compensator parameters are adjusted to change the
gain in 120 Hz. Due the control actuation, the current ripple
is decreased. Thus the bus capacitor can be decreased until
the current ripple reach the nominal value or until the input
current disagree with the standard.
The Figure 6 shows the variation of the minimum bus
relative capacitance (compared with the nominal value) in
function of the gain of the compensator in 120 Hz for each
topology, aiming to keep the output current ripple in 50%
and to comply with the standard.
Fig. 6. Minimum bus capacitor vs gain in 120Hz

The graphic shows that the BuFly topology starts to do
not comply with the standard since a gain of 5 dB in 120 Hz
and for that reason, the capacitor starts to be higher than the
nominal. The BoFly topology needs a capacitor higher than
the nominal until a gain of 0 dB in 120 Hz and stabilizes in a
gain of 15 dB, due the standard. The BuBoFly decrease the
capacitance value in all the tested gains and stabilizes in a
gain of 25 dB due the standard.
The Table III shows the parameters of the chosen
compensator for each topology, the bus capacitor and the
current ripple in the LEDs.

TABLE III
Compensators
BuFly BoFly BuBoFly
C
u.uuS47S
(s +Su264)
s
u.uS87
(s +Su264)
s
u.u8476
(s +Su264)
s
CBusR
61 F 3.5 F 2 F
Io
50% 47% 46%
V. EXPERIMENTAL RESULTS
The BoFly converter was implemented to validate the
project and simulation results, although all topologies are in
implementing process. The converter parameters
implemented are in the Table I.
The Figure 7 shows the open loop results of the
converter. It is possible to realize that the LEDs average
current is approximately 700mA and the ripple is almost
350mA (50%). The bus voltage value and the output power
are approximately 450 V and 70 W, respectively.
The Figure 8 shows the closed loop results of the
converter. It was implemented with the Integrated Circuit
SG 3524. The average values are according to the projected
values, but the output current ripple is lower than the
projected value because of the control action, the ripple is
280mA (40%).
Fig. 7. Bus voltage (Ch1 500 V/div), Current in the LEDs
(Ch2 500 mA/div), LEDs voltage (Ch3 100V/div) and Output
power (ChM 50W/div) 2 ms/div
Fig. 8. Bus voltage (Ch1 500 V/div), Current in the LEDs
(Ch2 500 mA/div), LEDs voltage (Ch3 100V/div) and Output
power (ChM 50W/div) 2 ms/div
Due the ripple decrease in the LEDs current, it is possible
decrease the bus capacitor to maintain the ripple value equal
the projected. The Figure 9 shows the results with the bus
capacitor in 3.5 F.
Fig. 9. Bus voltage (Ch1 500 V/div), Current in the LEDs
(Ch2 500 mA/div), LEDs voltage (Ch3 100V/div) and Output
power (ChM 50W/div) 2 ms/div
The converter behavior was the expected. The action
control decreased the LEDs current ripple, making possible
decrease the bus capacitor value to achieve the projected
LEDs current ripple. The bus capacitor of 3.5F (as seen in
Table III) maintained the ripple in 50%. Then, the action
control was efficient to reduce the bus capacitor.
The Figure 10 shows the converter input voltage, current
and power, to the circuit with closed loop and C
Bus
=3.5F. It
is possible to realize that the efficiency is approximately
84%.
0
0.2
0.4
0.6
0.8
1
-15 -10 -5 0 5 10 15 20 25
R
e
l
a
t
i
v
e

c
a
p
a
c
i
t
a
n
c
e
Gain in 120 Hz (dB)
Buck - Flyback Boost - Flyback Buck-Boost - Flyback
Fig. 10. Input voltage (Ch1 250 V/div), Input current (Ch2
1A/div) and Input power (ChM 100W/div) 4 ms/div
The Figure 11 shows the comparison by harmonic
content in the converter input current with the IEC 61000-3-2
standard, for the three situations. All of them agree with the
standard. It is possible to see the increasing of the
disagreement with the standard when the control is applied
and when the bus capacitor is decreased.
Fig. 11. Comparison between harmonic content and the
IEC 61000-3-2 class C standard
VI. CONCLUSIONS
This paper showed integrated converters family to supply
power LEDs applied in street light systems. The proposed
integration of power stages resulted in the reduction of
controlled switches, as well as its drives. It is possible
decrease the capacitors of the topologies with control actions
to decrease the current ripple in the LEDs. This way, it is
possible to replace electrolytic capacitors for other
technology with higher lifetime, resulting in higher lifetime
to the system, compatible with the LEDs.
Other objectives were also achieved, like high power
factor (0.93) and low harmonic content of input current
(29.0%), meeting the international standard IEC 61000-3-2
to class C devices. The circuit has still high efficiency, 84%.

ACKNOWLEDGEMENT
The authors gratefully acknowledge the CAPES for the
financial support.
REFERENCES
[1] Fusheng Li; Dahua Chen; Xianjie Song; Yuming Chen.
LEDs: A promising energy-saving light source for road
lighting, Power and Energy Engineering Conference,
APPEEC 2009, pp. 1-3, May 2009.
[2] Wu Chen; S. Y. R. Hui. "Elimination of an electrolytic
capacitor in AC/DC light-emitting diode (LED) driver
with high input power factor and constant output
current, IEEE Transaction on Power Electronics, vol.
27, pp. 1598-1607, March 2012.
[3] L. Gu; X. Ruan; M. Xu; K. Yao; Means of eliminating
electrolytic capacitor in AC/DC power supplies for LED
lightings, Power Electronics, IEEE Transaction, vol.
24, pp. 1399-1408, May 2009.
[4] R. A. Pinto; M. R. Cosetin; J. G. Roncalio; M. Melo; T.
B. Marchesan; J. M. Alonso; M. A. Dalla Costa; R. N.
do Prado. High-power-factor street lighting system to
supply LEDs without energy consumption during the
peak load time, 37th Annual Conference on IEEE
Industrial Electronics Society, pp. 2947-2952 IECON
2011.
[5] J. M. Alonso; A. J. Calleja; D. Gacio; J. Cardesin; E.
Lopez. A long-life high-power-factor HPS-lamp LED
retrofit converter based on the integrated buck-boost
buck topology, IECON 2011 37th Annual Conference
on IEEE Industrial Electronics Society, pp. 2860-2865,
2011.
[6] D. G. Lamar; J. Sebastian; M. Arias; A. Fernandez. On
the limit of the output capacitor reduction in power-
factor correctors by distorting the line input current,
IEEE Transaction on Power Electronics, vol. 27, pp.
1168-1176, 2012
[7] T. B. Marchesan. Two flyback-based integrated
converters for the implementation of LFSW electronic
ballasts, Industry Applications Conference, 2007, 42nd
IAS Annual Meeting, Conference Record of the 2007
IEEE, issue 23, pp. 463-470, September 2007.
[8] X. Xiaojun; A. Q. Huang. A novel closed loop
interleaving strategy of multiphase critical mode boost
PFC converters, Applied Power Electronics Conference
and Exposition, 2008. APEC 2008, Twenty-Third
Annual IEEE, Fev. 2008.
[9] Tsai-Fu Wu; Yu-Kai Chen. A systematic and unified
approach to modeling PWM DC/DC converters based
on the graft scheme, IEEE Transactions on
Industrial Electronics, vol.45, no.1, pp.88-98, doi:
10.1109/41.661309, 1998.
[10] Kirsten, A. L. Reator eletrnico para lmpadas de
descarga em alta presso baseado no conversor biflyback
inversor. 2011. Dissertation (Masters degree in
electrical engineering) Federal University of Santa
Maria, Santa Maria, 2011;
[11] J. M. Alonso; A. J. Calleja; D. Gacio, F. Sichirollo, M.
F. da Silva, M. A. Dalla Costa, R. N. do
Prado. Reducing storage capacitance in off-Line LED
power supplies by using integrated converters Industry
Applications Society Annual Meeting (IAS), 2012 IEEE,
pp. 1-8, 2011.
[12] Marchesan, T. B. Integrao de conversores estticos
aplicados a sistemas de iluminao publica. 2007.
Thesis (PhD in electrical engineering) Federal
University of Santa Maria, Santa Maria, 2007;
[13] J. M. Alonso, J. Calleja, F. J. Ferrero, E. Lopez, J. Ribas,
M. Rico Secades, Single-stage constant-wattage high-
power-factor electronic ballast with dimming capability
in Proc. IEEE Power Electron. Specialist Conf.,
Fukuoka, Japan, vol. 2, pp. 13301336, May 1998.
0.0
0.1
0.2
0.3
Open Loop - C
Bus
=10F
Harmonic Content
IEC 61000-3-2 Class C
0.0
0.1
0.2
0.3
Closed Loop - C
Bus
=10F
0.0
0.1
0.2
0.3
3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
Closed Loop - C
Bus
=3.5F