IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO.

9, SEPTEMBER 2007

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A 0.2-mW 2-Mb/s Digital Transceiver Based on Wideband Signaling for Human Body Communications
Seong-Jun Song, Student Member, IEEE, Namjun Cho, Student Member, IEEE, and Hoi-Jun Yoo, Senior Member, IEEE

AbstractThis paper presents a low-power wideband signaling (WBS) digital transceiver for data transmission through a human body for body area network applications. The low-power and highspeed human body communication (HBC) utilizes a digital transceiver chip based on WBS and adopts a direct-coupled interface (DCI) which uses an electrode of 50- impedance. The channel investigation with the DCI identies an optimum channel bandwidth of 10 kHz to 100 MHz. The WBS digital transceiver exploits a direct digital transmitter and an all-digital clock and data recovery (CDR) circuit. To further reduce power consumption, the proposed CDR circuit incorporates a low-voltage digitally-controlled oscillator and a quadratic sampling technique. The WBS digital transceiver chip with a 0.25- m standard CMOS technology has 2-Mb/s 7 , dissipating only 0.2 mW data rate at a bit error rate of 1.1 from a 1-V supply generated by a 1.5-V battery.

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Index TermsBody area network (BAN), clock and data recovery (CDR), digital transceiver, digitally-controlled oscillator (DCO), human body communication (HBC), quadratic sampling, wideband signaling (WBS).

I. INTRODUCTION

ECENT advances in semiconductor technologies and computing systems have enabled the proliferation of mobile and portable electronic devices in the ubiquitous mobile computing environment. A wearable computing technology is an example for the user to easily place such devices around the human body. The wearable electronic devices (e.g., wrist-type computers, earphones, video eyeglasses, and head-mounted displays) and sensors offer the potential for a wide range of applications from health management to personal entertainment [1], [2]. Since such devices are distributed on the human body, a body area network (BAN) can provide connectivity between each wearable device within the communication range of the human body, corresponding to 12 m. Moreover, it should be powered by a very small battery in order to minimize its physical size, and be connected through simple interfaces for convenience of use. Since the wearer utilizes wearable electronic devices and sensors continuously anytime and anywhere, the devices require a low-power data transceiver employing
Manuscript received November 6, 2006; revised April 16, 2007. The authors are with the Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Daejeon 305-701, Korea (e-mail: tornado@eeinfo.kaist.ac.kr; buzm@eeinfo.kaist.ac.kr; hjyoo@ee.kaist.ac.kr). Digital Object Identier 10.1109/JSSC.2007.903080

energy-efcient communication schemes and also the high data rate operation needs for exchanging multimedia data such as audio or video over BANs. There are two approaches to implementing the BAN: one exploiting the human body itself as a transmission medium and the other using external mediums such as wire and air. Traditional wireline technologies such as USB On-The-Go that provides a point-to-point link between portable devices can provide high data rates but needs long copper wires which are generally cumbersome for human body applications [3]. The radio-frequency (RF) short-range personal area connection using Bluetooth can provide more practical usability. However, it has potential problems such as low data rate, high power consumption, and vulnerability to interference at the 2.4-GHz frequency band [4]. Even the Zero-G receiver [5] for achieving significant power savings over the Bluetooth radios still consumes too much power. On the other hand, the novel wireless communication method utilizing the body as a data communication medium, the human body communication (HBC), can operate with good signal-to-noise ratio (SNR) performance in the low-frequency band. Thus, the HBC is an attractive wireless connection technology for achieving both the high data rate operation and the low power consumption. Recently, several HBC schemes have been suggested for the BAN and their data transferred through the skin of the human body. The near-eld electrostatic coupling scheme using a narrowband low-frequency signal was rst introduced by Zimmerman [6] and expected to signicantly reduce power consumption. His coupling scheme is strongly dependent on the conditions of the surrounding environment like the earth ground for the return path and has limited data rate of 2.4 kb/s due to the narrow bandwidth of 400 kHz. Another scheme employing an electromagnetic wave of 10 MHz also suffers from the bandwidth limitation of conventional FM and FSK [7]. Recently, another group reported a transceiver adopting electroopic conversion method to achieve higher data rate of 10 Mb/s by using a special off-chip sensor [8]. However, it leads to high cost, high power consumption, and large physical size for human body applications. Moreover, it must have two electrodes, signal and ground, which make it inconvenient to use. This paper presents a novel HBC scheme exploiting wideband signaling (WBS) technique with a direct-coupled interface (DCI) over the optimized HBC channel. The HBC channel is optimized for high-speed operation on the human body. The

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Fig. 1. Conceptual block diagram of the human body communication with a direct-coupled interface through a human body.

DCI is an interface method connecting the silicon chip with the human body directly. It uses only a single electrode for data transmission without any intentional ground electrode, in contrast to other methods which require an off-chip sensor to detect the feeble electric eld and the earth ground path. In addition, the 2-Mb/s WBS digital transceiver chip is implemented by a 0.25- m standard CMOS technology. The digital transceiver consumes 0.2 mW of power from a 1-V supply. Therefore, the proposed HBC scheme can achieve lower power consumption with high data rate operation than other HBC schemes in [6][8], which make it suitable for the application to energy-efcient point-to-point data transmission around the human body using the BAN. The proposed HBC using the DCI on the human body is illustrated in Fig. 1. The HBC transceiver with the DCI does not need an off-chip component or a sensor to detect electric eld. Thus, it can fully integrate all functional blocks on a silicon chip excluding a signal electrode, thereby achieving low cost and small physical size. Also, the WBS with the optimized HBC channel can provide energy-efcient data transmission to extend the lifetime of the battery. The paper is organized as follows. The communication channel characteristics of the human body are investigated in Section II. Section III describes the WBS digital transceiver with the detail explanation of its main building blocks such as the direct digital transmitter and the all-digital quadratic sampling clock and data recovery (CDR) circuit, including the external receiver analog front-end (AFE) block. Chip fabrication and measurement results are explained in Section IV. Finally, the conclusion is given in Section V. II. CHANNEL CHARACTERISTICS The transmission characteristics of the HBC channel have been investigated by using RF signals from 1 MHz to 40 MHz [7] and from 1 MHz to 3 GHz [9]. However, the frequency characteristics presented in [7] were obtained by using a pair of signal and ground electrodes and only the frequency domain

response was reported in [9]. In this paper, for the potential optimization of the WBS transceiver with the DCI, the characteristics of the HBC channel are investigated in the time and frequency domains by using only a single signal electrode without any intentional ground electrode or path. Fig. 2 illustrates the measurement setup for the time and frequency domains. The distance between a transmitter and a receiver is xed at 15 cm. The I/O impedances for the transmitter and the receiver are 50 . As shown in Fig. 2(a), a battery-powered crystal-based transmitter is connected to the forearm with a single Ag/AgCl electrode. An electrode as the receiver is connected to a digital oscilloscope and its ground is oated to parasitically couple it with the signal ground of the transmitter through air in consideration of its usage in the real situation. In this setup, the transmitter transfers the electrostatic pulse through the forearm to the oscilloscope with parasitic coupling of the earth ground by the electric eld. Fig. 3(a) shows the measured output waveform for the time-domain characteristics. For a square wave of 3 V at 2 MHz, the channel outputs are measured to be the positive and negative pulse signals with no DC offset. Each pulse signal exhibits a narrow small pulse signal with a width of about 8 ns corresponding to a bandwidth of 125 MHz and the amplitude of 90 mV. In order to obtain the characteristics of the human body over the frequency sweep without any purposeful ground electrode, a signal generator is exploited as a transmitter and its ground is connected to the common ground of the oscilloscope as shown in Fig. 2(b). The signal generator generates the sinusoidal waves with 1-V peak-to-peak in the frequency range from 100 Hz to 1 GHz. Fig. 3(b) indicates the measured frequency-domain characteristics. The human body behaves as a bandpass lter with a bandwidth of about 100 MHz and shows approximately 6-dB attenuation. This behavior is attributed to the capacitive coupling through the parasitic ground path for the return signal and the small input impedance of 50 . Further study on the considerable characteristics of the HBC channel such as the characteristics versus the distance and the antenna effect of the body is reported in [10]. According to this investigation, the range of 10 kHz to 100 MHz is founded as the suitable frequency for the WBS over the HBC channel. Therefore, the wide bandwidth HBC channel enables the WBS transceiver to operate at the high data rate. Based on the channel investigation, a HBC channel model is developed to optimize the performance of the WBS transceiver over the channel. An electrical circuit model of Fig. 4 for the WBS HBC system with the DCI is obtained by extending a , , and previous simplied electrical circuit model ( ) for the biological tissues [11] to the human body model. The capacitance value of , a parasitic capacitor associated with the parasitic air coupling as the return path between the ground of the transmitter and the receiver, is very small (several and are added as pF) due to the feeble coupling. the transmission loss model associated with the coupling to the (50 ) receivers ground path above about 1 MHz. (50 ) are the output and input impedances of the and is the input transmitter and the receiver, respectively. load capacitance of the receiver. Fig. 5 shows the HBC channel characteristics simulated by using the circuit model in the time and frequency domains.

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Fig. 2. Measurement setup for the investigation of the HBC channel (a) in the time domain and (b) in the frequency domain.

Fig. 3. Measured characteristics of the HBC channel (a) in the time domain and (b) in the frequency domain.

According to the safety study of the human exposure to the RF signals, the minimum electric eld intensity is 28 V/m over the frequency range up to 300 GHz for general public exposure to time-varying electric elds [12]. The maximum electric eld intensity is roughly estimated at 20 V/m and the induced displacement current is much less than 45 mA, because the human body impedance exhibits the range of 300 to 500 over the frequency range of 10 kHz to 100 MHz [12]. All measurement conditions meet the ICNIRP guidelines [12] as well as the IEEE recommendations to provide an electrical safety for the human body [13]. III. WBS DIGITAL TRANSCEIVER The HBC transmission is based on the WBS scheme that directly transmits binary digital signal through a transmitter into the human body, transfers wideband pulse signals over the HBC channel, and then recovers the binary data at the receiver. The WBS has two features: simple interface and high data rate capability. The WBS enables the use of only a single electrode for the data transmission. A transceiver exploiting the WBS is

connected to the human body with a single Ag/AgCl or metal electrode. The grounds of the transmitter and the receiver are parasitically coupled each other. The earth ground path for a return signal is not implemented and only the parasitic ground coupling exists. In addition, since the WBS is independent to the conditions of surrounding environments such as the earth ground, the data transmission using the WBS enables stable operation for the situation even if a part of the human body is touched to the ground, which is rather special compared with [6]. The WBS provides the maximum data rate of 125 Mb/s. According to the time-domain characteristics as shown in Fig. 3(a), the data rate can go up to about 125 Mb/s because the pulse bit signal has a width of about 8 ns. According to the channel investigation, several design requirements can be dened in realizing the data transmission with WBS technique. A WBS transceiver operating at the high data rate of 2 Mb/s can transfer the real-time multimedia data streams such as MP3 le without any encoding and decoding. For the longer lifetime of a very small battery, a power less than 10 mW is required with a 1-V supply. The 1-V supply voltage

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007

Fig. 4. Electrical circuit model for the WBS HBC system with the DCI.

Fig. 5. Simulated characteristics of the HBC channel using the electrical circuit model (a) in the time domain and (b) in the frequency domain.

is below the sum of the threshold voltage of nMOS and pMOS. This can eliminate short circuit currents for the digital circuits, thereby minimizing unnecessary power consumption [14]. For the transmission of the binary data, the nonreturn-to-zero (NRZ) is chosen to enable clock recovery from data transitions with no additional timing reference at the receiver. Accordingly, the transmitter is designed to drive the NRZ data over the human body channel. The receiver requires small input impedance to move the low-frequency pole away from the origin in the frequency spectrum. It can cut off the low-frequency interference noises including the baseline wandering below 0.5 Hz and powerline interference of 60 Hz. To facilitate the high-speed measurements, the 50- impedance was chosen to match with the impedance of the equipments. The 3-dB operational bandwidth of about 200 MHz at the receiver is chosen to sufciently sustain the channel bandwidth without inter-symbol interference (ISI) effects. To achieve the transmission between the ngertip and the ear, corresponding to 100-cm distance, the voltage gain should be larger than 30 V/V, and the minimum input sensitivity, the minimum received pulse swing, is to be 10 mV. Since the channel output signal is com-

prised of positive and negative pulses without DC offset, the symmetric operation is demanded. A clock and data recovery function requires a bit error rate (BER) less than 10 for the embedded clocking which includes the clock timing information into the data in NRZ data service. Fig. 6 shows the block diagram of the WBS transceiver that comprises a direct digital transmitter and a CDR-based WBS receiver. The direct digital transmitter consists of a clock synthesizer, a pseudo-random binary sequence (PRBS) generator, a 2-to-1 multiplexer (MUX), and a driver. The clock synthesizer has a ring oscillator structure and generates the clock signal with frequency scaling to activate the PRBS generator. The PRBS generator generates 2 1 PRBS data and transmits them through the driver to the human body for on-chip link testing. Also, external binary data such as digitally converted audio data or baseband data can be directly transmitted to the human body by the 2-to-1 MUX. The driver is connected to the electrode and induces the electric eld on the skin of the human body. The CDR-based WBS receiver consists of a receiver AFE, a CDR circuit, and a bit error detector. The receiver AFE amplies, triggers, inverts, and shifts the received wideband

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Fig. 6. Proposed architecture of the wideband signaling transceiver.

pulse signal in order to recover the binary data. The next CDR circuit extracts a clean clock signal from the recovered binary data and latches the data. The bit error detector is integrated for on-chip BER testing and detects error bits of the recovered data from the extracted clock for 2 1 PRBS. The transceiver is powered by a supply regulator, which generates the supply voltage of 1 V from a 1.5-V battery. Fig. 7 illustrates the timing diagrams of the WBS transceiver operation. As investigated in Section II, when the binary data is directly inserted into the human body, the channel outputs a narrow small pulse signal that comprises positive and negative pulses with no DC offset. The received pulse signal which may be corrupted by the channel is sufciently amplied for wide bandwidth, and subsequently, the signal is triggered to positive and negative states by using two symmetric thresholds, and , where the symmetric operation provides the duty cycle of 50%. Consequently, the binary data can be recovered by inverting and shifting the triggered signal. For CDR at the receiver, the full-rate clock signal is locked at the center point of the bit interval window. The binary data is recovered by latching the level-shifted signal at the rising edge of the clock signal. The WBS transceiver should operate over the wide bandwidth of 200 MHz in order to recover binary data from the wideband pulse signals. However, it increases power dissipation inherently. Particularly, since the receiver AFE and the CDR circuit are the crucial elements and power-hungry building blocks, the low-power techniques are necessary for their designs. For these reasons, the WBS digital transceiver incorporates four low-power techniques: direct digital transmission, all-digital CDR architecture, low-voltage digitally-controlled oscillator (DCO), and quadratic sampling technique. These techniques allow the WBS digital transceiver to signicantly reduce power consumption along with high data rate operation, which results in more energy-efcient data transmission than other transceivers [6][8] over the HBC channel.

Fig. 7. Timing diagrams for the operation of the WBS transceiver.

A. Direct Digital Transmitter Fig. 8 shows the detailed block diagram of the direct digital transmitter. The digital signal can be directly transmitted to the body by exploiting the WBS scheme. This voltage-mode transmission approach can considerably save power consumption of the HBC transmitter because it needs only an inverter-type driver without modulation blocks. The clock signal is generated from the ring oscillator and scaled by the frequency divider. The ratio of the frequency dividing is chosen by the 7-bit thermometer decoder. The PRBS generator as a binary data source . The voltage-mode is based on the polynomial of driver as a single inverter makes it difcult to maximize the transmitting power over the body due to the variation of its output impedance. To maximize the transmitting power along with the constant output impedance, the driver exploits a double inverter topology, combining a single inverter and an identical inverter with drain resistors. Fig. 9 depicts the schematic diagrams for three voltage-mode drivers: a single inverter, an iden-

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Fig. 8. Detailed block diagram of the direct digital transmitter.

Fig. 9. Schematic diagrams for three voltage-mode drivers: (a) a single inverter, (b) an identical inverter with drain resistors, and (c) a double inverter in the combination with (a) and (b).

tical inverter with drain resistors, and a double inverter. Fig. 10 illustrates the contour lines of the output impedance for three voltage-mode drivers, plotting the amount of the current transferred to the body as a function of the voltage at the drivers output. Since the body impedance exhibits the range of 300 to 500 over the frequency band with 100 MHz as mentioned in Section II, the transistors size (35 m/10 m) is large enough to drive the large human body capacitance (about 15 pF) and the drain resistor (200 ) is chosen for matching to the body impedance. The drivers output impedance is constant to almost 400 by controlling the output impedance of each inverter with the input voltage as shown in Fig. 10(c). It indicates that the transmitting power increases almost two times more than the conventional approaches. Accordingly, the proposed double inverter topology allows the increase of the transmitting power while maintaining its output impedance. B. WBS Receiver AFE According to the channel investigation, the output signal of the channel shows narrow small pulse signals with no DC offset, when the binary data is directly applied to the human body by a single electrode. These characteristics seem to be similar with the AC-coupled chip-to-chip interconnect using 50- transmission lines on a FR-4 PC board shown in [15]. The pulse receiver used in the AC-coupled interconnect achieves high data

rate of several Gb/s. However, it had a differential structure and poor receiver sensitivity more than 100 mV with a 1.8-V supply. The WBS transceiver requires that the input sensitivity of a receiver AFE should to be less than 10 mV for the 50input impedance. Fig. 11 shows the block diagram of the external WBS receiver AFE consisting of three blocks: a wideband preamplier, a Schmitt trigger, and a level shifter. The AFE accomplishes four tasks: amplifying, triggering, inverting, and shifting. Signal waveforms at each output are the same as those in Fig. 7. The wideband preamplier is designed as a noninverting opamp with a wide bandwidth that provides sufcient amplication to the received pulse although it is corrupted by the channel. The next Schmitt trigger stably triggers the output of the preamplier to positive and negative states with two thresholds against the variation of the received pulse swing. The Schmitt trigger consists of three resistors ( - ) and the same opamp as that of the preamplier. It produces positive and ). Each and negative triggering threshold voltages ( threshold voltage is chosen as the value of two times smaller than the output swing of the preamplier, enough to trigger at and are expressed as the half of the pulse signal. Thus,

(1)

(2) and are the received positive and respectively, where is the voltage gain of negative pulse swings, respectively, the preamplier given as , 10 V/V in this design, and is the supply voltage of the AFE, 1.5 V in this design. According to the design requirements of the WBS transceiver, the minimum input pulse swing is 10 mV. Hence, the values of and are 50 mV and 50 mV, respectively. Subsequently, the output signal is inverted and shifted up to ground level by for the digital input at the bias voltage of the next CDR circuit. The level shifter can be implemented by

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Fig. 10. Contour lines of the output impedance for three voltage-mode drivers: (a) a single inverter, (b) an identical inverter with drain resistors, and (c) a double inverter.

Fig. 11. Block diagram of the WBS receiver AFE.

Fig. 12. Quadratic sampling CDR architecture based on a low-voltage DCO.

using an inverting opamp with the reference voltage of . In order to verify the performance of the external receiver AFE, an on-chip AFE is implemented by using a 0.18- m standard CMOS process [16]. The AFE can operate at 10 Mb/s while consuming a power of only 4.8 mW with a 1-V supply. C. Quadratic Sampling CDR Circuit In human body communications, a stream of the binary data transfers over a human body with no clock accompanied, but a receiver must process the data synchronously. Thus, to extract a clean clock from the stream of the binary data and synchronize the data by the extracted clock, the WBS digital trans-

ceiver employs a CDR circuit that is exploited in areas such as optical communications and high-speed serial links or interconnects [17]. Since the transceiver operates at relatively low data rates for the recovered binary data, differently from gigabit serial links [17], bandwidth-limited effects such as ISI or amplitude noise and clock frequency offset between a transmitter and a receiver are tolerable in the WBS transceiver. Hence, it is desirable for the CDR circuit to be focused on low power consumption rather than high-speed operation. However, under V, an analog CDR circuit the condition of may experience performance degradation. But the power dissipation of digital circuitry is proportional to the square of the

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Fig. 13. Circuit diagram of a single delay stage of the low-voltage DCO.

Fig. 15. Simulated QSPD characteristic.

Fig. 14. (a) Timing operation and (b) detailed block diagram of the QSPD.

supply voltage. Therefore, the transceiver adopts an all-digital sampling CDR architecture based on a low-voltage DCO. To further reduce power consumption and complexity, a quadratic sampling technique is incorporated. The proposed CDR circuit takes an all-digital PLL conguration as shown in Fig. 12. It consists of a quadratic sampling phase detector (QSPD), a lockstate controller, a 4-bit UP/DN counter, and a low-voltage DCO with voltage reference. The QSPD samples the incoming data at every rising edge of the clock and detects the transition of the data. The 4-bit FT signals can be generated by averaging and low-pass ltering the sampled values through the lock-stage controller and the 4-bit UP/DN counter. When the LC signal of Fig. 12 goes high, the loop will be locked. The DCO controlled

by FT[3:0] is designed to generate 16 multi-phase clock signals for quadratic sampling. In order to further reduce power consumption, the low-voltage DCO and the quadratic sampling technique are used. Fig. 13 shows the circuit diagram of a single delay stage of the low-voltage DCO with eight delay stages. The pMOS differential input pair ( ) is used to achieve lower icker noise and large input capacitance. The delay stage takes a fully differential structure based on the switched nMOS capacitor arand ) that are digitally controlled by rays ( FT[3:0] for ne tuning [18]. To secure stable oscillation against the variation of the resistor loads ( ), the cross-coupled - . The increpair ( ) is adopted in parallel with mental timing delay of the unit capacitance ( ), 25 fF in this for design, should be smaller than a sampling time interval the stability of the capture behavior. For coarse tuning of the ossignal, generated by cillation frequency of the DCO, the a voltage reference with off-chip trimming, controls the amount ) is of the tail current ( ). The bias capacitor pair (

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Fig. 16. (a) Quadratic sampling algorithm and (b) comparison of the PD characteristics in the conventional and proposed CDRs.

Fig. 17. Acquisition behavior for the quadratic sampling CDR circuit. Fig. 18. Microphotograph of the test chip.

needed to improve the linearity of the DCO gain characteristics. According to the simulations, the tuning range of the DCO shows 1.1 MHz with the tuning gain of 60 kHz/bit. The power consumption of the single delay stage is only 14 W. Fig. 14(a) illustrates the timing operation of the QSPD. The incoming data (DIN) is sampled by the 16 sampling clocks (CK0CK15) with a uniform interval between sampling clocks. A bit interval window of the DIN is split into seven regions with respect to the position of the data transition. Each region has the quadratic interval, which is based on bilateral symmetry with region 4 as the central region. When the data transition is at regions 1, 2, or 3, the down signal (DN4, DN2, or DN1) goes high, respectively. The LC signal goes high for region 4. Three up signals (UP1, UP2, and UP4) show the same operation as the down signals at regions 5, 6, and 7, respectively. Fig. 14(b) shows the detailed block diagram of the QSPD for the timing operation. Fig. 15 plots the simulated QSPD characteristic, indicating the difference of the UP[2:0] and DN[2:0] signals as a function of the delay between the sampling clock CK0 and the input data DIN. The output of the QSPD shows the seven-level phase detection (solid line). Thus, the OSPD accomplishes the quadratic phase detection (dash line) by averaging and low-pass ltering through the lock-state controller and the 4-bit UP/DN counter. Fig. 16 illustrates the proposed quadratic sampling algorithm in (a) and the comparison of the PD characteristics between the

proposed quadratic sampling (solid line) and the conventional linear sampling (dash line) in (b). The QSPD generates the 3-bit UP, LC, and 3-bit DN signals that are produced by XORing two consecutive bits of the DIN signal with the quadratic interval window. All of them are converted to 4-bit twos complement values before weighting and averaging functions. To avoid potential loop instability, the averaged values are low-pass ltered by a simple digital lter. Then, the low-pass ltered values are used to generate the UDN and CCK signals. Based on this algorithm, the QSPD provides the quadratic gain over a bit interval window as depicted in Fig. 16(b). To acquire the same PD gain with the sampling time interval ( ), the conventional CDR with a linear PD needs 32 sampling clocks in the FT[3:0] range of 0100 to 1100. It leads to the increase of the number of the VCO delay stages as well as the sampling block in the PD. Hence, the linear PD characteristic should be paid additional power consumption and area costs. In other words, with the help of the quadratic gain characteristics, the number of sampling clock signals can be reduced by a factor of two against the linear approach. Therefore, the quadratic sampling can further reduce both the power consumption and the area overhead. Fig. 17 illustrates the simulated acquisition behavior of the quadratic sampling CDR circuit, plotting the code value of the 4-bit FT signals as a function of time. Its acquisition time is about 45 s.

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Fig. 21. Measured eye diagrams of the WBS digital transceiver for 2-Mb/s 2 1 PRBS.

Fig. 19. Photograph of the test board.

Fig. 20. Photograph of the test measurement setup. Fig. 22. Measured eye diagrams of the WBS receiver AFE for 2-Mb/s 2 PRBS.

01

IV. MEASUREMENT RESULTS The proposed WBS digital transceiver is fabricated with a 0.25- m standard 1P4M CMOS technology, where the threshold voltage for nMOS and pMOS at saturation region are 0.6 V and 0.65 V, respectively. Fig. 18 shows the microphotograph of the test chip, including the WBS digital transmitter and receiver. Its core area is about 0.85 mm . A test board powered by a 1.5-V battery is shown in Fig. 19. The metal electrode on the test board is composed of a gold plate with the size of 5 mm 7 mm. The Ag/AgCl electrode, 2 cm in diameter, is also connected to the board. The electrode for the signal transmission is chosen between the metal and Ag/AgCl electrodes by using a slide switch on the board. The transceiver chip was mounted on the FR-4 PC board by using chip-on-board assembly. The board size is about 6 cm by 10 cm. All measurements are conducted between the wrist and the ngertip, which corresponds to the distance of about 25 cm as shown in Fig. 20. A WBS transmitter board is attached to the wrist using a single Ag/AgCl electrode on the backside. When the ngertip touches the metal electrode on a WBS receiver board, the stream of the binary data is transferred through the body to the WBS receiver board. Fig. 21 shows the measured eye diagrams of each output of the direct digital transmitter, the HBC channel, the receiver AFE, and the recovered clock and data of the CDR circuit for 2-Mb/s 2 1 PRBS data, respectively. The channel output of the binary data exhibits the narrow small pulse signals with the

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Fig. 23. Measured jitter histograms of (a) the recovered clock output and (b) the recovered data output for 2-Mb/s 2

01 PRBS.

Fig. 24. Free-running characteristics of the DCO.

amplitude of about 50 mV and no DC offset. Fig. 22 shows the measured eye diagrams of each output of the wideband preamplier, the Schmitt trigger, and the level shifter at the WBS receiver AFE for 2-Mb/s 2 1 PRBS data, respectively. The recovered clock and data jitter are measured to be 1.6 ns rms and 1.7 ns rms, respectively, as shown in Fig. 23. Fig. 24 shows the simulated and measured free-running characteristics of the DCO, plotting after slightly controlling the amount of the tail current. This plot indicates that the measured DCO gain and tuning range are about 40 kHz/bit and 800 kHz, respectively. The frequency difference between the simulated and measured curves is attributed to the variation of the unit capacitance in the switched nMOS capacitor array. Since the capacitor array is laid out in symmetry with copying of a unit capacitor to minimize the mismatches between capacitors, the DCO characteristics keep positive linearity over the full tuning range as shown in Fig. 24. Thus, there is no malfunction on the frequency and phase tracking in accordance with the measurement results. The measured receiver input pulse swing as a function of the communication distance from the ngertip to the ear for 2-Mb/s 2 1 PRBS data is shown in Fig. 25. The measurement for the receiver input pulse swing is conducted between a ngertip and an ear, corresponding to the communication distance of 100 cm to prove the feasibility of the data transmission over a human body for an audio application utilizing the proposed HBC scheme. It indicates that the receiver input pulse swing rapidly decreases to the minimum input sensitivity of 10 mV, where the BER is measured to be about 1.1 with the on-chip bit error detector by counting error bits for

Fig. 25. Measured receiver input pulse swing as a function of the communication distance.

TABLE I PERFORMANCE SUMMARY OF THE PROPOSED WBS DIGITAL TRANSCEIVER

2 1 PRBS data. The overall digital transceiver chip consumes 0.2 mW from a 1-V supply. Table I summarizes the performance of the proposed WBS digital transceiver. The performance comparison with previous works is summarized in Table II. The power consumption of an on-chip receiver AFE for the WBS transceiver is 4.8 mW [16]. Thereby, the WBS transceiver including the receiver AFE dissipates a total power of 5 mW and achieves the transmission bit

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TABLE II PERFORMANCE COMPARISON WITH OTHER HBC TRANSCEIVERS

energy of 2.5 nJ/bit, which is 26 times more efcient than other HBC transceivers introduced in [6][8]. Hence, the proposed WBS digital transceiver achieves low power and high data rate operation suitable for energy-efcient data communications for BANs. V. CONCLUSION A novel HBC scheme is proposed and implemented for energy-efcient data communications using the human body as a data transmission medium. From the investigation of the HBC channel using the DCI, the human body behaves as a bandpass lter with a bandwidth of 100 MHz and the channel output exhibits the narrow small pulse signals with a width of 8 ns. The proposed HBC scheme exploits WBS technique with the DCI over the optimized HBC channel. For the convenience of usage, the DCI uses only a single electrode without an extra ground electrode for data transmission. With the help of four low-power techniques such as direct digital transmission, all-digital CDR architecture, low-voltage DCO, and quadratic sampling technique, the WBS digital transceiver achieves 2-Mb/s operation with power consumption of 0.2 mW from a 1-V supply. The minimum input sensitivity of the receiver exhibits about 10 mV in the range of the communication disat a BER of 1.1 tance of 100 cm. REFERENCES
[1] S. Kim, J.-Y. Lee, S.-J. Song, N. Cho, and H.-J. Yoo, An energy-efcient analog front-end circuit for a sub-1-V digital hearing chip, IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 876882, Apr. 2006. [2] R. L. Ashok and D. P. Agrawal, Next-generation wearable networks, IEEE Computer Mag., vol. 36, no. 11, pp. 3139, Nov. 2003. [3] T. B. Remple, USB on-the-go interface for portable devices, in Proc. IEEE Int. Conf. Consumer Electronics, 2003, pp. 89. [4] H. Komurasaki, T. Sano, T. Heima, K. Yamamoto, H. Wakada, I. Yasui, M. Ono, T. Miwa, H. Sato, T. Miki, and N. Kato, A 1.8-V operation RF CMOS transceiver for 2.4-GHz-band GFSK applications, IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 817825, May 2003.

[5] S. Verma, J. Xu, M. Hamada, and T. H. Lee, A 17-mW 0.66-mm direct-conversion receiver for 1-Mb/s cable replacement, IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 25472554, Dec. 2005. [6] T. G. Zimmerman, Personal Area Networks (PAN): Near-eld intrabody communication, M.S. thesis, MIT, Cambridge, MA, 1995. [7] K. Hachisuka, A. Nakata, T. Takeda, Y. Terauchi, K. Shiba, K. Sasaki, H. Hosaka, and K. Itao, Development and performance analysis of an intra-body communication device, in Proc. Transducers 03, Jun. 2003, pp. 17221725. [8] M. Shinagawa, M. Fukumoto, K. Ochiai, and H. Kyuragi, A neareld-sensing transceiver for intrabody communication based on the electrooptic effect, IEEE Trans. Instrum. Meas., vol. 53, no. 6, pp. 15331538, Dec. 2004. [9] J. A. Ruiz, J. Xu, and S. Shimamoto, Propagation characteristics of intra-body communications for body area networks, in Proc. IEEE Consumer Communications and Networking Conf., 2006, pp. 509513. [10] N. Cho, J. Yoo, S.-J. Song, S. Kim, and H.-J. Yoo, The human body characteristics as a signal transmission medium for intra body communication, IEEE Trans. Microw. Theory Tech., to be published. [11] L. C. Ward, N. M. Byrne, K. Rutter, L. Hennoste, A. P. Hills, B. H. Cornish, and B. J. Thomas, Reliability of multiple frequency bioelectrical impedance analysis: An intermachine comparison, Amer. J. Human Biol., vol. 9, pp. 6372, 1997. [12] Int. Commission on Non-Ionizing Radiation Protection (ICNIRP), Guidelines for limiting exposure to time-varying electric, magnetic, and electromagnetic elds (up to 300 GHz), Health Phys., vol. 74, pp. 494522, 1998. [13] IEEE Standard for Safety Levels with Respect to Human Exposure to Radio Frequency Electromagnetic Fields, 3 Hz to 300 GHz, IEEE C95.1-1991, 1999. [14] H. Neuteboom, B. M. J. Kup, and M. Janssens, A DSP-based hearing instrument IC, IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 17901806, Nov. 1997. [15] L. Luo, J. M. Wilson, S. E. Mick, J. Xu, L. Zhang, and P. D. Franzon, 3 Gb/s AC coupled chip-to-chip communication using a low swing pulse receiver, IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 287296, Jan. 2006. [16] S.-J. Song, N. Cho, S. Kim, and H.-J. Yoo, A 4.8-mW 10-Mb/s wideband signaling receiver analog front-end for human body communications, in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), 2006, pp. 488491. [17] S.-J. Song, S. M. Park, and H.-J. Yoo, A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique, IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 12131219, Jul. 2003. [18] S. B. Anand and B. Razavi, A 2.75 Gb/s CMOS clock recovery circuit with broad capture range, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2001, pp. 214215.

SONG et al.: A 0.2-MW 2-MB/S DIGITAL TRANSCEIVER BASED ON WIDEBAND SIGNALING FOR HUMAN BODY COMMUNICATIONS

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Seong-Jun Song (S01) received the B.S. (summa cum laude) and M.S. degrees in electrical engineering and computer science from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2001 and 2004, respectively. He is currently working toward the Ph.D. degree in electrical engineering and computer science from KAIST. Since 2001, he has been a Research Assistant at KAIST, where he worked on developing high-speed optical interface integrated circuits using submicron CMOS technology, phase-locked loops and clock and data recovery circuits for high-speed data communications, and radio-frequency CMOS integrated circuits for wireless communications. His current research interests include ultra low-power wearable/implantable biomedical microsystems and energy-efcient communication systems for body area and sensor networks.

Namjun Cho (S04) received the B.S. (summa cum laude) and M.S. degrees from the Korea Advanced Institute of Science and Technology (KAIST), Korea, in 2004 and 2006, respectively. He is currently working toward the Ph.D. degree at KAIST. He has worked on developing UHF RFID tag chip integrated with environmental monitoring sensors and the low-power digital-to-analog converter for hearing aid system. His current research interests include low-power biomedical microsystems and the wireless transceivers for body area networks.

Hoi-Jun Yoo (M95SM04) graduated from the Electronic Department of Seoul National University, Seoul, Korea, in 1983 and received the M.S. and Ph.D degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 1985 and 1988, respectively. His Ph.D. work concerned the fabrication process for GaAs vertical optoelectronic integrated circuits. From 1988 to 1990, he was with Bell Communications Research, Red Bank, NJ, where he invented the two-dimensional phase-locked VCSEL array, the front-surface-emitting laser, and the high-speed lateral HBT. In 1991, he became Manager of a DRAM design group at Hyundai Electronics and designed a family of fast-1 MDRAMs and synchronous DRAMs, including 256M SDRAM. From 1995 to 1997, he was a faculty member with Kangwon National University. In 1998 he joined the faculty of the Department of Electrical Engineering at KAIST. In 2001, he founded a national research center, System Integration and IP Authoring Research Center (SIPAC), funded by Korean government to promote worldwide IP authoring and its SOC application. From 2003 to 2005, he was the Project Manager for SoC in Korea Ministry of Information and Communication. His current interests are SOC design, IP authoring, high-speed and low-power memory circuits and architectures, design of embedded memory logic, optoelectronic integrated circuits, and novel devices and circuits. He is the author of the books DRAM Design (Seoul, Korea: Hongleung, 1996; in Korean) and High Performance DRAM (Seoul, Korea: Sigma, 1999; in Korean). Dr. Yoo received the Electronic Industrial Association of Korea Award for his contribution to DRAM technology in 1994 and the Korea Semiconductor Industry Association Award in 2002.