Computer Architecture

EG 2204 CT Total: 7 hour /week Year: II Lecture: 4 hours/week Semester: II Tutorial: hours/week Practical : 3 hours/week Course Description: This course is an introduction to computer architecture and organization. It covers topics in both the physical design of the computer (organization) and the logical design of the computer (architecture). Course Objectives: After completing this course the student will able to: 1. explain the over view of computer organization 2. explain the principle of CPU system 3. explain the principle of memory system 4. explain the principle of data flow Course Contents: Unit 1. Basic computer architecture: [6] 1.1 Introduction History of computer architecture Overview of computer organization Memory Hierarchy and cache External Memory Organization of hard disk 1.2 Instruction codes Stored program organization-Indirect address Computer Registers Common bus system Computer instruction Instruction set 1.3 Timing and Control-Instruction Cycle: Fetch and decode Limiting errors 1.4 Type of Instruction Register reference Instruction Memory reference instruction Input and output interrupt Unit 2. Micro programmed control: [8] 2.1 Basic Computer Design of Accumulator Control of AC register Adder and logic circuit ALU organization 2.2 Control Memory-Address Sequencing Conditional Branching Mapping of Instruction-Subroutines

2.3 Micro program Symbolic Micro program Binary Micro program 2.4 Design of control unit Basic requirement of control unit Structure of control unit Hard wired control unit Micro program sequencer Unit 3. Central processing Unit: [12] 3.1 General Register Organization: Control word. Stack organization. Instruction Formats-Addressing Modes 3.2 Data transfer and Manipulation: Data Transfer Instructions Data Manipulation Instructions Arithmetic Instructions Logical and Bit Manipulation Instructions Shift Instructions. 3.3 Program control: Status bit conditions Conditional Branch Instructions Subroutine Call and Return Program Interrupt Types of Interrupts. 3.4 Reduced Instruction set Computer (RISC): CISC Characteristics RISC Characteristics Overlapped Register Windows-Berkeley RISC I. Unit 4. Computer arithmetic and memory organization: [10] 4.1 Addition and Subtraction: Hardware Implementation Hardware Algorithm Addition and Subtraction with Signed-2's Complement 4.2 Data Multiplication Algorithms: Booth Multiplication Algorithm Array Multiplier. 4.3 Division Algorithms: Divide overflow Hardware Algorithm Floating Point Arithmetic Operations Basic considerations-Register Configuration 4.4 Memory concept Main Memory Auxiliary Memory Associative Memory: 4.5 Memory Hardware Organisation

 Match Logic Read operation and Write operation. Cache memory Associative Mapping Direct Mapping Set-Associative Mapping Writing into Cache-Cache Initialization. Virtual Memory-Address space and Memory space4.6 Address mapping Using Pages Associative Memory page table Page Replacement-Memory Management Hardware Segmented-Page MappingUnit 5. Pipeline, vector processing and multiprocessors: [9] 5.1 Parallel Processing Pipelining-Arithmetic Pipeline-Instruction 5.2 Pipeline Examples Four Segment Instruction Pipeline Data Dependency Handling of Branch Instructions. RISC Pipeline Three Segment Instruction Delayed load-Delayed branch. 5.3 Vector Processing: Vector operations Matrix Multiplication Memory Interleaving Super computers. array processors: Attached Array Processor-SIMD Array processor. Practical: [45] 8085 Assembly Language program: 1. Multi byte Addition and Subtraction Multi byte decimal addition and subtraction 2. Adder and substractor circuit 3. Study of 8259 programmable interrupt controller - Development of interrupt service routine 4. Keyboard/display controller- Keyboard scan- blinking and rolling display 5. Parallel data transfer 6. Study of Microcomputer development system Text books: 1. Morris Mano.M., Computer System architecture, PHI, 1993. Reference books: 1. Hamacher.V.C.,Vranesic.Z.G and Zaky.S.G.,Computer Organisation, McGraw Hill, New York,III Edition,1990. 2. Hayes," Computer System Architecture",Mc Graw Hill,1998.