IEEE MULTIDISCIPLINARY ENGINEERING EDUCATION MAGAZINE, VOL. 2, NO.

2, JUNE 2007

Introductory Graph Theory for Electrical and Electronics Engineers

Emmanuel A. Gonzalez, Graduate Student Member, IEEE
The rest of the paper is as follows. Section II presents some important graph terminology. Different graph representations are discussed in Section III. Section IV discusses graph connectivity, while Section V discusses Euler and Hamiltonian paths. In Section VI, the concepts of planar graphs and maps are presented. Finally, Section VII discusses a direction on the further study of graph theory for electrical and electronics engineering. II. TERMINOLOGY A graph basically is a pictorial representation of a system using two basic elements: nodes (some call it vertices) and edges. A node or vertex is represented by a circle (either hollow or shaded), and an edge is represented by a line segment connecting two nodes. The graph shown in Fig. 1(b) is called an undirected graph because all of its edges do not indicate any direction from one node to the other. However, if the edges of a graph direct one node to another node, as shown in Fig. 2, then the graph is said to be a directed graph. A graph G can be mathematically represented by a double (V , E ) , where V is the set of all vertices, and E is the set of all edges. If the graph G (V , E ) is undirected, then each edge e in E is associated with the vertices v and w , and is written as either e = {v, w } or e = {w, v} , i.e. the edge e connects vertices v and w . However, if the graph G (V , E ) is a directed graph, then each edge e in E is associated with an ordered pair of vertices v and w , and is uniquely written as e = ( v, w ) , i.e. the edge connects vertex v to vertex w , and not the other way around. The association of an edge e to a pair of vertices, for example v and w , means that e is incident on v and w , and v and w are said to be incident on e . Vertices v and w , on the other hand, are adjacent. A graph can have infinite number of vertices and edges. However, in this lecture note, it is assumed that the number of vertices and edges are both finite and nonempty unless otherwise specified. Sometimes, graphs are constructed with each edge having a corresponding label. Such graphs are called labeled graphs because each edge is labeled by a certain value. If the value is numerical, they are called weighted graphs. For example, if an edge e has a weight of 10.0, then that edge e has a weight of 10.0. Most graphs in engineering and sciences are

Abstract In this lecture note, an introduction to graph theory is presented which can be used as a lecture material for introducing graph theory in the fields of electrical and electronics engineering. The mathematics of graph theory is presented in detail, supported by different applications ranging from representing basic electric circuits into digital computers to printed circuit board (PCB) layout problems. Index TermsEulers path, Hamiltonian cycle, Bipartite.

I. INTRODUCTION

n 1736, Swiss mathematician Leonhard Euler presented a general theory that included a solution to a problem known as the Knigsberg bridge problem, a problem that has ignited the thorough study of graph theory until now. Fig. 1(a) presents a map of a part of Knigsberg, which is already currently known as Kaliningradskaya in Russia. It contains two islands connected to each other and the river banks having a total of seven bridges. The problem is to start at any location in the map, for examplepoint A; walk over each bridge exactly once; then return to the starting location. As seen in Fig. 1(a), the bridges of Knigsberg can be modeled using a graph as shown in Fig. 1(b). The vertices of the graph represent the locations of the map, while the edges of the graph represent the seven Knigsberg bridges. Since then, researches around the world have attempted and successfully develop mathematical analyses of graphs, meanwhile, scientists and engineers were able to successfully apply these concepts in their own respective fields. One of the reasons for the recent interests in graph theory is its applicability in many diverse fields, in which electrical and electronics engineering is the main focus of this lecture note. It can be applied to different problems such as determining whether a circuit can be implemented in a printed circuit board without the use of jumpers or through-holes for doublesided ones and determining the optimum layout of CMOS circuits.

The author is with the Department of Electronics and Communications Engineering, College of Engineering, De La Salle University - Manila (gonzaleze@dlsu.edu.ph). Publisher Identification Number 1558-7908-052007_01

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(Source: Google Earth, Retrieved March 8, 2007) (a)

A

(b) Fig. 1. The Knigsberg problem representationan example of an undirected graph with four nodes/vertices and five edges. (a). Satellite view of Kaliningradskaya in Russia with five (yellow/lighter) of the seven Knigsberg bridges. The two (blue/darker) lines are the other Knigsberg bridges which are not currently available.

weighted. As an example consider an electric network as shown in Fig. 3(a) with its graph representation in Fig. 3(b). It is seen that Fig. 3(b) is a good example of a directed graph and weighted graph with its weights representing the values of current flowing through each resistor. Another way of representing the circuit is shown in Fig. 3(c). Fig. 3(c) is an example of an undirected weighted

graph with its weights representing the values of the resistances of each branch. Either way, both Fig. 3(b) and 3(c) are good representations of the electric network in Fig. 3(a). In a graph, two or more edges are called parallel edges if all of these edges are associated with the same pair of vertices v and w . If an edge, on the other hand, is incident on a single vertex, then that edge is called a loop. A vertex that is

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A

C
Fig. 4. An example of a graph with an isolated vertex (i.e. vertex C) and a loop in vertex A.

Fig. 2. An example of a directed graph with three nodes/vertices and four edges.

R1

R2

R3

I1 I4 I5 R4

I2 I6

I3

(a)

R5

R6

(a)

I1

B I4

I2

I3

(b) Fig. 5. Examples of complete graphs. (a) The complete graph

I6

K3 .

(b) The complete graph

K4 .

I5 E F
(b)

R1

R2

R3

R4 R5 E F
(c)

R6

A graph is said to be complete if it is simple and there is an edge between every pair of distinct vertices. Such graphs can be denoted by K n , where n is the number of vertices. Figs. 5(a) and (b) show examples of complete graphs. A graph G (V , E ) is called a complete bipartite if the set of all vertices V is partitioned into two parts V1 and V2 such that each vertex in V1 is adjacent to each vertex in V2 . Complete bipartites are denoted by K m ,n , where m and n are the number of vertices in each partition. Figs. 6(a) and (b) show examples of complete bipartites. One of the applications of complete bipartites can be seen in the field of computational intelligence. Examples are Artificial Neural Networks (ANNs)1 [1]-[5], and Ant Colony Optimization (ACO) [6][10] construction graphs2. Furthermore, a bipartite is a graph in which each vertex in V1 is adjacent to any vertex in V2 . III. GRAPH REPRESENTATION Graphs can actually be represented using matrices. Two of the most widely used matrices for graph representation are adjacency matrices and incidence matrices. An adjacency
1 Artificial neural networks is the study of the mathematics of the brain and its implementation using electronic circuits. For more information about ANNs, refer to [1]-[5] 2 Construction graphs for ant colony optimization metaheuristics are similar to the networks in ANN. For more information about ACO, refer to [6]-[10]

Fig. 3. An electric network composed of resistors. (a) The schematic diagram of the electric network. (b) A directed graph representation of the electric network with its edges weights corresponding to the current flowing through each branch. (c) An undirected graph representation of the electric network with its edges weights corresponding to the resistance value of each branch.

not incident on any edge is called an isolated vertex. A graph with neither parallel edges nor loops is called a simple graph, as shown in Figs. 3(b), and 3(c). Examples of graphs with parallel edges are shown in Figs. 1(b) and 2, while a graph with a loop and an isolated vertex is shown in Fig. 4.

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20mi 10mi 13mi C 10mi 10mi 15mi D E 13mi

10mi

(a)

9mi

Fig. 7. An example of a graph for the Traveling Salesman Problem (TSP). (b) Fig. 6. Examples of bipartites. (a) The bipartite K 2 , 3 . (b) The bipartite K 1, 4 .
A B

matrix is a square matrix in which each row and column is represented by a vertex. For example, consider Fig. 1(b) of the Knigsberg bridge problem. The graph in Fig. 1(b) has four vertices, V = {A, B, C , D} . This means that the square matrix must be 4 4 , i.e. each row and column is represented by each of the four vertices in V . Thus, following Fig. 1(b), the adjacency matrix representing this graph is

(a)
A B

0 2 G1 = 0 0

2 0 2 1

0 2 0 0

1 0 0

(b) Fig. 8. Two directed graph. (a) A directed graph that is both strongly and weakly connected. (b) A directed graph that is weakly connected.

Fig. 2 can also be represented by an adjacency matrix. Since the graph contains three vertices, the adjacency matrix generated by a 3 3 square matrix and is represented by

0 1 2 G2 = 1 0 1 . 2 1 0
Figs. 3(b) and (c) can be represented by the matrix

It is also seen that adjacency matrices are symmetric. Furthermore, if the graph has no loop, then the diagonal of the adjacency matrix contains zeros. Graphs with parallel edges, on the other hand, have entries that are greater than one. Another common way to represent a graph is to use an incidence matrix. Suppose that the graph G (V , E ) has m vertices v1 , v 2 , ", vm and n edges e1, e 2 , ", en . Then the incidence matrix with respect to the ordering v1 , v 2 , ", vm and equal to 1 when edge e j is incident with vertex vi , and is 0

0 1 0 G3 = 0 0 0

1 0 1 0 0 1

0 1 0 1 0 1

0 0 1 0 0 0

0 0 0 0 0 1

1 1 0 1 0

e1, e 2 , ", en is the m n matrix M = [mij ] , where m ij is

otherwise. This means that each row represents a vertex, while each column represents an edge. To illustrate this concept, consider again Fig. 3(c), which contains 6 vertices and 6 edges V = {A, B, C , D, E , F }

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the start point and end point are the same, the path is called a closed path.
e2 e3 D

e1 B e4

e5

An undirected graph is called connected if there is always a path between every pair of distinct vertices in the graph. Thus, there is a simple path between every pair of distinct vertices of a connected undirected graph. Such example of a connected graph is shown in Fig. 7. Meanwhile, the graph shown in Fig. 4 is not connected because there is no path that will connect point C to any other points in the graph. Directed graphs can also be classified as either strongly or weakly connected. A strongly connected graph is a directed graph in which there is a path from vertices u and v and from v to u . On the other hand, a weakly connected graph is a directed graph in which there is path between every two vertices in the underlying undirected graph. Fig. 8(a) is an example of a directed graph that is both strongly and weakly connected. Fig. 8(b), on the other hand is an example of a directed graph that is weakly connected. Suppose that G1 (V1 , E1 ) and G 2 (V2 , E 2 ) are graphs and the function f : V1 V2 is a one-to-one correspondence between set of vertices such that {u, v} are adjacent vertices of G1 { f ( u ) , f ( v )} are adjacent vertices of G 2 . This means that graphs G1 and G 2 have the same graphical properties, such as degree for example, this they are isomorphic. The isomorphism between two graphs G1 and G 2 means that their graphical properties are the same even if they seem to look different. If given any graph G (V , E ) such that a new graph G (V , E ) is obtained by dividing an edge of G (V , E ) with additional vertices, then it is said that G (V , E ) and G (V , E ) are homeomorphic. V. EULER AND HAMILTONIAN PATHS Euler and Hamiltonian paths are two of the most important concepts of graph theory that are applied to the fields of both engineering and sciences. An Euler path in a graph G (V , E ) , which is named after Leonhard Euler (1707-1783), is a path containing every edge of G (V , E ) . Furthermore, an Euler circuit in a graph G (V , E ) is a closed path containing every edge of G (V , E ) . In Fig. 9, an Eulers path is can be determined as
pE = ( D, e3 , B, e 2 , A, e1 , B, e 4 , C , e5 , B ) .

Fig. 9. The Knigsberg bridge problem graph representation with labels on all of its edges.

E = {R1 , R2 , R3 , R4 , R5 , R6 } .

The

incidence

matrix

representing Fig. 3(c) is

1 1 0 M= 0 0 0

0 1 1 0 0 0

0 0 1 1 0 0

0 1 0 0 0 1

0 0 0 0 1 1

1 . 0 0 1

If two columns in an incidence matrix are equal, then the edges representing those columns are parallel edges. If a column contains only one nonzero element, then the edge corresponding to that column is a loop. If a column contains only one element with a value of n , then the edge corresponding to that column is an n -edge multi-loop. IV. CONNECTIVITY OF GRAPHS, ISOMORPHISM, AND HOMEOMORPHISM Consider for example a Traveling Salesman Problem (TSP) as shown in Fig. 7. In this problem, the objective is to start at a point within the graph, for examplepoint A, travel to all other vertices and then get back to point A. It is seen that there are many ways for traveling the entire network of points. For example, one might choose the path
p1 = ( A, B, F , E , C , D, A )

having a total length of 72 miles. Another would opt to choose the path
p 2 = ( A, B, F , C , E , D, A )

having a total length of 81 miles. Either way, both paths can be used in the TSP. Informally, a path is a sequence edges that begins at a vertex and travel along the edges of the graph until a vertex of destination is reached. In this example, since

Since pE is a path that contains every edge of G (V , E ) , it is evident that pE is an Euler path. However, no Euler circuit can be found in Fig. 9 since having a closed path would result to having the edge e3 passed more than once. Having a graph G (V , E ) with a large number of vertices and edges will be difficult if an Euler circuit is to be

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TABLE I FOUR-BIT GRAY CODE. Decimal Equivalent 0 1 2 3 4 5 6 7 Gray Code 0000 0001 0011 0010 0110 0111 0101 0100 Decimal Equivalent 8 9 10 11 12 13 14 15 Gray Code 1100 1101 1111 1110 1010 1011 1001 1000

e1 B e4

e2 e3 D

e5

C
Fig. 9. The Knigsberg bridge problem graph representation with labels on all of its edges.

100 110 111

101 0110 001

0100 0111

0101 1110 0001

1100 1111

1101

000

0000

1000

1001

010 (a)

011

0010

0011 (b)

1010

1011

Fig. 10. Graphical representations of Gray codes. (a) Q 3 . (b) Q 4 .

100 110 111

101 0110 001

0100 0111

0101 1110 0001

1100 1111

1101

000

0000

1000

1001

010 (a)

011

0010

0011 (b)

1010

1011

Fig. 11. Euler circuits. (a) Q 3 . (b) Q 4 .

determined. However, there is a theorem that a connected graph has an Euler circuit if and only if each of its vertices has even degree. The degree of a vertex is the number of edges incident to it. Looking again at Fig. 9, it is seen that the theorem is not satisfied because the degrees of vertices B and D are both odd, having 5 and 2 incident edges, respectively. A graph has an Euler path if and only if it has exactly two vertices of odd degree. Fig. 9 is an example of graph that has

two vertices both having odd degrees, therefore, an Euler path exists.

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r3

B
r2

r1

(a)
Fig. 12. Some examples of planar graphs.

(b)

(c)

A Hamilton path in a graph G (V , E ) , which is named after William Rowan Hamilton (1805-1865) is a path containing every vertex of G (V , E ) . Furthermore, a Hamilton circuit in a graph G (V , E ) is a closed path containing every vertex of G (V , E ) . Fig. 7 shows an example of a graph that has both a Hamilton path and a Hamilton circuit. An example of a Hamilton path for Fig. 7 is the sequence
pH = ( A, B, F , C , E , D ) ,

Another practical application of paths is the optimum fullcustom layout design of a CMOS digital integrated circuit. The idea is to construct a graph representation of the CMOS digital circuit, with the vertices representing the drains and sources of the PMOS and NMOS transistors, and edges representing the transistors themselves. After determining the graph representation of the circuit, all Euler paths are determined and then are used in determining the optimum layout of the circuit. The readers are referred to [11]-[15] for more information about the topic. VI. PLANAR GRAPHS A graph is said to be planar if it can be drawn in a plane so that its edges do not cross. Fig. 12 shows good examples of planar graphs. Fig. 12(a) is obviously a planar graph since its edges do not cross. Fig. 12(b) is also a planar graph since it is just a reconstruction of Fig. 12(a), thus they are isomorphic. Fig. 12(c) is another example of a planar graph. A planar graph is also called a map since the graph is said to divide the plane in different regions. In each region of the map, the borders are actually the edges of the planar graph. Figs. 12(a) and (b), for example, have 4 regions, while Fig. 12(c) have 3 regions. The degree of a region r , written as deg ( r ) , is the is the number of edges cycling bordering that region. The degrees of the regions of Fig 12(c) are: deg ( r1 ) = 5 , deg ( r2 ) = 6 , and deg ( r3 ) = 5 . The degree of

while an example of a Hamilton circuit for Fig. 7 is the sequence

cH = ( A, B, F , C , E , D, A ) .

If a simple graph G (V , E ) with n 3 vertices such that the degree of every vertex in G (V , E ) is at least n / 2 , then G (V , E ) has a Hamilton circuit. This theorem is currently known as the Diracs theorem. Furthermore, if G (V , E ) is a simple graph with n 3 vertices such that the sum of the degrees of two nonadjacent vertices is greater than or equal to 3, then G (V , E ) has a Hamilton circuit. This theorem is currently known as Ores theorem. Paths are practically useful in determining an Euler circuit from a Gray code graph representation. The Gray code, named after Frank Gray, is one of the most useful binary codes in digital systems. One advantage of using Gray code over other binary codes is that only one bit in the code group changes when going from one number to the next. The effect of this method is having minimal errors in transmitting digital signals. Table 1 presents the four-bit Gray code. Gray codes are commonly used in analog-to-digital signal conversion applications. Gray codes can be represented by a n -cube Qn where n is the number of bits. A three-bit Gray code can be represented by a 3-cube Q3 as shown in Fig. 10(a), while a four-bit Gray code can be represented by a 4-cube (hypercube) Q 4 as shown in Fig. 10(b). Figs. 11(a) and (b) each shows an Euler circuit for Q3 and Q 4 , respectively.

r2 is 6 because the edge {E , F } is repeated twice. Considering again Fig. 12(c), it is seen that the sum of the degrees of the regions is 16 and the number of edges of the map is 8. There is actually a theorem stating that the sum of the degrees of the regions of a map is twice the number of edges. Furthermore, the number of vertices and regions of a map is equal to two plus the number of edges. This theorem is actually called the Eulers Formula and is mathematically stated as
V +R =E +2

where V is the number of vertices, R is the number of regions, and E is the number of edges. Another theorem states that E 3V 6 as long as V 3 .

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R1

V+

R2

R3

V
R4
Fig. 13. An example of a simple electric circuit.

R5

R6

V+

R1

R2

V+ R3 C R6

R1

R2 R5 R6 R3

R4

R4

R5

(a)

(b)

Fig. 14. Graph representations of the simple electric circuit in Fig. 11. (a) A straight graphical representation of Fig. 11. (b) A reduced graphical representation of Fig. 12(a).

One typical application of planar graphs is in the design of printed circuit board (PCB) layouts for electric/electronic circuits. Consider, for example, a simple electric circuit shown in Fig. 13 with corresponding graphs shown in Figs. 14(a) and (b). Fig. 14(a) is a straight graphical model of the electric circuit in Fig. 13, with the vertices representing the nodes of the electric circuit, and the edges representing the resistors and wires connected the elements. However, due to the redundancy in the use of nodes, some nodes can be merged to form a single node, thus, minimizing the graph as shown in Fig. 14(b). Since it is obvious that Fig. 14(b) is planar, the PCB electric circuit layout can be designed in such a way that no jumper wires are to be used. The use of the Eulers formula and the other theorems would verify the claim, having V = 5 , E = 6 , and R = 3 , with V + R = E + 2 and E 3 V 6, V 3 , being both satisfied. VII. FURTHER STUDIES ON GRAPH THEORY Graph theory is a very interesting topic in discrete mathematics due to its numerous applications especially in the fields of electrical and electronics engineering. This paper presents an introductory lecture on graph theory emphasizing on some of its applications such as electric circuit digital computer representation using matrices, full-custom digital CMOS circuit design, and PCB layouting problems. More indepth topics on graph theory including the following, but are not limited to: nonplanar graphs and Kuratowskis theorem, graph coloring, four-color theorem, trees, and shortest path algorithms. Most of these topics can be found at [16] and [17].

ACKNOWLEDGMENT The authors would like give thanks to the anonymous reviewers for their helpful and insightful comments and suggestions about the contents of this lecture note. REFERENCES
[1] [2] [3] [4] [5] [6] [7] [8] B. Kosko, Neural Networks and Fuzzy Systems: A Dynamical Systems Approach to Machine Intelligence, Englewood Cliffs, NJ: Prentice-Hall, 1992. Y. Yao and W. J. Freeman, Model of biological pattern recognition with spatially chaotic dynamics, Neural Networks, vol. 2, no. 2, 1990, pp. 153-170. J. J. Hopfield, Neural networks and physical systems with emergent collective computational abilities, Proceedings of the National Academy of Science, vol. 79, 1982, pp. 2554-2558. J. J. Hopfield and D. W. Tank, Neural computation of decisions in optimization problems, Biological Cybernetics, vol. 52, 1985, pp. 141152. S. S. Haykin, Neural Networks: A Comprehensive Foundation, 2nd ed., Upper Saddle River, NJ: Prentice-Hall, 1999. M. Dorigo, V. Maniezzo, and A. Colorni, Ant system: optimization by a colony of cooperating agents, IEEE Trans. on Syst., Man, and Cybern.Part B: Cybernetics, vol. 26, no. 1, Feb. 1996, pp. 29-41. M. Dorigo and T. Sttzle, Ant Colony Optimization, London: MIT Press 2004. E. A. Gonzalez and F. S. Caluyo, Nearly optimal PID tuning for second-order systems using sequential ant colony optimization, Proc. Osaka Univ. De La Salle Univ. Academic Research Workhop, vol. 7, Aug. 8-9, 2006, pp. 175-179. E. A. Gonzalez and F. S. Caluyo, Optimal retuning of quarter-wave Ziegler-Nichols PID controllers using sequential ant colony optimization, 7th National Electrical, Electronics, Computer, and Communications Engineering Conference (EECCECON), EEE

[9]

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Department, University of the Philippines, Diliman Quezon City, Philippines, Nov. 30-Dec. 2. [10] E. A. Gonzalez, Ant Colony-Based Solutions for Sub-Optimal Control Systems, M.Sc. Thesis, Graduate School of Engineering, De La Salle University Manila, Philippines, 2006. [11] T. Uehara and W. M. vanCleemput, Optimal layout of CMOS functional arrays, IEEE Trans. Computers, vol. C-30, no. 5, May 1981, pp. 305-312.. [12] K. Roy, Optimum gate ordering of CMOS logic gates using Euler path approach: some insights and explanations, J. Computing and Information Technology, CIT-15, 2007, pp. 85-92.

[13] N. Deo, Graph Theory with Applications in Engineering and Computer Science, India: Prentice-Hall, 2001. [14] S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits Analysis and Design, McGraw-Hill, 1999. [15] R. Nair, A. Bruss, and J. Reiff, Linear time algorithms for optimal CMOS layout, Proc. Int. Workshop Parallel Comp. VLSI, Amalfi, Italy, May 1984, pp. 327-338. [16] S. Lipschutz, Schaums Outline Series, Theory and Problems of Discrete Mathematics, McGraw-Hill, Inc., 1976. [17] R. Johnsonbaugh, Discrete Mathematics, 4th ed., Upper Saddle River, NJ: Prentice-Hall, 1997.

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