Periodic Waveform Generation with RIO Enabled Hardware and LabVIEW FPGA

Publish Date: Jan 14, 2010 | 7 Ratings | 3.71 out of 5

Overview
One major benefit of Reconfigurable I/O (RIO) technology is the ability to create custom hardware to generate analog waveforms for specific applications. This tutorial describes one common method for developing a customized periodic waveform generator using RIO enabled hardware (for this tutorial we are using CompactRIO) and the LabVIEW FPGA Module. For additional information about waveform generation with the LabVIEW FPGA Module and CompactRIO return to the main tutorial, " Waveform Generation with CompactRIO ."

Table of Contents
1. Periodic Waveform Description 2. Periodic Waveform Applications with CompactRIO 3. Periodic Waveform Generation Using Sine Generator Express VI 4. Periodic Waveform Generation Using FPGA Memory 5. Conclusion 6. Periodic Waveform LabVIEW FPGA Examples

1. Periodic Waveform Description

A periodic waveform is a waveform that repeats itself at regular intervals. The unit of regularity in a periodic waveform is called its cycle. The waveform shown below is a periodic sine wave that has a cycle of 50 samples. Periodic waveforms do not have to be sinusoidal and can be arbitrarily complex within the defined cycle.

Figure 1. Periodic Waveform

2. Periodic Waveform Applications with CompactRIO

Periodic waveforms of varying shapes, amplitudes, and frequencies are used for simulation and control of electronic devices across a broad range of industries. The most common types of periodic waveforms are sine, square, triangle, and sawtooth, used in a variety of applications for simulation and control of electronic devices . As an application example, sawtooth waveforms are often used to sweep the frequency of a second signal. By using a sawtooth waveform to drive a voltage-controlled oscillator, engineers can continuously sweep through specific frequency ranges. As another application example, square waves are used in acoustical testing. Because square waves contain only odd integer harmonics, an acoustic engineer is able to compare the actual sound pattern of an audio system they are testing with the familiar square wave pattern. In addition to sine, square, triangle, and sawtooth cycles, periodic waveforms can also contain complex waveform cycles that allow engineers to represent periodic noise or specific sound patterns. CompactRIO gives engineers and scientists a customizable, rugged, and portable solution for generating periodic waveforms. The LabVIEW FPGA Module combined with CompactRIO hardware, provides maximum hardware flexibility for engineers. As an example, for periodic waveform generation developers are able to customize their hardware so they have the ability to continuously change the update rate, gain, and waveform type as the program runs. Also, developers can customize their hardware triggering to suit the needs of their specific application. In addition, using the LabVIEW FPGA Module developers can easily define the timing and synchronization of FPGA functions on the same CompactRIO hardware without any knowledge of hardware design or low-level EDA tools. This is beneficial if an application requires the tight synchronization of waveform generation with other FPGA functionality such as digital I/O and analog input. We are able to generate periodic waveforms with CompactRIO hardware and the LabVIEW FPGA Module using several different methods. The first method involves the use of the LabVIEW FPGA Sine Generator Express VI. By using this Express VI we can quickly develop an FPGA program, download it to the target hardware, and have a fully functional sinusoidal generator with frequency and phase offset controls. The second method uses advanced functionality of the LabVIEW FPGA Module to load arbitrarily complex cycles of a periodic waveform to the FPGA memory. This tutorial outlines these two methods of periodic waveform generation in detail.

3. Periodic Waveform Generation Using Sine Generator Express VI

First we will develop a simple sinusoidal waveform generator by using the LabVIEW FPGA Sine Generator Express VI. The advantage of using this Express VI is it allows us to quickly define our FPGA VI because of its built-in functionality. The Sine Generator Express VI performs all the low-level FPGA programming, such as memory reads and writes, so it is transparent to the programmer. This saves valuable development time and allows us to get our custom hardware up and running faster. This section describes how to create a sinusoidal waveform generator and also discusses the use of good programming practices to create scalable, maintainable, and robust FPGA code. Refer to the section, Periodic Waveform LabVIEW FPGA Examples, to download the example program.

Defining Hardware with the LabVIEW FPGA Module The first step in developing a sinusoidal waveform generator is to program and configure the hardware by using the LabVIEW FPGA Module. The requirements of the hardware are to generate samples of a sinusoidal waveform and use an analog output channel to output the waveform. To accomplish this we will use the LabVIEW FPGA Sine Generator Express VI in combination with the LabVIEW FPGA Analog Output function. Figure 2 below, from our LabVIEW FPGA VI, Sine_Generation(fpga), shows the connections for the Express VI and the Analog Output function. We can specify the analog output channel by using the Configure Analog Output dialog box associated with the Analog Output function. In our case we are outputting the waveform to analog output channel 0 of the cRIO-9263 module. Upon every iteration of this While Loop it outputs one data point to the analog output channel listed in the Analog Output function.

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Figure 2: FGPA VI: Sine_Generation(fpga) The Configure Sine Generator dialog box, shown in Figure 3, allows us to quickly set-up our sine generator. This dialog box is automatically displayed once the Sine Generator Express VI is placed on the block diagram. Through this dialog box we are able to adjust a variety of sine wave parameters including frequency, amplitude, phase offset, look-up table size (number of samples in each cycle of waveform), and amplitude resolution. Additionally, we can externally have access to the phase increment and phase offset parameters by selecting show increment terminal and show offset terminal. These terminals allow us to continually adjust the frequency and phase offset of the waveform as it is being generated. By using the following formulas we can take inputs for frequency and phase offset(degrees) and calculate corresponding values for phase increment and phase offset.

Figure 3. Sine Generator Configuration Dialog Box Through the LabVIEW FPGA VI, Sine_Generation(fpga), described above, we are able to quickly configure our hardware by using the LabVIEW FPGA Sine Generator Express VI. The hardware is now able to generate individual samples of a sine wave, generate the samples on an analog output channel, and allow the user to continuously adjust the frequency and phase offset of the signal. The cRIO-9263 Analog Voltage Output module has a minimum update period of 3 microseconds so by using this module we are able to generate a signal at a rate of 333,333 updates/sec.

NOTE: Voltage Output with CompactRIO Analog Output Modules The LabVIEW FPGA Module utilizes integer math for all mathematical operations; therefore, analog output operations with CompactRIO must utilize the binary code representation of the desired output voltage. The binary code representation of the desired voltage is determined by dividing the voltage by the code width of the module. The code width (or step size) is defined as the smallest change in voltage that the system can output. Code width is calculated according to the following equation:

For instance, the cRIO-9263 analog output module is a 16-bit analog output module with a range of -10V to +10V. Therefore the code width of the module is .305176mV/step (20V / 2^16 steps). Therefore, to output 5.0 volts, you would need to divide 5.0 V by .305176mV. This division yields a binary value of 16384. National Instruments has included a VI for each CompactRIO analog output module that does this conversion. This VI is named Convert to Binary (cRIO-XXXX), where XXXX is the model number of the module. It is included in the cRIO-XXXX Support Files LLB located in the \examples\FGPA\CompactRIO\cRIO-XXXX\ directory. This VI converts desired voltage values into the binary code representation of that voltage through the following equation:

Configuring the Host Interface

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The second step when developing a LabVIEW FPGA application is to create a host interface VI to communicate with the VI downloaded to the RIO hardware target. In the LabVIEW Real-Time Module (or LabVIEW for Windows), there is a small set of functions for accessing the FPGA: Open FPGA Reference, Read/Write Control, Invoke Method, and Close FPGA Reference. These functions provide all of the necessary control over the FPGA, such as downloading, reading or writing data, and starting or stopping the VI. Integrating an FPGA VI into an application using these functions alone, however, can make your application hard to read, hard to scale, and hard to maintain. By using these low-level functions as building blocks, however, you can create a set of subVIs which can function as an Application Programming Interface (API) for use in your host VI. There are several benefits for creating an API for your LabVIEW host VI. One major benefit that an API provides is abstraction, which involves grouping low-level code into logical functions or data stores. Creating the API greatly increases the usability of your FPGA VI by encapsulating the low-level functionality and increasing modularity of the code. Once the modules (subVIs) are created, you can simply place them into any LabVIEW Real-Time or LabVIEW for Windows application as functional nodes. In our example, shown in Figure 4, we have created four modules as subVIs: Open, Start, Set Controls, and Clear.

Figure 4. Top Level VI -> Sine_Generation(Host) This modular API allows us to easily modify our sinusoidal waveform VI and also create new host VIs that need the same functional building blocks. Let's investigate each of the four subVIs that are contained in our host VI, Sine_Generation(Host). Opening and Closing the FPGA Hardware Execution Reference Figure 5 shows the Open and Clear VIs of the API. FPGA_Sine_Open_Ref simply opens a Hardware Execution Reference, which is obtained from the Open FPGA Reference function. This Hardware Execution Reference is then used throughout the host VI to specify the hardware target and corresponding FPGA VI. FPGA_Sine_Clear is called at the end of the host VI and stops the FPGA VI that is currently running on the target hardware and closes the Hardware Execution Reference.

Figure 5. Opening and Closing the FPGA Reference Initializing and Generating the Sinusoidal Waveform FPGA_Sine_Start, displayed in Figure 6, initializes controls on the LabVIEW FPGA VI, Sine_Generation(fpga), and then runs the FPGA VI. By using the Read/Write Control function we are able to set the initial values of the two inputs on our FPGA VI, phase increment and phase offset. The subVIs PhaseOffset and PhaseIncrement implement the equations shown below by using Formula Nodes. This conversion allows us to input Frequency in hertz and Phase Offset in degrees.

Once these controls are set, the Invoke Method function specifies the Run action and the code runs continuously in the While Loop of the FPGA VI.

Figure 6. Starting the FPGA VI on the Target Hardware

Continuously Updating Waveform Parameters Now that the sinusoidal waveform is being generated, we can call FPGA_Sine_Set_Cntls, displayed in Figure 7, to continuously adjust the Frequency(Hz) and Phase Offset(deg) controls. To accomplish this, we first we use the subVIs PhaseOffset and PhaseIncrement to convert the Frequency(Hz) and Phase Offset(deg) user values to phase increment and phase offset, respectively. Second, we use the Read/Write Control function to write these resulting values to the FPGA VI being run on the target hardware. By placing FPGA_Sine_Set_Cntls in a While Loop we are able to continuously poll these controls and write them to the FPGA VI as they change values. Additionally, a Stop button is also polled in the same fashion, giving the user the ability to stop the sinusoidal waveform generation when they desire.

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Figure 7. Updating the Controls on the FPGA VI

4. Periodic Waveform Generation Using FPGA Memory

The previous section described how to use the LabVIEW FPGA Sine Generator Express VI for a fast way to create a sinusoidal function generator. This Express VI is great for applications that only need a sinusoidal waveform output, but it often does not have the full functionality that the developer needs for periodic waveform generation. The Sine Generator Express VI only lets the user change the frequency and offset period continuously as the waveform is being generated. In addition, the Express VI does not allow for generation of periodic waveforms with complex cycles. By using the advanced LabVIEW FPGA programming functions, Memory Read and Memory Write, we are able to take advantage of the onboard FPGA memory and create periodic waveforms with complex cycles. These functions allow the developer to load an arbitrarily complex waveform cycle with up to 8192 16-bit samples and continuously generate that cycle as a periodic waveform. This section outlines the creation of a periodic waveform generator that uses the FPGA onboard memory. Additionally, it discusses the use of good programming practices to create scalable, maintainable, and robust FPGA code. Refer to the last section, Periodic Waveform LabVIEW FPGA Examples, to download the example program. Configuring the Hardware with the LabVIEW FPGA Module As described in the previous section, Periodic Waveform Generation Using Sine Generator Express VI, the first step in developing a periodic waveform generator is to program and configure the hardware by using the LabVIEW FPGA Module. The requirements of the hardware are as follows: - Write data to the FPGA memory (one cycle of the waveform) - Read data from the FPGA memory continuously - Output data to an analog output channel* - Allow the user to adjust the waveform frequency and amplitude while continuously outputting signal * In our example we are using the cRIO-9263 16-bit Analog Voltage Output module Since the FPGA onboard the CompactRIO hardware can only have one VI loaded at a time, we need to integrate all the above functionality into one LabVIEW FPGA VI. To accomplish this we will use a case structure that has two cases. One case writes data to the FPGA memory and the other case reads data from the FPGA memory and outputs the waveform through the cRIO-9263 module. Figure 8 below, from the LabVIEW FPGA VI Read_Write_Memory(fpga), shows the False case of the case structure. The Memory Write VI within this case allows us to write one data value at a specified address each time Read_Write_Memory(fpga) is called. To write multiple waveform data points into the FPGA memory we must call Read_Write_Memory(fpga) multiple times. By using the FPGA memory we can avoid the use of arrays in the FPGA code which can consume a large number of limited FPGA gates. By avoiding arrays, and having additional FPGA gates available, we have the ability to write a more complex FPGA program, resulting in increased hardware functionality.

Figure 8. False Case of FPGA VI: Writing Waveform Elements Into FPGA Memory Figure 9 shows the True case of the Read_Write_Memory(fpga) VI. The true case reads each data element of the stored waveform and outputs the corresponding voltage to an analog output channel at a specified update rate. Within this case there are three additional LabVIEW structures, a While Loop, For Loop, and Sequence Structure. Let's first take a look at the Sequence Structure which has two sequences. The first sequence has a Loop Timer that can be configured in microseconds, milliseconds, or tick counts. We have specified microseconds in our example, giving us exact hardware timing to control the update rate at which each data point of the waveform is output. The Update Period control feeding the Loop Timer allows us to change the microsecond interval between each data point as the waveform is being generated. The cRIO-9263 has a minimum update period of 3 microseconds when outputting data to one analog output channel. This corresponds to a maximum update rate of 333,333 updates/sec. The second sequence of the Sequence structure has a Memory Read VI followed by a gain multiplication and an Analog Output function. The Memory Read VI has an input called Address and every time the VI is called it reads one data value in the FPGA memory at the specified address. The data is then multiplied by the integer control Gain, and the resulting value is passed to the Analog Output function. By using the Configure Analog Output dialog box associated with the Analog Output function, an analog output channel can be specified. In our case we are outputting the waveform to analog output channel 0 of the cRIO-9263 module. Every time this Sequence structure executes it outputs one data point to the analog output channel list in the Analog Output function. The next structure is a For Loop that repeatedly calls the Sequence structure and outputs every data element in the waveform. The For Loop iterates a fixed number of times according to the control # Waveform Elements. The iteration terminal of the For Loop tells the Memory Read VI what address to read on the current loop iteration. For example, if there are 100 elements stored in the FPGA memory then the # Waveform Elements control would be set to 100 and the iteration terminal would start at the integer 0. The For Loop would run for 100 iterations, reading FPGA memory addresses 0-99 and output the data values stored at each address space. Additionally, each time the For Loop iterates it reads the two controls within the Sequence structure: Update Period and Gain. This allows the user to change the values of these controls and adjust the waveform as it is being continuously generated. The final structure in the True case is the While Loop. This allows the waveform generation to continuously repeat cycles until the Stop button is pressed.

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Figure 9. True Case of FPGA VI: Reading Waveform Elements and Outputting Through the LabVIEW FPGA VI, Read_Write_Memory(fpga), described above we are successfully able to fulfill all our hardware requirements and configure our FPGA. The program is able to write data to the FPGA memory, read data from the FPGA memory, output data to an analog output channel, and allow the user to continuously adjust the frequency and amplitude of the signal. NOTE: Voltage Output with CompactRIO Analog Output Modules The LabVIEW FPGA Module utilizes integer math for all mathematical operations; therefore, analog output operations with CompactRIO must utilize the binary code representation of the desired output voltage. The binary code representation of the desired voltage is determined by dividing the voltage by the code width of the module. The code width (or step size) is defined as the smallest change in voltage that the system can output. Code width is calculated according to the following equation:

For instance, the cRIO-9263 analog output module is a 16-bit analog output module with a range of -10V to +10V. Therefore the code width of the module is .305176mV/step (20V / 2^16 steps). Therefore, to output 5.0 volts, you would need to divide 5.0 V by .305176mV. This division yields a binary value of 16384. National Instruments has included a VI for each CompactRIO analog output module that does this conversion. This VI is named Convert to Binary (cRIO-XXXX), where XXXX is the model number of the module. It is included in the cRIO-XXXX Support Files LLB located in the \examples\FGPA\CompactRIO\cRIO-XXXX\ directory. This VI converts desired voltage values into the binary code representation of that voltage through the following equation:

Configuring the Host Interface After completing our FPGA VI and configuring the hardware, we must create a host interface VI to communicate with the FPGA VI as we did when using the Express VI. In our example, shown in Figure 10, we have created five modules as subVIs: Open, Load, Start, Set Controls, and Clear.

Figure 10. Top-Level VI -> Periodic_Output_Memory(Host) This modular API allows us to easily modify our periodic waveform VI and also create new host VIs that need the same functional building blocks. Let's investigate each of the five subVIs that are contained in our host VI, Periodic_Output_Memory(Host). Opening and Closing the FPGA Hardware Execution Reference Just as with the our sinusoidal waveform generator example, we have Open and Clear VIs. FPGA_Periodic_Open_Ref simply opens a Hardware Execution Reference, which is obtained from the Open FPGA Reference function and FPGA_Periodic_Clear is used to stop the FPGA VI currently running on the target hardware and close the Hardware Execution Reference.

Figure 11. Opening and Closing the FPGA Reference Loading the Periodic Waveform Cycle to FPGA Memory FPGA_Periodic_Load, displayed in Figure 12, allows us to load a waveform cycle into FPGA memory. Before going into the details and functionality of this VI we should first discuss different methods to create a waveform cycle. The Waveform Input control that sends the waveform cycle into FPGA_Periodic_Load is a dynamic data type that is converted to a 1-D array of doubles. This gives developers the flexibility to generate and read a waveform from a variety of different formats. In our example we generate one cycle of a waveform by using the Basic Function Generator VI. This VI allows us to generate a sine, square, triangle, or sawtooth wave and also has inputs for DC offset, frequency, amplitude, phase, and square wave duty cycle. If the developer has a more complex waveform cycle that they'd like to generate then they have several options. First, they can read a waveform from a file by using the Read LabVIEW Measurement File Express VI which allows them to read comma or tab-delimited spreadsheet files. Second, if they have a binary or ASCII file they'd like to read a waveform cycle from, they can use the LabVIEW File I/O functions. Finally, if the developer does not want to read a waveform from a file they can generate a waveform array in LabVIEW. Once a waveform cycle is created or read from a file, it then needs to be loaded to the FPGA memory. Remember from our LabVIEW FPGA VI, Read_Write_Memory(fpga), we have to continuously call the false case to write multiple data values into memory. To do this we use a For Loop that calls a Read/Write Control function and Invoke Method on each iteration. The

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Read/Write Control function allows us to update the two controls, Address and Data, on the FPGA VI. After updating these controls, we use the Invoke Method function and specify the action as Run to execute the FPGA VI on our target hardware. Each time the For Loop iterates it writes a data value from our Waveform Input array to the FPGA memory at the address specified by the iteration terminal. By using the LabVIEW Array Size function we are able to set the loop count terminal on the For Loop. The subVI Convert to Binary (cRIO-9263) takes an input voltage (+-10V) and converts it to the binary code (-32768 to +32767) that is accepted by the cRIO-9263 Analog Output Module.

Figure 12. Loading the Waveform Cycle to FPGA Memory Initializing and Generating the Periodic Waveform FPGA_Periodic_Start, show in Figure 13, initializes controls on the LabVIEW FPGA VI, Read_Write_Memory(fpga), and then runs the FPGA VI in the true case. By using the Read/Write Control function the we are able to set the initial values of the two controls, Update Period and # Waveform Elements. Once these controls are set, we specify the Run action with the Invoke Method function and the code runs continuously in the true case of the FPGA VI. Remember that this true case continuously reads data from the FPGA memory and outputs the corresponding voltages on a specified analog output channel of the cRIO-9263 Analog Output Module.

Figure 13. Starting the FPGA VI on the Target Hardware

Continuously Updating Waveform Parameters Once the periodic waveform is being generated, we can then call FPGA_Periodic_Set_Cntls, displayed in Figure 14, to continuously adjust the frequency and amplitude. This is accomplished by using the Read/Write Control function to write the values of the two controls, Update Period and Gain, to the FPGA VI being run on the target hardware. By placing this VI in a While Loop we are able to continuously poll these controls and write them to the FPGA VI as they change values. Additionally, a Stop button is also polled in the same fashion, giving the user the ability to stop the waveform generation when they desire.

Figure 14. Updating the Controls on the FPGA VI

5. Conclusion
CompactRIO gives engineers and scientists a customizable, rugged, and portable solution for periodic waveform generation. The LabVIEW FPGA Module, and CompactRIO hardware provides maximum flexibility for the developer. In this tutorial we have outlined two methods for creating periodic waveform generators. By using the LabVIEW FPGA Sine Generator Express VI we are able to quickly design our FPGA VI and configure the target hardware. This Express VI performs all the low-level FPGA programming, such as memory reads and writes, so it is transparent to the programmer saving valuable development time. For more advanced periodic waveform generator functionality we use the FPGA memory. The FPGA memory can be accessed by using Memory Read and Memory Write FPGA VIs, allowing us to create complex periodic waveform cycles. The periodic waveform generators that we outlined throughout this tutorial can be downloaded below. For additional information about waveform generation with the LabVIEW FPGA Module and CompactRIO return to the main tutorial, " Waveform Generation with CompactRIO " See Also: Waveform Generation with CompactRIO

6. Periodic Waveform LabVIEW FPGA Examples

See Also: Sinusoidal Waveform Generation with LabVIEW FPGA (Sine Generator Express VI) Periodic Waveform Generation with LabVIEW FPGA (Memory Read and Write)

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Related Links: CompactRIO Product Page LabVIEW FPGA Module Product Page LabVIEW FPGA Module User Manual

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