TITLE- FUNCTIONAL DESCRIPTION OF STATIC RANDOM ACCESS MEMORY(SRAM) CONTROLLER Static Random Access Memory SRAM is used by devices,

such as the CPU, for extra fast memory or as cache.It acts as an interface between Master(s) and Slave, i.e, whenever Master wants a read or write operation to be performed, it sends a signal called REQUEST to the SRAM controller. SRAM then replies with a signal called GRANT to the Master indicating that request has been enabled. Now depending upon the signal READ/WRITE either reading of data from Slave operation or writing of data into Slave operation will be performed. SRAM has various input and output pins which have been discussed later.

R/W0 GRANT0 ACK0

(A18-A0)1

R/W1 GRANT1 ACK1

(A18-A0)2

MASTE R 2

R_DATA2 W_DATA2 REQUEST2 R/W2 GRANT2 ACK2

(A18-A0)3

MASTE R 3

R_DATA3 W_DATA3 REQUEST3 R/W3 GRANT3 ACK3

CLK RST

A R S

MASTE R 1

R_DATA1 W_DATA1 REQUEST1

T N O C

L O R M

MASTE R 0

R_DATA0 REQUEST0 W_DATA0

R E
A17 - A0 I/O15 I/O0

(A18-A0)0

CE 0 CCCE
REQUEST0

WE OE LB UB

SRAM 256Kx1 6

A17 - A0

I/O15 I/O0

CE 1 CCCE
REQUEST0

WE OE LB UB

SRAM 256Kx1 6

Pin Descriptions: Master0 (A18-A0)0 REQUEST0 GRANT0 R/W0 R_DATA0 W_DATA0 ACK0 Master1 (A18-A0)1 REQUEST1 GRANT1 R/W1 R_DATA1 W_DATA1 ACK1 Master2 (A18-A0)2 REQUEST2 GRANT2 R/W2 R_DATA2 W_DATA2 ACK2 Master3 (A18-A0)3 REQUEST3 GRANT3 R/W3 R_DATA3 W_DATA3 ACK3

Address input from Master 1 to the controller Request from Master1 to the Controller for Read or Write operation Request granted from Controller for carrying out Read or Write operation Read or Write operation Read data operation from the SRAM Write data operation into the SRAM Operation Completed Address input from Master 2 to the controller Request from Master2 to the Controller for Read or Write operation Request granted from Controller for carrying out Read or Write operation Read or Write operation Read data operation from the SRAM Write data operation into the SRAM Operation Completed

Address input from Master 3 to the controller Request from Master1 to the Controller for Read or Write operation Request granted from Controller for carrying out Read or Write operation Read or Write operation Read data operation from the SRAM Write data operation into the SRAM Operation Completed Address input from Master 4 to the controller Request from Master4 to the Controller for Read or Write operation Request granted from Controller for carrying out Read or Write operation Read or Write operation Read data operation from the SRAM Write data operation into the SRAM Operation Completed

PORT SPECIFICATION:(Slave side interface) Output Ports: Address Outputs: A17- A0 : Address of memory location where intended operation is to be performed. Chip Enable outputs : CE0 (Active Low):When CE0 is HIGH, the SRAM0 device is deselected and assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. When CE0 is LOW ,the memory locations in SRAM0 can be accessed.
CE1 (Active Low ): When CE1 is HIGH, the SRAM1 device is deselected and assumes a

standby mode at which the power dissipation can be reduced down with CMOS input levels. When CE0 is LOW ,the memory locations in SRAM0 can be accessed. Output Enable : OE (Active Low ) : When OE is HIGH , the SRAM0's and SRAM1's output will be forced to High Impedance. When OE is LOW, the outputs are enabled. Byte Select : LB (Active Low) : When LB is LOW, the lower byte input/output ports (IO7-IO0) will be enabled. When LB is HIGH, the the lower byte input/output ports will be disabled.
UB (Active Low) : When UB is LOW, the upper byte input/output ports (IO15-IO7) will be enabled. When UB is HIGH, the the upper byte input/output ports will be disabled.

Bidirectional Ports: Data Input/Outputs : IO15- IO0 : Bidirectional port for data input and output required for read /write operations.