DPSD Lab Manual

Digital Lab Manual
VIDYAA VIKAS
COLLEGE OF ENGINEERING AND TECHNOLOGY, TIRUCHENGODE.
DIGITA
L LAB
MANUAL
Department of ECE| VVCET | Page
Digital Lab Manual
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Digital Lab Manual
DIGITAL LABORATORY
Digital Lab Manual
Digital Lab Manual
EXTRACT OF ANNA UNIVERSITY SYLLABUS DIGITAL LABORATORY CSE LIST OF EXPERIMENTS
1. Verification of Boolean theorems using digital logic gates 2. Design and implementation of combinational circuits using
basic gates for arbitrary functions, code converters, etc.
3. Design and implementation of 4-bit binary adder /

subtractor using basic gates and MSI devices
4. Design and implementation of parity generator / checker

using basic gates and MSI devices
5. Design and implementation of magnitude comparator 6. Design and implementation of application using
multiplexers/Demultiplexers
7. Design and implementation of Shift registers 8. Design and implementation of Synchronous counters 9. Design and implementation of Asynchronous counters 10. Simulation of combinational circuits using Hardware
Description Language (VHDL/ Verilog HDL software required)
11.Simulation of sequential circuits using HDL (VHDL/ Verilog

HDL software required)
Digital Lab Manual
Digital Lab Manual
LAB EXPERIMENTS
Digital Lab Manual
Digital Lab Manual
INTRODUCTION TO COMPONENTS USED
A Bread-Board is used in a laboratory for constructing the different circuits and testing them. This is very useful since here; we do not have to solder the different components. Soldering, as you know can be very time consuming. Further, we can reuse the components again and again, since they are not cut and soldered. Let us learn below how we can use the breadboard for such applications. The breadboard contains a number of metal clips aligned beneath the array of holes so that when we insert the lead of a component (say, resistor) inside a hole, the clip grips the lead tightly. Observe the figure. Fig(a) shows a metal clip before a component inserted, while Fig(b) shows after the lead inserted. Fig(c) shows a clip which is beneath an array of 5-holes. All the five holes correspond to one node since all of them are connected together electrically by the metal clip. That means up to 5 wires can be connected to this single node.
Digital Lab Manual
Multimeter :
A Multimeter is indeed a multiple meter. It measure dc and ac voltages, currents and in addition resistances in some recent DMMs we can measure even frequency, capacitance, etc. Two long probes are used to connect the DMM to a circuit during a measurement. The central dial knob is rotated to choose the parameter we wish to measure. When not in use we keep the knob in OFF position.
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Digital Lab Manual
Measuring DC Voltage by using Multimeter:
Measuring Resistance Value by using Multimeter:
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Digital Lab Manual
Basic Logic Gates:
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Digital Lab Manual
Pin Details of Digital Logic Gates:
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Digital Lab Manual
Postulates and Theorems of Boolean algebra: S. No 1 . 2 . 3 . 4 . 5 . 6 . 7 . 8 . 9 . 10 . Postulate/Theorem X+0=X X + X = 1 X+X=X X+1=1 (X) = X X+Y=Y+X X + (Y + Z) = (X + Y) +Z X.(Y + Z) = X.Y + X.Z (X + Y) = XY X + XY = X X.Y = Y.X X.(Y.Z) = (X.Y).Z X + (Y.Z) = (X + Y)(X + Z) (XY) = X + Y X.(X + Y) = X X.1 = X X.X = 0 X.X = X X.0 = 0 Duality Remarks Involution Commutative Associative Distributive DeMorgans Theorem Absorption
Bit Grouping: Bit A single, bivalent unit of binary. decimal Two bits. Equivalent to a "digit." Crumb, Tydbit, or Tayste Nibble or Nybble Nickle Byte Deckle Playte Dynner Word Arithmetic Notations: Augend Minuend Multiplicand Dividend + X / -
Four bits. Five bits. Eight bits. Ten bits. Sixteen bits. Thirty-two bits. (system dependent). = Sum
Addend Subtrahend Multiplier Divisor
= Difference = Product = Quotient
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Digital Lab Manual
Verification of Logic Gates:
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Digital Lab Manual
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Digital Lab Manual
EXP. NO: 1 VERIFICATION OF BOOLEAN THEOREMS USING DIGITAL LOGIC GATES To verify the truth table of basic Boolean algebric laws by using logic gates. Components Required: S.NO 1 COMPONENT S Digital IC trainer kit RANG E 7400 7402 2 IC 7404 7408 7432 7486 3 4 Bread board Connecting wires QUANTIT Y 1 1 1 1 1 1 1 1 As required
Aim :
Theory: Demorgans Theorems First Theorem: It states that the complement of a product is equal to the sum of the complements. (AB) =A +B Second Theorem: It states that the complement of a sum is equal to the product of the complements. (A+B) =A.B Boolean Laws:
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Digital Lab Manual Boolean algebra is a mathematical system consisting of a set of two or more distinct elements, two binary operators denoted by the symbols (+) and (.) and one unary operator denoted by the symbol either bar (-) or prime (). They satisfy
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the
commutative, of
associative,
distributive
and
absorption
properties
the Boolean algebra.
Commutative Property: Boolean addition is commutative, given by A+B=B+A Boolean algebra is also commutative over multiplication, given by A.B=B.A De-Morgans Theorem: 1
De-Morgans Theorem: 2
Associative Property: The associative property of addition is given by A+ (B+C) = (A+B) +C The associative law of multiplication is given by A. (B.C) = (A.B).C Distributive Property: The Boolean addition is distributive over Boolean multiplication, given by A+BC = (A+B) (A+C) Boolean multiplication is also distributive over Boolean addition given by
A. (B+C) = A.B+A.C
Realization of circuits for Boolean expression after simplification: A binary variable can take the value of 0 or 1. A Boolean function is an expression formed with binary operator OR, AND and a unary operator NOT, parenthesis function can be 0 or 1. For example, function consider the
The
prime
implicants
are
found
by
using
the
elimination
of
complementary function. The circuit diagram for the function is drawn using AND.OR and NOT of A , A , B gates. The output for the corresponding input
1,
is calculated and the
truth table is drawn.
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Procedure:
1. Test the individual ICs with its specified verification

table for proper working.
2. Connections are made as per the circuit/logic diagram. 3.

Make sure that the ICs are enabled by giving the suitable V
cc
and ground
connections.
4. Apply the logic inputs to the appropriate terminals of the ICs. 5. Observe the logic output for the inputs applied. 6. Verify the observed logic output with the verification/truth table
given.
Commutative Law:
Truth Table: Input A 0 0 1 1 B 0 1 0 1 Output A+ B 0 1 1 1 B+ A 0 1 1 1
Associative Law:
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Truth Table: Input A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 A+ B 0 0 1 1 1 1 1 1 Output (A+B) +C 0 1 1 1 1 1 1 1 B+ C 0 1 1 1 0 1 1 1 A+ (B+C) 0 1 1 1 1 1 1 1
Distributive Law:
Truth Table: Input A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 B+ C 0 1 1 1 0 1 1 1 A. (B+C) 0 0 0 0 0 1 1 1 Output A. B 0 0 0 0 0 0 1 1 A. C 0 0 0 0 0 1 0 1 A.B+A .C 0 0 0 0 0 1 1 1
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27
Circuit of the ICs Used:
Result: Thus the verification of Boolean laws and theorems using digital logic gates were performed.
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29
EXP. NO: 2 DESIGN AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS USING BASIC GATES FOR ARBITRARY FUNCTIONS AND CODE CONVERTERS Aim : To design and implement a combinational circuit to convert gray code to
Binary and BCD to Excess-3 vice versa. Components Required: S.NO 1 COMPONENTS Digital IC Trainer kit IC RANGE 7404 74 08 74 32 7486 QUANTIT Y 1 1 2 1 1 As required 1
3 4 Theory:
Connecting wires Bread board
Binary to Gray Vice versa: The binary coded decimal (BCD) code is one of the early computer codes. Each decimal digit is independently converted to a 4 bit binary number. A binary code will have some unassigned bit combinations if the number of elements in the set is not a multiple power of 2. The 10 decimal digits form such a set. A binary code that distinguishes among 10 elements must contain at least four bits, but 6 out of the 16 possible combinations remain unassigned. Different binary codes can be obtained by arranging four bits in 10 distinct combinations. The code most commonly used for the decimal digits is the straight binary assignment. This is called binary coded decimal.
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The gray code is used in applications where the normal sequence of binary numbers may produce an error or ambiguity during the transition from one number to the next. If binary numbers are used, a change from 0111 to 1100 may produce an intermediate erroneous number 1001 if the rightmost bit takes longer to change in value than the other three bits. The gray code eliminates this problem since only one bit changes in value during any transition between two numbers. Truth Table (Binary to Gray): Binary (Input) B Gray (Output) B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
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BCD to Excess 3 Vice versa: Excess 3 code is a modified form of a BCD number. The excess 3 code can be derived from the natural BCD code by adding 3 to each coded number. For example, decimal 6 can be represented in BCD as 0110. Now adding 3 to the given number yield equivalent excess 3 code i.e., 6 + 3 = 9 ???0110 + 0011 = 1001. Thus for the entire sequence of BCD value (i.e., 0 to 9) excess 3 equivalent table should be made so that the realization of Boolean expression for the circuit implementation is feasible. In the reverse process of designing a code converter from excess 3 to BCD the same procedure is followed. Here are the general steps to be followed while going for a code converter design,
start with the specification of the circuit to be designed. Identify the inputs and outputs Derive truth table Obtain simplified Boolean equations Draw the logic diagram Check the design to verify correctness with the truth/verification table.
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Logic Diagram:
Pin Diagram:
Procedure:
1. Test the individual ICs with its specified verification table for
proper working.

Make sure that the ICs are enabled by giving the suitable V ground
cc
and
connections.
36
given.
37
38
Truth Table (Gray to Binary): Gray (Input) G Binary (Output) G 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 G 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 B 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 B 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 B 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
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Logic Diagram:
Truth Table:
Decimal Value
BCD Input A B C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1
Excess 3 output W X Y 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0
z 1 0 1 0 1 0 1 0 1 0
0 1 2 3 4 5 6 7 8 9
0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 1 1 1 0 0
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42
Realization of Boolean Expression for BCD to Excess 3 Converter:
Circuit Diagram:
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Truth Table:
Decimal Value
Excess 3 Input W X Y 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0
z 1 0 1 0 1 0 1 0 1 0
BCD Output A B C 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0
D 0 1 0 1 0 1 0 1 0 1
0 1 2 3 4 5 6 7 8 9
Realization of Boolean Expression for Excess 3 to BCD Converter:
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Circuit Diagram:
Result: Thus the combinational circuit for an arbitrary function, code converter using logic gates was designed, implemented and tested its performance with truth table.
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EXP. NO: 3 DESIGN AND IMPLEMENTATION OF 4 BIT BINARY ADDER / SUBTRACTOR USING MSI DEVICES Aim : To design and implement a four bit binary adder / subtractor using MSI
devices. Components Required: S.NO 1 2 3 Theory: Digital computers perform a variety of operations. information processing tasks. Among the functions encountered are the various arithmetic The most basic arithmetic operation is the addition of two binary digits. This simple addition consists of four possible elementary operations: 0+0=0, 0+1=1, 1+0=0 and 1+1=10. A binary adder-subtractor is a combinational circuit that performs the arithmetic operations of addition and subtraction with binary numbers. A combinational circuit that performs the addition of two bits is called half adder. One that performs the addition of three bits is a full adder. A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. Procedure: COMPONENT S IC trainer kit ICs Connecting wires RANG E 7483 7486 QUANTIT Y 1 1 1 -
1. Connect the circuit as per the circuit diagram. 2. Power supply is switched ON and a voltage of 5v is maintained. 3. Four bit binary number is given and verifies the sum result. 4. If the adder or subtractor signal is low addition is performed. 5. If the adder or subtractor signal is high subtractor result is verified.
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Verification Table:
Terminology Augend Addend Results Addition Subtraction A
Input Variables A A A 1 1
Binary inputs 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0
3
B
2
B
1
B
0
B
3
C
2 in
1
C
out
Result: Thus the 4 bit parallel adder/subtractor was implemented and tested using the MSI device IC 7483.
EXP. NO: 4 DESIGN AND IMPLEMENTATION OF PARITY GENERATOR AND CHECKER To design and implement the parity generator and checker using logic gates and verify its performance with the verification table. Components Required: S.NO 1 COMPONENT S Digital IC Trainer kit 2 IC RANGE 7486 74 74 74 04 QUANTIT Y 1 1 2 1 As required 1
Aim :
3 4 Theory:
Connecting wires Bread board
Parity generator: A parity bit is a scheme of detecting error during transmitting of binary information. A parity bit is an extra bit included with a binary message to make the number of 1s either odd or even. Parity generators are used in digital transmission system for the errorless transmission of digital data. A parity bit is added to the data before the transmission and it will be checked for the correctness at the receiver end. There are two types odd parity. In the of parity systems, even parity and even parity system if the number of 1s in the data
word is odd, a 1 will be added as a parity bit to the data to make total number of 1s even. If the number of 1s even, a 0 bit will be added. In the odd parity system if the number of 1s in the data word is odd, a 0 will be added to make the number of 1s odd. Otherwise, a 1 is added to make it odd. The circuit shown in the figure is used as a parity generator as well as a checker. ABCD is the 4-bit data word. Pi and Po are the parity input and parity output respectively.
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The working of the circuit can be concluded as follows, Work as a Parity generator: To generate an odd parity bit for ABCD, Pi must be made 0. To generate an even parity bit for ABCD, Pi must be made1. Work as a parity checker: If the parity of ABCD Pi is odd, Po will be 0. If the parity of ABCD Pi is even, Po will be 1. Circuit Diagram:
Pin Diagrams:
The message, including the parity bit, is transmitted and then checked at the receiving end for errors. An error detected if the checked parity does not correspond with the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator. The circuit that checks the parity in the receiver is called parity checker. In even parity the added parity bit will make the total number of 1s an even amount. In odd parity the added parity bit will make the total number of 1s an odd amount. Procedure:
proper working.

cc
and
connections.
given.
Truth Table for Even Parity Checker: PARITY ERROR C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CHECK PEC 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0
4 BIT DATA RECEIVED A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Circuit Diagram: B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
K.M ap Simplication for Even Parity Checker:
Result: Thus the Parity Generator was designed, implemented using logic gates and its performance was verified.
EXP. NO : 5 DESIGN AND IMPLEMENTATION OF 2 BIT MAGNITUDE COMPARATOR AIM : To design and implement a 2-bit magnitude comparator using logic gates. COMPONENT S Digital Trainer Kit ICs RAN GE 740 4 748 6 740 8 743 2 QUANTI TY 1 1 1 3 1 As requi red1
COMPONENTS REQUIRED: S.NO 1
3 4. THEORY:
Connecting Wires / Patch Cords board Bread
The comparison of two numbers is an operation that determines if one number is greater than, less than, or equal to the other number. A magnitude comparator is a combinational circuit that compares the two numbers, A and B, and determines their relative magnitude. The circuit for comparing two n-bit numbers has 2 n entries in the
truth table and becomes too cumbersome even with n=3. On the other hand comparator circuits possess a certain amount of regularity. The algorithm is a direct application of the procedure a person uses to compare the relative magnitudes of two numbers. Consider two numbers, A and B, with four digits each consider
A=A A A A B=B B B B
3 2 1 0
3 2 1 0
The two numbers are equal if all pairs of significant digits are equal: A =B , A =B , A =B
and A =B
0.
When the numbers are binary, the
digits are either 0 or 1,
and the equality relation of each pair of bits
can be expressed logically with an EX- OR function Department of ECE| VVCET | Page 63
x =A B + i i i A B
for i=0,1,2,3
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The binary variables A=B=X X
1 0
=1.
A>B= A B + X
1 1
0 0
B B
A<B = A
+X
Truth Table (2 Bit magnitude Comparator): Input A Output A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A =
A >
1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1
A <
0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0
1 1 1 0 0 1 1 0 0 0 1 0 0 0 0
Procedure:
proper working.

cc
and
connections.
given.
RESULT: Thus the 2 bit magnitude comparator was constructed using logic gates and verified with its truth table.
EXP. NO: 6 DESIGN AND IMPLEMENTATION OF APPLICATION USING MULTIPLEXERS To design and implement the combinational logic using multiplexers Components required: S. No 1 2 3 4 5 6
Aim :
Components Name Digital IC trainer kit IC IC IC Bread Board Connecting wires
Range -
Ty pe 74 08 74 04 7432 -
Quantit y 1 2 1 1 1 As required
Theory:
The Block diagram shows the implementation of Boolean function using 4:1 multiplexer. The implementation table is nothing but the list of the inputs of the multiplexer and under them list of all the minterms in two columns. The first column lists all the minterms where least significant variable is complemented (C), and the second column lists all the minterms with least significant variable is un-complemented (C).
The minterms given in the function are circled and then each row is inspected separately as follows. ???If to the two minterms in a row are not circled, 0 is applied
corresponding multiplexer input. ???If the two minterms in a row are circled, 1 is applied to corresponding multiplexer input. ???If the minterm in the column 1 is circled, least significant variable is complemented (C) and applied to the corresponding multiplexer input. ???If the minterm in the column 2 is circled, least significant variable is un-complemented multiplexer input. Procedure: (C) and applied to the corresponding
proper working.

cc
and
connections.
given.
Result: Thus the implementation of the given Boolean function using multiplexer was designed, implemented and verified with its truth table.
EXP. NO : 7 DESIGN AND IMPLEMENTATION OF SHIFT REGISTERS Aim : To design, implement and verify the functioning of shift right registers (all
types) using D flip-flop. Components Required: S.NO 1 COMPONENT S Digital IC trainer kit RANG E 7474 2 ICs 7408 7404 7432 3 4 Theory: A register that is used to store binary information is known as a memory register. A register capable of shifting binary information either to the right or the left is called a shift register. Shift registers are classified into four types, Connecting wires Bread Board QUANTIT Y 1 2 2 1 1 1
1. Serial-in Serial-out (SISO) 2. Serial-in Parallel-out (SIPO) 3. Parallel-in Serial-out (PISO) 4. Parallel-in Parallel-out (PIPO)
Serial-in Serial-out (SISO): This type of shift registers accepts data serially, i.e., one bit at a time on a single input line. It produces the stored information on its single output and the output also in serial form. Data may be shifted left (from low to high order bits) using shift-left register or shifted right (from high to low order bits) using shift- right register.
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Serial-in Parallel-out (SIPO): It consists of one serial input, and outputs are taken from all the flip-flop simultaneously in parallel. In this register, data is shifted in serially but shifted out in parallel. In order to shift the data out in parallel, it is necessary to have all the data available at the outputs at the same time. Once the data is stored, each bit appears on its respective output line and all the bits are available simultaneously, rather than on a bit by bit basis as with the serial output. Parallel-in Serial-out (PISO): This type of shift register accepts data parallel, i.e., the bits are entered simultaneously into their respective flip-flops rather than a bit-by-bit basis on one line. Circuit Diagram: Parallel-in Serial-out shift Register
Circuit Diagram: Parallel IN Parallel OUT shift Register
Parallel-in Parallel-out (PIPO): In PIPO, data inputs can be shifted either in or out of the register in parallel. Procedure:
1. Test the individual ICs with its specified verification table

for proper working.

cc
and ground
connections.
4. Apply the logic inputs to the appropriate terminals of the ICs. 5. Observe the logic output for the inputs applied. 6. Verify the observed logic output with the verification/truth
table given. Pin Diagram:
Verification Table:
Result: Thus the shift registers using D flip-flop were implemented and studied their operation in 4 different modes.
EXP. NO: 8 DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTER Aim: To design and implement a 3-bit synchronous binary up and down counter using JK flip-flop. Components Required: S.NO 1 COMPONENT S Digital Trainer Kit ICs RANG E 7476 7408 7432 3 4 Theory: A Synchronous counter is also called parallel counter. In this counter the clock inputs of all the flip-flops are connected together so that the input clock signal is applied simultaneously to each flip-flop. Also, only the LSB flip-flop C has its J and K inputs connected permanently to Vcc while the J and K inputs of the other flip-flops are driven by some combination of flip-flop outputs. 3 Bit Synchronous Binary UP Counter: The J and K inputs of the flip-flop B are connected to with Q . The Connecting wires Bread Board QUANTIT Y 1 2 1 1 As required 1
J and K inputs of the flip-flop A, are connected with AND operated output of Q
and Q .
B The flip-flop C changes its state when with

each clock pulse. The flip-
the occurrence of negative transition at

flop B changes its state when Q
= 1 and when there is negative
transition at clock input. Flip-flop A changes its state when Q 1
= Q
and when there is negative transition at clock input.
3 Bit Synchronous Binary DOWN Counter: The J and K inputs of the flip-flop B are connected to with Q
. The
J and K inputs of the flip-flop A, are connected with AND operated output of Q and Q .
The flip-flop C changes its state when with
the occurrence of negative transition at
each clock pulse. The flip-flop B changes its state when Q = 1 and
when there is negative transition at clock input. Flip-flop A changes its state when Q = Q = 1
and when there is negative transition at
clock input.
Circuit Diagram:
86
87
88
Procedure:
1. Test the individual ICs with its specified verification table

for proper working.

Make sure that the ICs are enabled by giving the suitable V and ground
cc
connections.
given. Pin Diagram:
State Table (3 bit synchronous binary DOWN counter) Present State A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 A 1 0 0 0 0 1 1 1 Next State B 1 0 0 1 1 0 0 1 C 1 0 1 0 1 0 1 0 J JK Flip-Flop Inputs
A
1 0 0
K X X X X 1 0 0 0
J 1 0 X X 1 0 X X
K X X 1 0 X X 1 0
C
1 X 1
K X 1 X 1 X 1 X 1
0 X X X X
X 1 X 1 X
89
90
JK Excitation Table:
Q 0 0 1 1
0 1 0 1
J 0 1 X X
K X X 1 0
Circuit Diagram:
91
92
State Table: Present State D 0 0 0 0 0 0 0 0 1 1 C 0 0 0 0 1 1 1 1 0 0 B 0 0 1 1 0 0 1 1 0 0 A 0 1 0 1 0 1 0 1 0 1 D 0 0 0 0 0 0 0 1 1 0 Next State C 0 0 0 1 1 1 1 0 0 0 B 0 1 1 0 0 1 1 0 0 0 A 1 0 1 0 1 0 1 0 1 0 T 0 0 0 0 0 0 0 1 0 1 T input T 0 0 0 1 0 0 0 1 0 0 T 0 1 0 1 0 1 0 1 0 0 T 1 1 1 1 1 1 1 1 1 1
Result: Thus the synchronous up and down counters were constructed and tested the operations with the help of their verification tables.
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EXP. NO: 9 DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS COUNTER Aim : To design and and down implement a 4-bit asynchronous binary up
counter using JK flip-flop. Components Required: S.NO 1 2 3 4 5 6 Theory: A counter, by function, is a sequential circuit consisting of a set of flip-flops connected in a suitable manner to count the sequence of the input pulses presented to it digital form. An asynchronous counter, each flip-flop is triggered by the output from the previous flip-flop which limits its speed of operation. The settling time in asynchronous counters, is the cumulative sum of the individual settling times of flipflops. It is also called a serial counter. The asynchronous counter is the simplest in terms of logical operations, and is therefore the easiest to design. In this counter, all the flipflops are not under the control of a single clock. Here, the clock pulse is applied to the first flip- flop, i.e. the least significant bit stage of the counter, and the successive flip-flop is triggered by the output is constructed using clocked JK flip-flops. The system clock, a square wave, drives flip-flop A (LSB). The output of A drives flip-flop B, the output of B drives flip-flop C. all the J and K inputs connected to Vcc (High (1)), which means that each flip-flop toggles on the edge (-ve) clock pulse.
COMPONENT S Digital IC trainer kit
RANG E 7476
QUANTIT Y 1 2 1 1 1 As required
IC
7400 -
Bread board Connecting wires
95
Consider initially state (i.e. drives flip-flop A
all
flip-flops
to
be
in
the
logical
Q =Q =Q =Q =0). A negative transition in the clock input which
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causes Q
to change from 0 to 1. Flip-flop B doesnt change its state
since it is also requires negative transition at its clock input, i.e. it requires its clock input (Q ) to change from 1 to 0. With arrival of
second clock pulse to flip-flop A, Q
goes from 1
to 0. This change of
flop
state creates the negative going edge needed to trigger flipB, and thus Q
goes from 0 to 1. Before the arrival of the 16th clock
pulse, all the flip-flops are in the logical 1 state. Clock pulse 16 causes Q ,Q ,Q
and Q
to go
logical 0 state in turn.
Verification Table (4 bit binary ripple down counter): Clock Pulse 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
1 1 1 0 0 0 0 1 1 1 1 0 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1
98
15
99
100
Circuit Diagram:
Procedure:
1. Test the individual ICs with its specified verification

table for proper working.

cc
and ground
connections.
given.
101
102
Pin Diagram:
Verification Table (BCD ripple up counter): Clock Pulse 0 1 2 3 4 5 6 7 8 9 10
0 0 0 0 0 0 0 0 1 1 0
0 0 0
0 0 1 1 0 0 1 1 0 0 0
0 1 0
0 1 1 1 1 0 0 0
1 0 1 0 1 0 1 0
103
104
Circuit Diagram:
Result: Thus the asynchronous up, down and BCD counters were constructed and tested the operations with the help of their verification tables.
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EXP. NO: 10 Aim:
HDL FOR COMBINATIONAL LOGIC
To write a VHDL code for the combinational circuits given below and simulate the result using EDA tool. S.N o 1 2
1. Logic Gates (OR , NAND and EX-OR) Component Range / Type Name Personal Computer EDA Tool (ModelSim
5.5e)
Quantity 1 -
2. Half adder and Full adder

Components Required:
Theory: The basic steps involved in the Digital System Design are, 1. Specify the desired behavior of the circuit. 2. Synthesize the circuit.
3. Implement the circuit. 4. Test the circuit to check whether the desired specifications meet.
But as the size and complexity of digital system increase, they cannot be designed manually because their design becomes highly complex. At their most detailed level, they may consist of millions of elements (Transistors or logic gates). So, Computer aided design (CAD) tools are used in design of digital systems. One such a tool is a Hardware Description Language (HDL). HDL describes the hardware of digital systems. This description is in textual form. The Boolean expressions, logic diagrams and digital circuits (Simple and Complex) can be represented using HDL.
The HDL provides the digital designer with a means of describing a digital system at a wide range of levels of abstraction and at the same
107
time, provides access to computer aided design tools to aid in the design process at these levels.
The HDL represents digital systems in the
form
of
documentation
which can understand by human as well as computers. It allows hardware designers to express their design with behavioral constructs. An abstract representation helps the designer explore
108
architectural
alternatives
through
simulations
and
to
detect
design bottlenecks before detailed design begins.
The HDL makes it easy to exchange the ideas between the designers. It resembles a programming language, but the orientation of the HDL is specifically towards describing hardware structures and behavior. The storage, retrieval and processing of programs written using HDL can be performed easily and efficiently.
HDLs are used simulation,
to
describe
hardware
for
the
purpose
of
modelling, testing and documentation. VHDL for full adder Structural Model -- Library Declaration library ieee; use ieee.std_logic_1164.all; use work.all; -- Entity Declaration entity fa is port (a,b,c:in std_logic; sum,cout: out std_logic); end fa; -- Architecture Declaration Structural Model architecture arc_fa of fa is component ha port(a,b:in std_logic; s,c:out std_logic); end component; component gor port(a,b:in std_logic; c:out std_logic); end component;
110
111
signal s1,c1,c2:std_logic; begin ha1:ha port map(a,b,s1,c1); ha2:ha port map(s1,c,sum,c2); or1:gor port map(c1,c2,cout); end arc_fa; VHDL for half adder Data Flow Model library ieee; use ieee.std_logic_1164.all; entity ha is port ( a,b: in std_logic; s,c: out std_logic); end ha; architecture arc_ha of ha is begin s <= a xor b; c <= a and b; end arc_ha; Procedure:
1. Click the ModelSim SE 5.5e icon to start the simulation of VHDL code. 2. Select create a project options given on the welcome screen in order
to create a new project otherwise choose open a project to open the existing project.
3. Proper project name should be given along with the location to save
the project in the create project window.
4. In the main window go to file ???New ???Source ???VHDL to get in to the

source editor window.
112
113
5. Enter the VHDL source code on that source editor window and save
with the extension .vhd in the project (project created) folder and location specified previously.
6. Select file ???compile in the source editor window for compiling the written
code. If there is an error debug the error, save and compile again.
7. Load the design by selecting Design ???load design in the main window
after successful compilation of the VHDL codes.
8. Select signals from the view menu of the main window for
selecting the signals.
9. In signal window, choose edit ???force / clock for applying the

appropriate input levels for the signals selected.
10. Select view ???wave ???signals in design to view the response of the design
(Wave form) with the help of run option from the signal window.
11. Continue the simulation for different input levels with the procedure
stated above.
Result: Thus the VHDL Code for the Combinational circuits was developed and simulated using Electronic Design Automation tool.
114
115
EXP. NO : 11 Aim:
HDL FOR SEQUENTIAL LOGIC
To write a VHDL code for the sequential circuits given below and simulate the result using EDA tool. S.N o 1 2 Component Name Personal Computer EDA Tool (ModelSim 5.5e) Range / Type Quantity 1 -
1. D flip flop
Components Required:
2. Synchronous UP / DOWN Counter
Theory: The basic steps involved in the Digital System Design are,
1. Specify the desired behavior of the circuit. 2. Synthesize the circuit. 3. Implement the circuit. 4. Test the circuit to check whether the desired specifications meet.
But as the size and complexity of digital system increase, they cannot be designed manually because their design becomes highly complex. At their most detailed level, they may consist of millions of elements (Transistors or logic gates). So, Computer aided design (CAD) tools are used in design of digital systems. One such a tool is a Hardware Description Language (HDL). HDL describes the hardware of digital systems. This description is in textual form. The Boolean expressions, logic diagrams and digital circuits can be represented using HDL.
The HDL provides the digital designer with a means of describing a digital
116
system at a wide range of levels of abstraction and at the same time, provides access to computer aided design tools to aid in the design process at these levels.
The HDL represents digital systems in the form of documentation which can understand by human as well as computers. It allows hardware behavioral designers to express their design with
constructs. An abstract representation helps the designer explore
117
architectural
alternatives
through
simulations
and
to
detect
design bottlenecks before detailed design begins.
The HDL makes it easy to exchange the ideas between the designers. It resembles a programming language, but the orientation of the HDL is specifically towards describing hardware structures and behavior. The storage, retrieval and processing of programs written using HDL can be performed easily and efficiently.
HDLs are used simulation,
to
describe
hardware
for
the
purpose
of
modelling, testing and documentation. Procedure:
1. Click the ModelSim SE 5.5e icon to start the simulation of VHDL code. 2. Select create a project options given on the welcome screen in order
to create a new project otherwise choose open a project to open the existing project.
3. Proper project name should be given along with the location to save
the project in the create project window.
4. In the main window go to file ???New ???Source ???VHDL to get in to the

source editor window.
5. Enter the VHDL source code on that source editor window and save
with the extension .vhd in the project (project created) folder and location specified previously.
6. Select file ???compile in the source editor window for compiling the
written code. If there is an error debug the error, save and compile again.
7. Load the design by selecting Design ???load design in the main window
after successful compilation of the VHDL codes.
8. Select signals from the view menu of the main window for selecting
the signals.
9. In signal window, choose edit ???force / clock for applying the appropriate
input levels for the signals selected.
10. Select view ???wave ???signals in design to view the response of the design
with the help of run option from the signal window and continue. Result: Thus the VHDL Code for the Sequential circuits was developed
and simulated using EDA tool.

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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

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Digital Lab Manual

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Digital Lab Manual

EXTRACT OF ANNA UNIVERSITY SYLLABUS DIGITAL LABORATORY CSE LIST OF EXPERIMENTS

3. Design and implementation of 4-bit binary adder /

4. Design and implementation of parity generator / checker

11.Simulation of sequential circuits using HDL (VHDL/ Verilog

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Digital Lab Manual

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Digital Lab Manual

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Digital Lab Manual

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INTRODUCTION TO COMPONENTS USED

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Measuring DC Voltage by using Multimeter:

Measuring Resistance Value by using Multimeter:

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Basic Logic Gates:

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Pin Details of Digital Logic Gates:

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Addend Subtrahend Multiplier Divisor

= Difference = Product = Quotient

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Digital Lab Manual

Verification of Logic Gates:

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Digital Lab Manual

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the Boolean algebra.

is calculated and the

truth table is drawn.

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1. Test the individual ICs with its specified verification

2. Connections are made as per the circuit/logic diagram. 3.

Truth Table: Input A 0 0 1 1 B 0 1 0 1 Output A+ B 0 1 1 1 B+ A 0 1 1 1

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Truth Table: Input A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 A+ B 0 0 1 1 1 1 1 1 Output (A+B) +C 0 1 1 1 1 1 1 1 B+ C 0 1 1 1 0 1 1 1 A+ (B+C) 0 1 1 1 1 1 1 1

Truth Table: Input A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 B+ C 0 1 1 1 0 1 1 1 A. (B+C) 0 0 0 0 0 1 1 1 Output A. B 0 0 0 0 0 0 1 1 A. C 0 0 0 0 0 1 0 1 A.B+A .C 0 0 0 0 0 1 1 1

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Circuit of the ICs Used:

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