Lect 12: Hardware Architecture of 80386

Lect 12-1

386 DX Microprocessor
Flexible 32-bit Microprocessor Optimized for System Performance
Pipelined Instruction Execution On-chip Address Translation Caches Dynamic Bus Sizing

CHMOS(Complementary High-Performance Metal-OxideSemiconductor) III and CHMOS IV Technology

approximately 275,000 Transistors
more than twice that of the 80286 almost 10 times that of the 8086

132-pin Pin Grid Array (PGA) package

See fig 9.2 : pin layout See fig 9.2 (b) : signal pin numbering 80386SX : 100-lead Plastic quad flat package(PQFP) - surface mount installation
Lect 12-2

Pin Layout

Lect 12-3

Signal Pin Numbering

Lect 12-4

Interfaces of the 80386DX

Block Diagram of the 80386

Lect 12-5

Interfaces of the 80386DX

Four interfaces
Memory/IO interface Interrupt Interface DMA Interface Coprocessor Interface

Signals of the 80386DX

See Fig. 9.4 on page 377

Memory/IO Interface
Address Bus A31 - A2
Real address mode : only use 20 lines (A19 - A2) Protected mode : use 32 lines A0 - A1 : byte enable output I/O address space : 64 K bytes A2 through A31 and the
Lect 12-6

Signals of the 80386DX

Lect 12-7

Interfaces of the 80386DX

Data Bus: D31 - D0
Bi-directional Bus Dynamic Bus size : BS16 input BE0 : D0 - D7 BE1 : D8 - D15 BE2 : D16 - D23 BE3 : D24 - D31
M/IO D/C W/R 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 0 1 1 1 1 Type of Bus Cycle Interrupt Acknowledge Idle I/O data read I/O data write Memory code read Halt/shutdown Memory data read Memory data write

Memory I/O Control

M/IO : memory/ input-output indication W/R : write/read indication D/C : data/control indication

Lect 12-8

Interfaces of the 80386DX

Bus Cycle Control Signals
ADS (Address status)
indicates that M/IO, D/C, W/R, BE, and ADDR are all stable

READY (Transfer Acknowledge) NA (Next address)

Bus Interface control

LOCK (Bus lock indication)

Interrupt Interface
INTR (Interrupt request) NMI (Non-maskable Interrupt) RESET (System reset)

Lect 12-9

Interfaces of the 80386DX

DMA Interface
HOLD (Bus hold request) HLDA (Bus hold acknowledge)

Coprocessor Interface
PEREQ (Coprocessor request) BUSY (Coprocessor busy) ERROR (Coprocessor error)

System Clock
CLK2 : Clock input
twice the frequency of the microprocessor : 32MHz(16MHz), 66MHz (33MHz)

Lect 12-10

System Clock

Lect 12-11

Interfaces of the 80386DX

Hardware Organization of the Memory Address Space
Physical Memory space : 4GB
SW Viewpoint: organized ad individual byte over the address range form 00000000H through FFFFFFFFH HW Organization: No Alignment

Lect 12-12

Memory Access

Lect 12-13

Memory Access

Lect 12-14

Memory Access

Lect 12-15

Bus Cycles
Bus State and Bus Cycle
Bus cycle: minimum two processor clock periods (two bus states: T states) - T1 and T2
T state: a processor clock period (twice the period of the CLK2)

Non-pipelined and Pipelined Bus Cycle

Non-pipelined Bus Cycle

Two T states(T1 and T2)

Lect 12-16

Bus Cycles
Pipelined Bus Cycle

Lect 12-17

Bus State

Lect 12-18

Lect 12-19

READ and WRITE Bus Cycle Timing

Bus Cycles
read from memory space locked read from memory space write to memory space locked write to memory space read from I/O space write to I/O space interrupt acknowledge indicate halt or indicate shutdown

Non-pipelined Read Cycle Timing Non-pipelined Write Cycle Timing Pipelined Read- and Write-cycle timing

Lect 12-20

Non-pipelined Read Cycle Timing

M/IO D/C W/R 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 0 1 1 1 1 Type of Bus Cycle Interrupt Acknowledge Idle I/O data read I/O data write Memory code read Halt/shutdown Memory data read Memory data write

Lect 12-21

Non-pipelined Write Cycle Timing

M/IO D/C W/R 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 0 1 1 1 1 Type of Bus Cycle Interrupt Acknowledge Idle I/O data read I/O data write Memory code read Halt/shutdown Memory data read Memory data write

Lect 12-22

Pipelined Read- and Write-cycle timing

Lect 12-23