ELECTRONIC INSTRUMENTATION ET8017 DELFT UNIVERSITY OF TECHNOLOGY

Homework 3.1 to 3.5

Luis C. Gutirrez Lzaro, Student number 4180666

Abstract these set of assignments study low offset, low noise techniques such as chopper amplifier and auto-zeroing. Here is shown how undesired effects like charge injection, clock asymmetry and offset drift can affect the performance of circuits. Additionally, dynamic element matching is presented in a simple case study where its advantages are depicted and a hot-plate temperature control loop is analyzed.

Here, it is possible to observe the clock and how the spikes appear on the rise and fall edges, respectively. After demodulation, the negative spikes are placed back in the positive quadrant, causing a residual offset effect. This offset can be defined as:

= 2

I. INTRODUCTION

= 2

= 2 (1)

the development of electronic instrumentation, several innovative techniques have been developed in order to overcome the fundamental causes of readout error such as noise and offset. Nonetheless, as Prof. Makinwa use to say: Theres no such a thing as a free lunch, and some drawbacks may arise in one or another configuration, generating side effects that can undermine the behavior of the circuit under specific conditions. In these assignments, several of these effects are presented, namely voltage spikes due to charge injection in a chopper amplifier (section II), clock asymmetry (section III) and offset drift (section IV). Later, in section V, the advantages of dynamic element matching are presented on a simple amplifier case study while section VI shows a hot-plate temperature control loop. Finally, the conclusions are given in section VII.
LONG

Where Tch is the chopping period and similarly fch is the chopping frequency. Since it is given that Tch >> , the first term of the integral becomes negligible and therefore the result turns out to be 2Afch, as presented in eq. (1).

III. SOLUTION 3.2 In this problem, the source of error is due to the digital logic drivers and it is given that this may cause errors up to 1ns in the chopping waveforms. From theory, it is known that in order to completely suppress any offset, the duty cycle of the chopping waveforms must be a perfect 50%. Hence, the worst case condition in this scenario appears when the 1ns timing error occurs completely either in the high level or the low level of the clock, therefore creating the maximum possible error at the duty cycle. Figure 2 presents the offset chopped at duty cycle of 50% and with an increment on the high level equal to a time delay td.

II. SOLUTION 3.1 In this assignment it is considered that the input chopper of a chopper amplifier creates exponentially decaying spikes with and amplitude A and a time constant that is significantly less than the chopping period. Figure 1 shows an illustration of the residual offset due to charge injection [1].
A ideal

delayed

Tch

td

Fig. 2: Chopped offset at 50% and with digital logic error.

Fig. 1: Illustration of the residual input offset due to charge injection.

Given that the amplitude of the offset is 2 mV and the chopping frequency is 10 kHz (i.e. a period of 100 s) and the maximum time delay td is 1ns, the worst case residual offset can be obtained as: = = = 20 [ ] 2

ELECTRONIC INSTRUMENTATION ET8017 DELFT UNIVERSITY OF TECHNOLOGY

IV. SOLUTION 3.3 An amplifier with a finite gain of 100 and 10 mV input offset is utilized in an auto-zero topology. Moreover, a drift offset of 0.1 V/s due to ambient temperature variations creates an additional source of error. The auto-zero frequency used for this circuit is given to be 1 kHz. Under these conditions, it is required to calculate the worst case input residual offset for this amplifier. A representation of the offset behavior in this amplifier is depicted in figure 3.

Fig. 4: Non inverting amplifier with DEM switches.

The resistors R1 and R2 have a nominal value of 10 k with 20% tolerance. The switch resistances are 100 with a 20% tolerance as well. The spread of the gain of the amplifier, without using dynamic element matching can be determined using the worst case spread on the resistances, as follows: = 1 +
Fig. 3: Offset behavior of the auto-zeroed amplifier.

+ = 2.5 (4)

= 1 +

The horizontal dashed line on the top part of the graphic represents the intrinsic input offset of the amplifier, which is 10 mV. The linearly increasing line corresponds to the temperature drift offset. At the times t1 to t4, the auto-zero circuit samples the offset. The auto-zero phase is to be negligible, therefore one can say that the hold time is equal to the auto-zero period, which is 1ms. Two main sources of error build the input residual offset: One due to the finite gain of the amplifier and the other to the drift itself. The bottom part of the graphic shows the residual offset behavior during several auto-zeroing periods, where it can be seen that the worst case happens just before the next sampling event. At that moment, the residual offset can be calculated as: = 1 + = 199 [ ] 3 + 1

= 1. 667 (5) +

From equations 4 and 5, it is obtained that the value of the gain can go as high as 2.5 and as low as 1.667. Assuming a normal Gaussian spread on the resistors values and using 1 million samples, the gain spread would look like the one presented in figure 5.

Where A is the amplifiers gain (100), VOS is the input offset (10 mV), TAZ is the period of auto-zeroing and VOS-drift is the drift constant. V. SOLUTION 3.4 For this assignment, a typical non inverter amplifier is introduced, where the dynamic element matching technique effect must be analyzed, as shown in figure 4.

Fig. 5: Gain spread without using DEM.

Now, following the same procedure but considering the DEM is working, we get: + + + =1+ = 2.083 (6) 2

ELECTRONIC INSTRUMENTATION ET8017 DELFT UNIVERSITY OF TECHNOLOGY

The results obtained in equation 6 show that the maximum gain spread is just 0.083 above the ideal gain of 2. There is no other case to analyze since the dynamic element matching averages the values of the resistances. Figure 6 shows the gain spread of this amplifier using DEM.

Applying KCL on the positive input node of the amplifier it yields: 5 + = (7) + 5 = 2 (8) Since R2 >> R, it is obtained that VIN is equal to 2.5. Then, the temperature difference can be calculated knowing that the sensitivity of the thermocouple is 20 mV/K. = 2.5 = 125 (9) 20 10

Hence:

Fig. 6: Gain spread using DEM

Interestingly, the value of the gain cannot be less than its ideal value. This is just a consequence of the averaging process that occurs in DEM technique. Furthermore, it is possible to observe that the gain spread is highly dense between 2 and 2.01, showing a great improvement in gain stability compared to its counterpart without DEM. It is important to stress that the same data sets were used in both spread analyses, and they were generated using the MATLAB function normrnd with a mean value of 10 k and a standard deviation of 660 , hence containing 6-sigma samples (>99%) within the 8 k to 12 k range. VI. SOLUTION 3.5 Assignment 3.5 considers a hot-plate control loop as shown in figure 7. Here, it is required to determine the average temperature of the hot plate considering that R1=R3=R and R2 >> R.

Considering ambient temperature as 300 K, the hot-plate average temperature is then 425 K. Now, we are interested in the value of R2 required to maintain the temperature of the hot-plate in a 1C range. Under these conditions, we are interested in the point where the output voltage of the amplifier is zero volts, which stops applying any current to the hot-plate resistance. Obviously, at that point, the hot-plate will start to lose temperature, however, this is the equilibrium point required for the calculations. Moreover, the amplifier needs to have a hysteresis band to avoid oscillations around the set point. Considering the sensitivity parameter as k, the input voltage VIN can then be redefined as k*(T-T), where T have just been calculated as 125 K and T is the 1C affordable error. Using this expression in equation 8 we get: k(T T) + 5 = 2kT T (10) Solving for R2 we get: = T T = 62 (11) 2T T 5

Therefore requiring a resistance value for R2 62 times higher than the value of R.

VII. CONCLUSIONS In these assignments, the effects of charge injection, clock mismatch and offset drift were considered. In the assignment 3.1 an expression for the residual input offset due to voltage spikes was found. The RMS value of this offset is a function of the time constant of the spikes, the chopping frequency and the spike amplitude. Intuitively, it can be seen that higher chopping frequencies increase this residual offset. The parasitic capacitances on the chopper transistors also affect this offset, considering that the charge injection depends directly on the channel charge and overlap capacitances. In 3.2, a similar effect was observed when there is a clock asymmetry and the duty cycle is not exactly 50%. If the logic

Fig. 7: Hot plate control loop from assignment 3.5.

ELECTRONIC INSTRUMENTATION ET8017 DELFT UNIVERSITY OF TECHNOLOGY driver error occurs on the period of the chopping signal but not in the duty cycle, the offset remains unaltered. Assignment 3.3 presented an amplifier with finite gain used in an auto-zeroing configuration. The residual input offset was calculated, with two components almost equal (99 and 100 V, respectively) due to the finite gain error and the temperature offset drift. Naturally, the worst case was observed at the end of each sampling and hold period. Increasing the S&H frequency would help to reduce the overall residual error; however, this is not a straightforward approach, since it is also necessary to allow enough time for the capacitors to charge to the offset value appropriately. In 3.4, the advantages of dynamic element matching were depicted. The gain spread on a simple non inverting amplifier was analyzed with and without DEM technique, showing a significant improvement on the former over the latter. Assuming a Gaussian distribution on the resistance values, it was also shown that the gain using DEM is far denser near the ideal gain value than without using this approach. Finally, a hot-plate control loop was analyzed, determining the temperature difference between the hot body and ambient temperature and the resistance ratio necessary to maintain the temperature within 1C range. REFERENCES
[1] Dynamic Offset Cancellation Techniques. Makinwa, Kofi. Smart Sensors Systems 02. Electronic Instrumentation Laboratory, DIMES. Delft University of Technology.