DIGITAL SIGNAL PROCESSING (EEE C415)

Laboratory Manual

BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, PILANI K.K. BIRLA GOA CAMPUS 2012

INTRODUCTION
This Digital Signal Processing Laboratory manual is to accompany the course EEE C415 DSP at the BITS-Pilani K.K.Birla Goa campus. It introduces the Code composer studio software and the DSP Starter Kits (DSK). The DSP laboratory has TMS320C6455, TMS320C55XX as well as emulator kits.

This lab manual will help the students to have hands-on experience on CCS as well as DSK. Few project ideas for real-time implementation are also suggested.

Table of contents
1. Introduction to Digital Signal Processing

1.1 TMS 320 Family

1.2 Code composer studio

2. Procedure to work on code composer studio

3. Introduction to DSK

4. Lab sessions

5. Exercises and Project Ideas

1. Introduction to Digital Signal Processing

Digital Signal Processing is one of the most powerful technologies that will shape science and engineering in the twenty-first century. It finds application in communication, medical, space, automotive, industrial, graphics, imaging fields. The areas and applications are numerous. It has in fact helped in bringing revolution in many areas in science and technology. Digital signal processors, specifically designed to handle digital signal processing tasks, have seen tremendous growth in the last decade, finding use in everything from cellular telephones to advanced scientific instruments. In fact, hardware engineers use "DSP" to mean Digital Signal Processor, just as algorithm developers use "DSP" to mean Digital Signal Processing. It is important to choose a right DSP according to the application requirement.

One of the biggest bottlenecks in executing DSP algorithms is transferring information to and from memory. This includes data, such as samples from the input signal and the filter coefficients, as well as program instructions, the binary codes that go into the program sequencer. For example, suppose we need to multiply two numbers that reside somewhere in memory. To do this, we must fetch three binary values from memory, the numbers to be multiplied, plus the program instruction describing what to do. The architectures of modern DSPs are substantially different with respect to this aspect. We will be considering the modern VelociTI architecture developed by TI in the DSP laboratory for this course. Digital Signal Processing can be divided into two categories, fixed point and floating point. These refer to the format used to store and manipulate numbers within the devices. Fixed point DSPs usually represent each number with a minimum of 16 bits, although a different length can be used. In comparison, floating point DSPs typically use a minimum of 32 bits to store each value. This results in many more bit patterns than for fixed point. A key feature of floating point notation is that the represented numbers are not uniformly spaced. In the most common format (ANSI/IEEE Std. 754-1985), the largest and smallest numbers are 3.41038 and 1.210
-38

respectively. All floating point DSPs can also handle fixed point numbers, a necessity to implement counters, loops, and signals coming from the ADC and going to the DAC.

1.1

The TMS320 DSP family

The TMS320 DSP family consists of fixed-point, floating-point, and multiprocessor digital signal processors (DSPs). TMS320 DSPs have an architecture designed specifically for realtime signal processing. With a performance of up to 8000 million instructions per second (MIPS) and an efficient C compiler, the TMS320C6000 DSPs give system architects unlimited possibilities to differentiate their products. High performance, ease of use and affordable pricing make the C6000 generation the ideal solution for multichannel, multifunction applications, such as:

Pooled modems Wireless local loop base stations Remote access servers (RAS) Digital subscriber loop (DSL) systems Cable modems Multichannel telephony systems

1.2

Code Composer Studio

TI has a variety of development tools available that enable quick movement through the digital signal processor (DSP) based application design process from concept, to code/ build, through debug analysis, tuning, and on to testing. Many of the tools are part of TIs real-time eXpressDSP software and development tool strategy, which is very helpful in quickly getting g started as well as saving valuable time in the design process. TIs real-time eXpressDSP Software and Development Tool strategy includes three components that allow developers to use the full potential of TMS320 DSPs: Powerful DSP-integrated development tools in Code Composer Studio eXpressDSP Software, including: Scalable, real-time software foundation: DSP/BIOS kernel Standards for application interoperability and reuse: TMS320 DSP Algorithm Standard Design-ready code that is common to many applications to get you started quickly on DSP design: eXpressDSP Reference Frameworks A growing base of TI DSP-based products from TIs DSP Third Party Network, including eXpressDSP-compliant products that can be easily integrated into systems [1]

Fig 1.1 eXpress DSP Software and Development Tools [1]

Code Composer Studio (CCS) is the standard Integrated Development Environment (IDE) for Texas Instrument C2000/C5000/C6000 DSPs.

Fig 1.2. Code Composer Studio

Code Composer Studio speeds and enhances the development process for programmers who create and test real-time, embedded signal processing applications. It provides tools for configuring, building, debugging, tracing, and analyzing programs. Code Composer Studio

extends the basic code generation tools with a set of debugging and real-time analysis capabilities. Code Composer Studio supports all phases of the development cycle shown here:

Fig 1.3. Simplified Code Composer Studio Development Flow

Code Composer is the DSP industrys first fully integrated development environment (IDE) with DSP-specific functionality. With a familiar environment liked MS-based C++TM, Code Composer lets you edit, build, debug, profile and manage projects from a single unified environment. Other unique features include graphical signal analysis, Injection/extraction of data signals via file I/O, multi-processor debugging, automated testing and customization via a C-interpretive scripting language and much more. CODE COMPOSER FEATURES INCLUDE: IDE Debug IDE Advanced watch windows Integrated editor File I/O, Probe Points, and graphical algorithm scope probes Advanced graphical signal analysis Interactive profiling Automated testing and customization via scripting Visual project management system Compile in the background while editing and debugging Multi-processor debugging Help on the target DSP

Procedure to work on Code Composer Studio

1. Launch Code Composer Studio (CCStudio V3.3)

2. To create a New Project

Project -> New (SUM.pjt) By default, Project Type is set as Executable (.out) and Target is set as the current configuration of Code Composer Studio. Give the name of Project. (Ex. Sum). Click Finish. Code Composer Studio creates a project file called sum.pjt. This file stores your project settings and references the various files used by your project. This project name will appear in the project pane

3.

To Create a Source file

File -> New

Type the code (Save & give a name to file, Eg: sum.c).

4. To Add Source files to Project Project ->Add files to Project -> sum.c Add files to the project by choosing Add Files to Project from the Project menu. You can also right-click the project in the Project View window on the left and then select Add Files to Project. The inclusion can be seen by the appearance of a + symbol to the left of the source folder in project pane.

Or it can be alternately done by using following method,

5. To Add rts6455.lib file Project ->Add files to Project -> rts6455.lib Path: c:\CCStudio_v3.3\c6000\cgtools\lib\rts6400.lib Note: Select Object & Library in(*.o,*.l) in Type of files

6. To add the linker command file to project Project ->Add files to Project -> c6455.cmd Path: //Myprojects/6455prog/c6455.cmd Note: Select Linker Command file(*.cmd) in Type of files

7. To Compile: Project -> Compile File 8. To build or Link: Project ->build, Which will create the final executable (.out) file.(Eg. sum.out).

In Project build options select the c64x+ compiler

9. Procedure to Load and Run program:

Load program to DSK: File -> Load program -> sum. Out

10. To execute project: Debug -> Run.

C code for Sum

sum.c
#include<stdio.h> main() { int i=30,j=40,k; k=i+j; printf("%d",k); }

Graphical Display
The buffer contains a 64 sample record of the most recently processed samples. These samples continuously write over old samples, so the buffer actually contains a discontinuity any time you halt the processor to examine the buffer. The watch window lets you look at the contents of an array, but with CCS graphical displays, you can plot the contents of a buffer and perform operations. You will then see the Graph Property Dialog. Configure the start address. Configure the acquisition buffer size and display data size both to 64 (N_buffer). Configure the DSP data type to short (16-bit signed integer). Finally configure the sampling rate to 32,000 Hz; this agrees with the setting in the DSK_Config.h file. OK the dialog and a plot window will appear.

At this point you can take measurement from the waveform by dragging the cursor around and reading the amplitude and time locations (time in seconds according to the entered sampling rate value). The Fourier transform (actually the FFT) of the data set can also be obtain by right-clicking over the graph and choosing Properties; this brings up the Graph Property Dialog one again. Under Display Type, the top listed property, choose display FFT magnitude, then OK the dialog and observe the spectrum
Using the Graph:1. Right -Click on the output variable for which you wish to view the graph. Ex. Array y[i]

2. In the panel which appears, click on View location of y

Right-click in CCS main window, for the options of inserting graph as follows,

Laboratory Instructions

1. Pen-drives, CD, Laptops are not allowed in the Lab. 2. Keep your Mobiles switched off or on silent Mode.

3. Dont keep the DSK kit on for a longer time. 4. The peak-to-peak I/P voltage should not exceed 2V while applying to Line-in on the DSK. 5. Always switch on the power much before connecting the power chord to kit. 6. Switch off the power only after disconnecting the Kit. 7. Use only Line in with the signal generator.

DSK CONNECTION TO PC
Connect the supplied USB port cable to the board Connect the other end of the cable to the USB port of PC Note: If you plan to install a Microphone, speaker, or Signal generator/CRO these must be plugged in properly before you connect power to the DSK Plug the power cable into the board Plug the other end of the power cable into a power outlet The user LEDs should flash several times to indicate board is operational Connect your DSK through USB on a Windows loaded PC where the CCS software is installed

Troubleshooting DSK Connectivity

If Code Composer Studio IDE fails to configure your port correctly, perform the following steps: Test the USB port by running DSK Port test. - The below Screen will appear Select ->Start ->Select 6455 DSK Diagnostic Utility Icon from Desktop The Screen Look like as below Select Start Option Utility Program will test the board After testing Diagnostic Status you will get PASS

Procedure to work in real time

Procedure for Real time Programs: 1. Connect CRO to the Socket Provided for LINE OUT. 2. Connect a Signal Generator to the LINE IN Socket. 3. Switch on the Signal Generator with a sine wave of frequency 500 Hz. and Vpp=1.5v 4. Now Switch on the DSK and Bring Up Code Composer Studio on the PC. (Click on the 6455 DSK V3.3 Icon. 5. Create a new project. (Same way as given before) 6. Add source file. (Same way as given before) 7. Add the library file (Location CCStudio_V3.3/Boards/dsk6455V2/Lib/dsk6455bsl)

8. From the File Menu ->new -> DSP/BIOS Configuration -> select Platform dsk6455

9. Uncheck the boxes of DSP features . Click ok, the following window will appear

10. Save the configuration (Tconf file) in the same project folder. (Ex. Configuration1.tcf)

11. Add this file (Configuration1.tcf) in the project (similar to adding source/lib files).

Choose the file type as configuration file from the drop-down menu.

12. Once this file is added to the project, two files will be created automatically for these settings under the folder Generated files. For example, in this case, Configuration1cfg.62 and configuration1cfg_c.c

13. Click on the file configuration1cfg_c.c. Copy the highlighted line as the header file name in the main program as shown.

14. Put the required header files into your project folder. For ex. Here, dsk6455.h and dsk6455_aic2.h 15. Linker command file is automatically generated, Add that .cmd file in the project

16. The DSK kit needs to be connected before loading the program on it. By default the status in disconnected, the status is indicated by CCS. Go to DEBUG -> Connect

17. Build, Load, run 18. You can notice the input signal of 500 Hz. appearing on the CRO verifying the codec configuration. 19. You can also pass an audio input and hear the output signal through the speakers. 20. You can also vary the sampling frequency using the DSK6455_AIC23_setFreq function in the code given below and repeat the above steps.

Sample program
#include "Configuration1cfg.h" #include "dsk6455.h" #include "dsk6455_aic23.h" DSK6455_AIC23_Config config = { \ 0x0017, /* 0 DSK6713_AIC23_LEFTINVOL Left line input channel volume */ \ 0x0017, /* 1 DSK6713_AIC23_RIGHTINVOL Right line input channel volume */\ 0x00d8, /* 2 DSK6713_AIC23_LEFTHPVOL Left channel headphone volume */ \ 0x00d8, /* 3 DSK6713_AIC23_RIGHTHPVOL Right channel headphone volume */ \ 0x0011, /* 4 DSK6713_AIC23_ANAPATH Analog audio path control */ \ 0x0000, /* 5 DSK6713_AIC23_DIGPATH Digital audio path control */ \ 0x0000, /* 6 DSK6713_AIC23_POWERDOWN Power down control */ \ 0x0043, /* 7 DSK6713_AIC23_DIGIF Digital audio interface format */ \ 0x0081, /* 8 DSK6713_AIC23_SAMPLERATE Sample rate control */ \ 0x0001 /* 9 DSK6713_AIC23_DIGACT Digital interface activation */ \ }; /* * main() - Main code routine, initializes BSL and generates tone */ void main() { DSK6455_AIC23_CodecHandle hCodec; Uint32 l_input, r_input,l_output, r_output; /* Initialize the board support library, must be called first */ DSK6455_init(); /* Start the codec */ hCodec = DSK6455_AIC23_openCodec(0, &config); DSK6455_AIC23_setFreq(hCodec, 1); while(1) { /* Read a sample to the left channel */ while (!DSK6455_AIC23_read32(hCodec, &l_input)); /* Read a sample to the right channel */ while (!DSK6455_AIC23_read32(hCodec, &r_input)); l_output=l_input; r_output=l_output; /* Send a sample to the left channel */ while (!DSK6455_AIC23_write32(hCodec, l_output)); /* Send a sample to the right channel */ while (!DSK6455_AIC23_write32(hCodec, r_output)); } /* Close the codec */ DSK6455_AIC23_closeCodec(hCodec); }

Lab sessions

a. To verify linear convolution b. To verify circular convolution c. Computation of FFT d. LED DIP switches e. To design FIR filter of given specifications f. To design IIR filter of given specifications

Session 1 LINEAR CONVOLUTION

Linear Convolution involves the following operations. 1. Folding 2. Multiplication 3. Addition 4. Shifting These operations can be represented by a Mathematical Expression as follows:

x[ ]= Input signal Samples h[ ]= Impulse response co-efficient. y[ ]= Convolution output. n = No. of Input samples h = No. of Impulse response co-efficient. Algorithm to implement C or Assembly program for Convolution: Eg: x[n] = {1, 2, 3, 4} h[k] = {1, 2, 3, 4} Where: n=4, k=4. ; Values of n & k should be a multiple of 4. If n & k are not multiples of 4, pad with zeros to make multiples of 4 r= n+k-1 ; Size of output sequence. = 4+4-1 =7

Output: y[r] = { 1, 4, 10, 20, 25, 24, 16}. NOTE: At the end of input sequences pad n and k no. of zeros

PROCEDURE: Open Code Composer Studio; make sure the DSP kit is turned on. Start a new project using Project-new pull down menu, save it in a separate directory with name lconv.pjt. Add the source files lconv.c to the project using Project ->add files to project pull down menu. Add the linker command file c6455.cmd . (Path: myproject/6455prog/c6455cmd) Add the library file rts6400.lib (Path: ccstudio_v3.3\c6000\cgtools\lib\rts6400.lib) Compile the program using the Project-compile pull down menu or by clicking the shortcut icon on the left side of program window. Build the program using the Project-Build pull down menu or by clicking the shortcut icon on the left side of program window. Load the program (lconv.out) in program memory of DSP chip using the Fileload program pull down menu. To View output graphically Select view -> graph -> time and frequency.

Session 2 CIRCULAR CONVOLUTION

Steps for Cyclic Convolution
Steps for cyclic convolution are the same as the usual convolution, except all index calculations are done "mod N" = "on the wheel" Steps for Cyclic Convolution Step1: .Plot f[m] and h[m]

Step 2: "Spin" h[m] n times Anti Clock Wise (counter-clockwise) to get h[n-m] (i.e. Simply rotate the sequence, h[n], clockwise by n steps)

Step 3: Point wise multiply the f[m] wheel and the h[nm] wheel. sum=y[n] Step 4: Repeat for all 0nN1 Example 1: Convolve (n = 4)

Multiply f[m] and sum to yield: y[0] =3

Multiply f[m] and sum to yield: y[1] =5

Multiply f[m] and sum to yield: y[2] =3

Multiply f[m] and sum to yield: y[3] =1

PROCEDURE: Open Code Composer Studio; make sure the DSP kit is turned on. Start a new project using Project-new pull down menu, save it in a separate directory with name cir_conv.pjt. Add the source files cir_conv.C to the project using Project->add files to project pull down menu. Add the linker command file c6455.cmd . (Path: myproject/6455prog/c6455cmd) Add the library file rts6400.lib (Path: ccstudio_v3.3\c6000\cgtools\lib\rts6400.lib) Compile the program using the Project-compile pull down menu or by clicking the shortcut icon on the left side of program window. Build the program using the Project-Build pull down menu or by clicking the shortcut icon on the left side of program window. Load the program (cir_conv.out) in program memory of DSP chip using the Fileload program pull down menu.

Session 3 Fast Fourier Transforms (FFT)

The DFT equation 1 =

Where twiddle factor

In the Definition of the DFT, there is a factor called the Twiddle Factor where N = number of samples. If we take an 8 bit sample sequence we can represent the twiddle factor as a vector in the unit circle. e.g.

Note that 1. It is periodic. (i.e. it goes round and round the circle !!) 2. That the vectors are symmetric 3. The vectors are equally spaced around the circle. Why the FFT? If you look at the equation for the Discrete Fourier Transform you will see that it is quite complicated to work out as it involves many additions and multiplications involving complex numbers. Even a simple eight sample signal would require 49 complex multiplications and 56 complex additions to work out the DFT. At this level it is still manageable; however a realistic signal could have 1024 samples which requires over 20,000,000 complex multiplications and additions. As you can see the number of calculations required soon mounts up to unmanageable proportions.

The Fast Fourier Transform is a simply a method of laying out the computation, which is much faster for large values of N, where N is the number of samples in the sequence. It is an ingenious way of achieving rather than the DFTs clumsy P^2 timing. The idea behind the FFT is the divide and conquers approach, to break up the original N point sample into two (N / 2) sequences. This is because a series of smaller problems is easier to solve than one large one. The DFT requires (N-1)^2 complex multiplications and N(N-1) complex additions as opposed to the FFTs approach of breaking it down into a series of 2 point samples which only require 1 multiplication and 2 additions and the recombination of the points which is minimal. For example Seismic Data contains hundreds of thousands of samples and would take months to evaluate the DFT. Therefore we use the FFT. FFT Algorithm The FFT has a fairly easy algorithm to implement, and it is shown step by step in the list below. This version of the FFT is the Decimation in Time Method 1. Pad input sequence, of N samples, with ZEROs until the number of samples is the nearest power of two. e.g. 500 samples are padded to 512 (2^9) 2. Bit reverse the input sequence. e.g. 3 = 011 goes to 110 = 6 3. Compute (N / 2) two sample DFTs from the shuffled inputs. 4. Compute (N / 4) four sample DFTs from the two sample DFTs. 5. Compute (N / 2) eight sample DFTs from the four sample DFTs. 6. Until the all the samples combine into one N-sample DFT Shuffled Inputs The process of decimating the signal in the time domain has caused the INPUT samples to be re-ordered. For an 8 point signal the original order of the samples is 0, 1, 2, 3, 4, 5, 6, 7 But after decimation the order is 0, 4, 2, 6, 1, 5, 3, 7 At first it may look as if there is no order to this new sequence, BUT if the numbers are represented as binary a patter soon becomes apparent.

Original input Decimal Binary 0 000 1 001 2 010

Re-ordered input Binary Decimal 000 0 100 4 010 2

3 4 5 6 7

011 100 101 110 111

110 001 101 011 111

6 1 5 3 7

What has happened is that the bit patterns representing the sample number has been reversed. This new sequence is the order that the samples enter the FFT.

ALGORITHM TO IMPLEMENT FFT: Step 1 - Select no. of points for FFT (Eg: 64) Step 2 Generate a sine wave of frequency f. (eg: 10 Hz with a sampling rate =No. of Points of FFT (eg. 64)) using math library function. Step 3 - Take sampled data and apply FFT algorithm. Step 4 Use Graph option to view the Input & Output. Step 5 - Repeat Step-1 to 4 for different no. of points & frequencies.

Session 4 LED DIP switches

Procedure
Initialize the DIP switches Retrieve the DIP switch value Initialize the LEDs Turn the LEDs ON/OFF/Toggle using DIP switches values. Code for the LED program is given below

#include "ledcfg.h" #include "dsk6455.h" #include "dsk6455_led.h" #include "dsk6455_dip.h" void main( ) { DSK6455_init( ); DSK6455_LED_init( ); DSK6455_DIP_init( ); while( 1 ) { if ( DSK6455_DIP_get( 0 ) == 0 ) { DSK6455_LED_on( 0 ); DSK6455_LED_toggle( 1 ); DSK6455_LED_toggle( 2 ); DSK6455_LED_toggle( 3 ); } else { DSK6455_waitusec( 200000 ); } if ( DSK6455_DIP_get( 1 ) == 0 ) { DSK6455_LED_on( 1 ); DSK6455_LED_toggle( 0 ); DSK6455_LED_toggle( 2 ); DSK6455_LED_toggle( 3 ); } else { DSK6455_waitusec( 200000 ); } } }

Session 5 FIR filter

To design FIR filter of given specifications

Following are the steps to design linear phase FIR filters Using Windowing Method. I. Clearly specify the filter specifications. Eg: Order = 30; Sampling Rate = 8000 samples/sec Cut off Freq. = 400 Hz. II. Compute the cut-off frequency W c Eg: W c = 2*pie* fc / Fs = 2*pie* 400/8000 = 0.1*pie III. Compute the desired Impulse Response h d (n) using particular Window Eg: b_rect1=fir1(order, W c , high,boxcar(31)); IV. Convolve input sequence with truncated Impulse Response x (n)*h (n)

USING MATLAB TO DETERMINE FILTER COEFFICIENTS : Using FIR1 Function on Matlab B = FIR1(N,Wn) designs an N'th order lowpass FIR digital filter and returns the filter coefficients in length N+1 vector B. The cut-off frequency Wn must be between 0 < Wn < 1.0, with 1.0 corresponding to half the sample rate. The filter B is real and has linear phase, i.e., even symmetric coefficients obeying B(k) = B(N+2-k), k = 1,2,...,N+1. If Wn is a two-element vector, Wn = [W1 W2], FIR1 returns an order N bandpass filter with passband W1 < W < W2. B = FIR1(N,Wn,'high') designs a highpass filter. B = FIR1(N,Wn,'stop') is a bandstop filter if Wn = [W1 W2].

If Wn is a multi-element vector, Wn = [W1 W2 W3 W4 W5 ... WN], FIR1 returns an order N multiband filter with bands 0 < W < W1, W1 < W < W2, ..., WN < W < 1. B = FIR1(N,Wn,'DC-1') makes the first band a passband. B = FIR1(N,Wn,'DC-0') makes the first band a stopband. For filters with a passband near Fs/2, e.g., highpass and bandstop filters, N must be even. By default FIR1 uses a Hamming window. Other available windows, including Boxcar, Hanning, Bartlett, Blackman, Kaiser and Chebwin can be specified with an optional trailing argument. For example, B = FIR1(N,Wn,kaiser(N+1,4)) uses a Kaiser window with beta=4. B = FIR1(N,Wn,'high',chebwin(N+1,R)) uses a Chebyshev window. By default, the filter is scaled so the center of the first pass band has magnitude exactly one after windowing. Use a trailing 'noscale' argument to prevent this scaling, e.g. B = FIR1(N,Wn,'noscale'), B = FIR1(N,Wn,'high','noscale'), B = FIR1(N,Wn,wind,'noscale') Write a Matlab Program to generate FIR Filter-Low Pass Coefficients using FIR1and C program to implement FIR filter from this coefficients.

PROCEDURE : Switch on the DSP board. Open the Code Composer Studio. Create a new project Project -> New (File Name. pjt , Eg: FIR.pjt) Initialize on board codec. Add the C. source file to the current project Connect the speaker jack to the input of the CRO. Build the program. Load the generated object file(*.out) on to Target board. Run the program

Observe the waveform that appears on the CRO screen. Tabulate the observed amplitudes corresponding to different frequencies Plot the frequency response of the different window filters by changing the filter coefficients and repeating thereafter. This way obtain frequency response plots for different filters. Vary the frequency on function generator to see the response of filter. Observe and note the main lobe width, side (first) lobe amplitude for comparison of different window techniques used here.

Observations
View the waveform on the CRO and tabulate the frequency obtained in each case. window type Frequency (Hz) Filter gain (dB) 10 log(Vout/Vin)

Session 6 IIR filter

To design IIR filter of given specification

Filter Specifications Butterworth Fs=..Hz Passband = Hz Stopband= .Hz Gain in Passband =..db Stopband attenuation=.db Chebyshev (Type 1) Fs=..Hz Passband = Hz Stopband= .Hz Gain in Passband =..db Stopband attenuation=.db Elliptic Fs=..Hz Passband = Hz Stopband= .Hz Gain in Passband =..db Stopband attenuation=.db

TheoryAn IIR stands for Infinite Response Filter. Such a filter has infinite number of impulse response coefficients. Due to this the filter is realized recursively. An IIR filter has a number of properties, which makes it different from the FIR filter. The IIR filter can realize both poles and zeros of the system. The transfer function of an IIR filter is shown below.

= 1

The roots of the denominator determine the pole locations of the filter and the roots of the numerator determine the zero locations. The difference equation of such a system is described by the following, = + In most applications the order of the 2 polynomials M and N are equal. There are several means of implementing the above transfer function with an IIR structure. Key features of an IIR filter

The IIR filter has fewer number of coefficients required for a particular filter design (Higher efficiency) Due to its recursive realization(which requires a feedback), such a filter can become unstable. The IIR filters do not posses linear phase and so are not preferred for sound processing based applications. The IIR filters have less memory requirements due to lesser number of coefficients.

This is one of the basic realization structures for IIR filters. It directly relates to the difference equation of an IIR filter
= +

The Z-1 block represent memory to store a sample value of the input signal. This structure requires more number of memory elements to implement. The coefficients of the filter bs (numerator) and as (denominator) have been shown as gain multiples in the figure. Multiplication and addition is carried out and the recursive portion of the IIR filter is clearly visible in the implementation. Butterworth filterThis filter has no ripples in passband and stopband. Chebyshev filter This filter has ripples in the passband while no ripples in the stopband. Elliptic filterThis filter has ripples in the passband and the stopband

Use MATLAB to determine filter coefficients, write a C code to implement the filter. PROCEDURE : Switch on the DSP board. Open the Code Composer Studio. Create a new project Project -> New (File Name. pjt , Eg: IIR.pjt) Initialize on board codec. Add the C. source file to the current project Connect the speaker jack to the input of the CRO. Build the program. Load the generated object file(*.out) on to Target board.

Run the program Observe the waveform that appears on the CRO screen. Tabulate the observed amplitudes corresponding to different frequencies Plot the frequency response of the different window filters by changing the filter coefficients and repeating thereafter. This way obtain frequency response plots for different filters. Vary the frequency on function generator to see the response of filter.

Observations
View the waveform on the CRO and tabulate the frequency obtained in each case. Filter type Butterworth Frequency Filter gain (dB)

Filter type Chebyshev fiter

Frequency

Filter gain (dB)

Chebyshev Type 1 :- Passband ripple =dB

Filter type Butterworth

Frequency

Filter gain (dB)

Elliptic filter:- Passband filter =dB, Stopband filter= dB

Exercises and Project Ideas

Exercises Sound effect generator To implement some features of audio processing on DSK processor like volume control, Panning, Echo, reverberation, Flanging. Project Ideas 1. 2. 3. 4. 5. To implement companding techniques ( A-law, Mu-law companding) To perform sampling rate conversion (Multi-rate DSP) Design the DTMF detector Design a Winamp-like visual display Design and implement a 4-channel (time multiplexed) audio mixer

References [1]. SPRU509. Code Composer Studio v3.1 IDE Getting Started Guide