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IEEE TRANSACTIONS ON EDUCATION. VOL. 32. NO. 3. AUGUST 1989

Introducing VLSI Computer-Aided Design into the EE Curriculum: A Case Study

Abstract-The rapid progress in VLSI technology, as evidenced by continual increases in chip size, density, and speed, has produced a need within the E E curriculum for design courses which tie together the disparate disciplines required in producing a VLSI device, and provide experience in utilizing the CAD tools necessary for their design. These disciplines include device physics, circuit design, logic design, system or architectural design, and software, and a r e currently found in most E E curricula. However, they a r e typically considered in isolation, and generally lack a design component, stressing fundamental analysis tools and mathematical models over design experience and heuristics. T h e integration of CAD experience into the E E curriculum has become important because future chip designers will depend on these tools to overcome the enormous complexity inherent in VLSI design. This paper describes a case study at Purdue Universitys School of Electrical Engineering in the successful integration of VLSI CAD into both the undergraduate and graduate curriculum. This success was due to several factors, including university-industry-government cooperation; the development of a comprehensive set of interactive tutorials and notes describing the lab procedures and VLSI issues considered in the class; and a coherent, structured approach to teaching system design and the use of CAD tools in this process. New educational technologies, including computer-aided instruction (CAI) and video-taped lectures on VLSI, have also played a part in the development of the CAD courses.

I. INTRODUCTION
HE issue of incorporating design into the EE curriculum has, in recent years, been of great interest [1][ 5 ] . This issue has gained even more importance as VLSI technology has advanced and provided an implementation medium of great complexity. If a system designer is to use this medium effectively, he must have some understanding of design techniques for managing this complexity and some experience in their use. Although it may be argued that such experience is best gained when a student goes to industry, several goals may be served by incorporating VLSI design experience early in an electrical engineers education: motivate the use of analytical tools and models developed elsewhere in the curriculum;
Manuscript received February 5, 1988. This work was supported in part by the IBM Corporation and the Indiana Corporation for Science and Technology. M. T. OKeefe and J. C. Lindenlaub are with the School of Electrical Engineering, Purdue University, West Lafayette, IN 47907. S . C. Bass was with the School of Electrical Engineering, Purdue University. He is now with the Department of Electrical and Computer Engineering. George Mason University, Fairfax, V A 22030. T. P. Wahlen was with the Federal Systems Division. IBM Corporation. Manassas, VA. He is now with the Marketing and Service Group. IBM Corporation. Pittsburgh, PA. IEEE Log Number 8929073.

introduce design in a formal framework so that a student learns disciplined, structured design techniques; and discuss all levels of VLSI design, not just what an engineer considers his or her specialty, to provide a more complete view of the design process. Due to the effects of intense competitive pressure, it is unlikely that these goals can be served well by industry. In an effort to satisfy these and other goals, Purdue University, in cooperation with the IBM Corporation, has recently introduced courses in VLSI chip design using IBMs Manassas VLSI Interactive System for Automation (MVISA). MVISA is a CAD program that implements all stages in the VLSI design process, including logic entry (schematic capture), logic simulation, timing analysis, design rule checking, placement of cells, and automatic and manual wiring. An undergraduate laboratory course and a graduate course based on the MVISA system are now offered at the School of EE. The focus of this paper will be the integration of VLSI CAD into the EE curriculum. We will discuss the practical difficulties of initiating and operating courses on VLSI CAD from several different perspectives: industry, university administration, instructor, and student. The use of new educational technologies, including CAI and video-taped lectures, will be examined. We will also discuss the IBM-Purdue relationship as an example of effective university-industry cooperation. This relationship has several elements. It provides for the development of VLSI CAD courses based on the MVISA system, creation of the necessary educational materials, the fabrication of VLSI chips designed by students at the IBM Federal Systems Division (FSD) in Manassas, VA, and the execution of several development tasks by university personnel. Significant financial support for introducing these courses was also obtained from the State of Indiana through the Indiana Corporation for Science and Technology and from the Tektronix Corporation. The paper is organized as follows. Section I1 will consist of a description of the MVISA system and the hardware and software resources at Purdue required to support the laboratory. The IBM-Purdue relationship is also discussed. Section I11 will concentrate on the courses supported by MVISA, covering the structure, philosophy, and goals behind them and their relationship to the EE curriculum at Purdue. In Section IV, the research and development projects associated with the MVISA system are described. Section V is dedicated to a summary. Our hope

0018-9359/89/0800-0226$01.OO 0 1989 IEEE

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is that the lessons learned in this effort will provide an understanding of some of the difficulties involved in introducing VLSI CAD courses and how to avoid them. 11. MVISA SYSTEM AT PURDUE UNIVERSITY MVISA is a VLSI CAD system which is used to design VLSI digital circuits [6]. Its salient features include automatic placement and wiring of a logic design, allowing the designer to concentrate on system level design and simulation, and the systematic incorporation of testability into a chip design through the level sensitive scan design (LSSD) technique [9]. The MVISA user may also employ manual placement and wiring to optimize critical paths and resolve wiring problems. The MVISA system can be applied to several different technologies: at Purdue, it has been used to design 2 pm NMOS on a fixed die size of either 4.2 x 4.2 mm or 8 . 0 x 8.0 mm. These chip sizes provide 560 and 2952 internal cells, respectively, each cell being the maximum equivalent of a four-input NOR gate (ten NMOS transistors, including buffers). The 4.2 x 4.2 mm chip image was developed by IBM FSD for the VLSI Academic Program [7], and provides student designers a reduced chip size more appropriate for projects implemented in a one-semester course. The discussion of the MVISA system at Purdue is given in two parts: first, a description of the basic steps used to design a VLSI chip in MVISA are given; then, hardware and software resources to support MVISA at Purdue are described. A . MVISA Design System The MVISA system at Purdue is targeted for a polysilicon gate, NMOS process, using 2 pm line widths and two levels of metal. The VLSI design methodology used is the masterimage approach [8], which shares features common to both standard cell and gate array techniques. In a masterimage chip, the chip floorplan consists of a regular, fixed array of cell sites where each site represents a reserved area of silicon which a circuit may occupy. This is similar to a gate array approach except that each cell in a gate array consists of a predefined set of transistors. The circuits used in a masterimage chip will be unique to each individual function so that better performance and density than that achieved by gate arrays is possible. It is this aspect of masterimage design that makes it similar to standard cells. A small difference is that in many standard cell systems, the chip floorplan can be varied to achieve a smaller die size. This is usually accomplished through shrinking the wiring bays between rows of cells. The die size and floorplan in a masterimage chip are fixed, and cannot be changed to achieve more compaction. The masterimage floorplan for the 4.2 mm chip is shown in Fig. 1. Although masterimage is somewhat different from standard cells in the lowest transistor and circuit level details, the design techniques used at the logic and system level are the same. In both the masterimage and standard cell design methods, a library is available from which the chip designer may select cells to implement a digital design.

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The cell library contains the standard set of basic logic gates including NOR, NAND, INVERT, and more complex circuits such as ALUs, registers, multiplexors, full adders, magnitude comparators, parity generators, carrylookahead generators (CLAs), counters, and others. Several RAM macros of various sizes are also available. 110 circuits, including receivers, drivers, and transceivers, are provided to translate between the internal NMOS voltage levels and the TTL levels required off chip. A flow diagram detailing the steps necessary to design a chip using MVISA is given in Fig. 2. The first step is logic entry, more generally referred to as schematic capture. The MVISA user enters the selection of chip library cells (known as blocks) into the design database. The user can interactively edit these blocks and the connections between them. Two tests, DRC (design rules check) and Block Check, are applied at this stage. The DRC check ensures that the LSSD design for testability rules required by IBM are followed, while the Block Check verifies that blocks are used correctly. After logic entry is completed, a series of prephysical design (Pre-PD) tests are run. These tests flag errors associated with logic entry that will interfere with physical design, such as too many cells for the given chip size, improper I/O pin naming conventions, or excessive fanout on pins that may cause performance degradation. If these tests are passed, the next step is to perform a logic simulation of the design. This is accomplished using the AUSSIM simulator, developed at IBM Austin. This logic simulator utilizes a library of rules associated with each cell in the library to accurately model cell behavior and delays. Adherence to data setup times and other timing constraints are monitored during simulation. The simulation can be directed by a set of commands contained in a file, by commands entered interactively by a user at a terminal, or a combination of both. Results of the simulation may be observed using an option contained within

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IEEE TRANSACTIONS ON EDUCATION. VOL. 32. NO. 3. AUGUST 1989

w a
Logic Entry Pre-PD

AUSSIM

f i
ETE (Early Timing Estimator) Placement

Wire

CHECK

? I

Fabrication

Fig. 2. MVISA subsystems

AUSSIM called SCOPE, which generates a set of timing diagrams for display on a high-resolution graphics screen. This output format is very similar to that of logic analyzer, and many features are available to manipulate the display to facilitate debugging the logic design. Any logic or timing errors found while using AUSSIM or other errors found with Pre-PD require the user to return to logic entry to correct the problems. Following AUSSIM verification of functional operation of the logic design, the early timing estimator (ETE) is employed to estimate wiring capacitances, and this information is applied to calculate individual block delays. Worst case path delays are then determined and can be used by the designer to identify critical paths before the actual placement and wiring of the chip is performed. Before commencing with the actual placement and wiring of the chip, the MAP program is executed to convert the blocks selected in logic entry to their physical counterparts in the cell library. This step is performed automatically when the user enters the placement program. During the placement process, both manual and automatic options are available. Very large macros (groups of cells), such as RAMS, must be placed using manual techniques, which employ a Tektronix 614 graphics display and a joystick. The remaining cells are placed using the automatic placement option. The manual option may need to be invoked following automatic placement if there is a need to rearrange macros to improve performance or if

there are cells which could not be placed. The latter event rarely occurs unless the number of cells used in the logic design is very near the capacity of the chip. Wireability analysis may be performed to determine the quality of placement in terms of the difficulty in wiring the chip. A histogram showing wiring channel demand versus availability is displayed on the Tektronix 614 graphics display. Potential problems discovered here may require modifications to the placement to achieve a high wiring completion rate with the automatic wiring program. The early timing estimator (ETE) may again be invoked following placement to calculate delays using placement information and estimated wiring lengths. The system provides three modes for wiring the chip: automatic channel packer, automatic line probe, and manual. The channel packing algorithm is the workhorse of the wiring process, and typically achieves completion rates above 99 percent. The remaining connections may be completed using the line probe algorithm or manually if necessary. Manual wiring is also necessary to implement any logic changes without performing a complete redesign. Once again, ETE is employed following actual wiring to determine performance, this time using complete information regarding wiring lengths, and hence capacitive loading to determine circuit delays precisely. After physical design is completed, several checks are required to verify that technology layout rules (physical spacing between devices) are followed and that the physical design corresponds to the logic design specified in logic entry. Additional checks are made to calculate chip power consumption and wire capacitances to determine that they are within acceptable limits based on a 10 MHz clock. All checks and other crucial steps in the design process are monitored during the design process, and an audit trail of these steps is generated before releasing the chip design to fabrication. The final physical design step is the creation of the mask (pattern generator) information in the Graphics Languagelone (GL/ 1)IBM standard format [ 131. A complete description of the algorithms used in automatic placement and wiring is given in [6].

B. Hardware and Software Resources at Purdue

The successful introduction of VLSI CAD into the EE curriculum requires a significant commitment in terms of time, personnel, and money. It was accomplished at Purdue through the combined efforts of industry, in particular IBM and Tektronix; government, as represented by the State of Indiana; and of course, Purdue University itself. IBM, through the VLSI Academic Program [7], has contributed hardware, software, and personnel to this effort at Purdue and several other universities. These contributions include fabrication privileges at the Federal Systems Division facility at Manassas, VA; assistance to MVISA designers at Purdue; software maintenance and support; hardware in the form of IBM PC-XTs, 3277 terminals, and other equipment which are configured as workstations; hardware to support the time-shared CPU, includ-

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INTRODUCING VLSI CAD INTO EE CURRICULUM

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ing several disk storage units, a magnetic tape storage unit, line printers, and communications controllers; and operating system and other software to support MVISA programs, in addition to the MVISA programs themselves. Indianas Corporation for Science and Technology (ICST) has provided approximately $342 000 for the purchase, installation, and maintenance of the dedicated IBM 434 1 mainframe computer which supports the workstations, and for other equipment used to support VLSI education at Purdue. ICSTs chief goal in supporting VLSI education at Purdue is to provide Indiana industry with a talent pool of VLSI design engineers well trained in the most important integrated circuit design techniques. The eight most frequently used workstations in the Purdue MVISA facility are IBM 3277 terminals with Tektronix 614 graphics attachments. Tektronix, Inc. has contributed to the facility by allowing Purdue to purchase these graphics units at approximately 40 percent off list price. The Universitys contribution toward the physical facilities required to house and support the MVISA system is difficult to calculate, especially at this time when space and equipment funds within the university are at a premium. The major costs that can be accounted for total about $129 000. The MVISA laboratory is custom furnished; it provides each student design team with a reasonable amount of workspace for not only their workstation equipment, but also the necessary papers, drawings, manuals, etc. A separate machine room housing the IBM 4341 and its various peripherals is provided. These two rooms are devoted solely to MVISA equipment and activities. A full-time site specialist manages the IBM mainframe and its software. The computing power of the IBM 4341 CPU is comparable to that of a dual VAX 11 /780. The size of main memory is 16 Mbytes, and disk storage capacity is roughly 3.5 Gigabytes. It is a time-shared system running under the VM cms operating system. During a normal semester, this system must support nearly 60 regular MVISA users, although the number of students on the system at any one time is lower, typically 10-12 students. These students regularly use the combination 3277 terminals and Tektronix 614 high-resolution displays; the 614 display allows the students to perform detailed manual placement and wiring using a joystick and crosshairs, view their current logic design, and manipulate the simulation timing diagrams to aid debugging. The students may also use the PC/XTs as the interface to the mainframe for these tasks. The PC/XTs have 512 bytes of RAM (an extra RAM card is necessary), a 10 Mbyte hard disk and floppy disk unit, a 3278/79 adapter card which is required to interface the PC to the mainframe, a mouse and PC Paint graphics software, and an enhanced color monitor and card to go with the standard monochrome display. Software is provided which will configure the PC with the color monitor as a Tektronix 614 display, and the monochrome display and PC keyboard as the 3277 terminal. Other universities in the VLSI Academic Program have made exclusive use

of PCs, connected to a time-shared IBM mainframe, as the workstations in their programs [7]. A total of 14 workstations are available in the MVISA laboratory. The successful introduction of classes using MVISA has been supported by the networking of computing resources at Purdue. The IBM mainframe is connected to a local area network, the Engineering Computer Network (ECN), that serves the schools of engineering at Purdue. The Engineering Computer Network is comprised of an Ethernet connection between numerous VAX 11/780s and several superminicomputers from Gould and CCI Corporation. The student users of the IBM system typically have accounts on several ECN machines, and it is possible to log in to the IBM mainframe from another computer on the network. Thus, it is possible to use any part of the MVISA software from a terminal that is physically remote from the lab. File transfers between the IBM mainframe and any other machines on the network are also supported. ECN supports electronic mail, and this facility is heavily used to communicate to the students information concerning new software features, fixes to bugs that have appeared in MVISA programs, changes in class procedures, and other information that changes quickly and must be disseminated rapidly. Electronic mail is also used by the teaching assistants to send out class announcements, and it has proven to be an extremely effective way to get information out quickly and efficiently. A BITNET link exists between the IBM Manassas facility and Purdues IBM mainframe. This connection has been used to transfer chip designs to be fabricated, MVISA software updates, and messages between MVISA support personnel at Manassas and Purdue.
C. Discussion

Several issues are important when deciding on which particular VLSI CAD system will be employed to support VLSI design in a schools EE curriculum. These issues include the choice of the computing environment, either a time-shared CPU as in the MVISA system at Purdue or a collection of distributed workstations, each one a powerful computing engine. To some extent, a time-shared CPU approach is well suited to a large number of students working on small designs, as in beginning digital logic courses. It may be overkill to have available to each student a powerful workstation. On the other hand, for the small number of students in upper level VLSI design courses, the power and sophistication of the current class of workstations would be appropriate. Workstation hardware continues to fall in price, although the software cost remains formidable. If a common design environment thread is desired in a curriculum, and financial support resources are available, a distributed workstation environment may be appropriate. Another option would be to introduce schematic capture and logic simulation on PCbased workstations for the small designs typical of beginning digital design courses. However, these PC-based workstations would not be powerful enough to support higher level VLSI design courses that require more com-

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IEEE TRANSACTIONS ON EDUCATION. VOL 3 2 . NO 3. AUGUST 19x9

puting power to drive automatic placement and wiring or graphics. Another important issue is deciding on whether to use a proprietary system, such as IBMs MVISA, or a commercially available CAD system, such as a Mentor Graphics workstation. Proprietary CAD systems often are more coherent and structured. By focusing narrowly on a particular technology, they can provide a complete, integrated system, in which all subcomponents fit together neatly. A common design methodology is often enforced in such areas as design for testability. This is true with the MVISA system, as the LSSD design for testability methodology [9] is enforced throughout. However, commercial CAD systems typically have a prettier and more friendly user interface. Also, if the system has a large segment of the CAD market, a student is more likely to see such a system in the future. Since commercial VLSI CAD systems try to serve many technologies and strive to support a broad range of standard cell, gate array, and analog libraries, they may be applicable across a larger spectrum of classes. This fact also allows a school to obtain foundry services from many different sources, and accept software gifts from companies which use a standard CAD workstation as a platform. Unfortunately, this broader applicability often means that the system is not as integrated and complete as a proprietary CAD system. 111. VLSI CAD COURSE SUPPORTED BY MVISA Two new courses which use the MVISA system have been developed. The undergraduate laboratory course supported by MVISA, EE 357-VLSI Chip Design, seeks to introduce students to VLSI chip design while at the same time stressing engineering design methodology in general. The course also serves to motivate the analytical tools and models developed in other courses, such as introductory digital circuits, solid-state device theory, and others. The structure, philosophy, and goals of the course are discussed. Lessons learned from experience as the class evolved are examined. Many of these will apply to other efforts to introduce VLSI CAD into the EE curriculum. The graduate course, EE 595-Automated VLSI Design and Design Algorithms, includes the design of a large (20 000 transistors or larger) VLSI chip and also focuses on algorithms used in the automated physical design of VLSI devices, in particular, those used for cell placement and wiring. EE 595M emphasizes system and architectural level design. Both courses, and their relationship to the rest of the curriculum, are now described in more detail.

A. Undergraduute Course Description The undergraduate course is currently offered in four sections, 12 students per section, during the regular semester. One section is offered during the summer semester. The course meets once a week for three hours during the regular semester; when offered in summer semester, an accelerated schedule is used and the course meets twice

a week. It counts as one of seven required lab credits in the curriculum. A pool of teaching assistants (TAs) splits the teaching tasks. One TA currently handles miscellaneous support tasks associated with the hardware and software used directly by students in EE 357. This TA is often in contact with IBM support personnel to work out any MVISA software difficulties. The full-time site specialist handles the major chore of keeping the complete system working. EE 357 is an introduction to the design of digital VLSI systems. It consists of logic entry, logic simulation, placement of cells, automatic wiring, timing analysis, and testing of student designed chips. A systematic, modular design methodology is emphasized throughout the course. The first eight weeks (there are 15 total weeks in the semester) consist of a series of introductory labs along with reading assignments, short lectures by the TA, and quizzes, all of which help the students become familiar with the MVISA design system and the IBM computing environment. Except for the introductory lab experiments, lab work is done in groups of two. This allows the students to get a good understanding of the MVISA system by initially working on their own, but keeps the design project and documentation tasks manageable as they are shared among two people. The introductory labs take the student through the complete process of designing a simple NMOS chip and preparing it for fabrication by IBM. The chip is a keyboard scanner, shown in Fig. 3 , consisting of three main blocks: the scan generator, decode logic, and keyboard reader. The students are given the scan generator block, and are required to design the decode logic keyboard reader themselves. This project serves to introduce the students to logic entry, simulation, and physical design (placement and wiring) through tutorials that guide them through all the steps necessary in each process. The students digital design experience is refreshed by requiring them to complete the design of the decode logic and keyboard reader themselves. Most importantly, the keyboard scanner design exemplifies the hierarchical, modular design methodology that is emphasized throughout the course. The basic steps in this methodology are summarized as follows. 1) Consider the entire design to be a single block. 2) Write the complete specifications for the block being designed. Describe all inputs and outputs and how they relate to each other. 3 ) Develop testing criteria for the block. 4) Design the block. If it is fairly simple, this will consist of mapping .. - its function directly into the basic building blocks that are available. Otherwise, it must be divided into two or more subblocks with well-defined functions. 5) For each subblock that was proposed, start another invocation of this design process beginning from step (2) using the subblock as the block to be designed. The only prerequisite for the course is an introductory course in digital logic design and its associated lab. This course introduces students to the basic building blocks

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23 I
TABLE I
LIST OF VIDEOTAPFS A S [ ) A S S O C I A T E I )

KEYBOARD SCANNER

TOPICS
#Gates

1 DESIGN
Pipelined Multiplier 3 x 3 Content Addressable Mrmory 4 x 4 Pipelined Array Multiplier

i i Cells Used/56O

d Transistors
2635

163 247 185 198 239 125 217 409 310 505

937
1206 371 R6?

3380
1960
2194

7 ~ b i Microprocessor t

752

Decode Logic

8-bit Piograrnrnable Timer 16-bit Error Detectmn/Correction Unit CRC Asynchronous C'omrnunicatmns Transceivcr 4Kbyte FIFO BuRer 4-bit Microprocessor Slice

603 7% 2139
1617 3314
545 2,540

DAThOUTlN]

4x4 Cascadeable C o n t e n t Addresrable Llemoiy 2 x 2 Bit-Level Processor Array

ALL wrth Conditional S u m Adder
. .

20:

300
464 439

541

1727

2827 I742 2859 5447 4727 11177 2252 8684 5030 5465

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Fig. 3. Keyboard scanner.

used to implement digital systems, and the lab provides some design experience in breadboarding TTL parts into small digital designs. Surveys performed at the end of the semester indicate that students feel that they have the necessary background for EE 357. The fact that a masterimage technology is used means that students may essentially avoid most of the details of the physical design process if they wish. However, the lectures and course notes attempt to cover the major steps in the complete VLSI design process; students with the appropriate background from other courses can thus gain a better appreciation of the whole process. Table I contains a list of student designs from EE 357 fabricated at the IBM Manassas facility, and considerable design sophistication can be seen in this list. EE 357concentrates a large amount of information into a one-semester lab course, and several different educational media are used to transfer this information efficiently. These include manuals, tutorials, and lab procedure notes produced at Purdue; videoltapes concerning a variety of VLSI design issues, including design for testability; and computer-aided instruction (CAI) programs written using the PILOT programming language on the IBM PC's. The manuals, tutorials, and lab procedure notes were developed during the first two years of EE 357. They are continually being refined, and have now been collected into a comprehensive set of class notes. IBM provided a set of four manuals and several reference guides that were used by the students initially, covering the use of the AUSSIM simulator, the cell library, physical design, and logic entry. However, the students found these manuals more appropriate as references than as teaching guides. We decided to develop at Purdue new manuals to fill this need, with the idea that they were to be written for student designers. The Purdue Circuit Data Book was written to describe the cells in the library more clearly, and to act as a teach-

ing guide for student users. The Beginner's Guide to AUSSIM was also written. Since students spend a large percentage of their lab time performing logic simulation, it was important to provide them with an effective guide to the use of the AUSSIM simulator. This was accomplished through a tutorial approach, in which students were given a defective parallel-to-serial converter design, and led through the debugging features in the simulator as they corrected the design errors. This provides the student with concrete examples of the use of AUSSIM and gives them a chance to work interactively with the simulation tool and find the design errors themselves. Another tutorial gave an example of exhaustive simulation of a microprocessor design, revealing more features of the AUSSIM simulator. Additional sections of this manual gave a summary of typical error messages and their probable causes, a dictionary of common terms, and a summary of the AUSSIM commands and their most common usage. In addition to these manuals, three tutorials in logic entry, simulation, and physical design were developed. These tutorials guide the students through the detailed sequences of MVISA commands required to perform these tasks. The emphasis throughout the materials developed at Purdue is an interactive approach to learning how to use MVISA. It was found necessary to develop many lab procedure notes, each one detailing how to perform a particular lab procedure or other course-related task. These include printing logic diagrams, using the plotter to obtain a plot of a final chip design, report formats, file transfers, using the IBM operating system and utilities, and others. Notes were also provided on several issues discussed in the class, including VLSI design methodologies, design for testability in general, and level sensitive scan design (LSSD) [9] in particular. All these materials have been put together into a single set of class notes handed out at the beginning of the semester. We feel that these class notes are essential to teaching VLSI CAD effectively with the limited amount of time students have for the course. A set of videotapes have been developed which cover a variety of VLSI design issues. Some of these tapes are required viewing and some are optional. A listing of the topics covered and the featured speakers is given in Table 11. Several of the presentations cover architectures real-

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ized using the MVISA system. Others cover issues in VLSI design and design for testability using LSSD rules. These videotapes complement the class notes and reinforce the material covered there. CAI programs have been written using the PILOT programming language on the IBM PC's. These programs cover VLSI design methodologies and LSSD rules. They provide a graphics-oriented, interactive approach to presenting these topics, and include quizzes so that students may test their understanding of the material. Course grading is based on several factors, including facility with MVISA, project quality and documentation, staying on schedule, an understanding of VLSI CAD, design for testability and design methodology. Quizzes are given at the beginning of the lab period for the first five to seven weeks covering reading material, previous lectures, and work done in previous labs. A lab practical exam is given in the final lab period of the semester to test the student's facility with MVISA. It consists of entering and simulating a simple piece of logic, along with generating a few reports associated with the design. The main purpose of the lab practical is to determine if a student has leaned on a partner too much during the semester, and to deter this from happening. It has been very effective in this matter, and gives the TA's concrete information concerning each student's ability to use the MVISA system. As with many project-oriented courses, there is a great temptation for the students to put off much of the work until the end of the semester. This frequently happened during the first semesters the course was offered, with many students spending much of the last week of the semester in the lab. This detracts from the goal of teaching a structured, disciplined approach to design, and represents an inefficient use of laboratory and TA resources. To prevent this from happening in the future, a portion of the student's grade is determined by keeping up with the class schedule for the first half of the semester, and with their own project schedule during the second half of the semester. Every week or two, a checkpoint is scheduled, and the students must present evidence that they have progressed to the proper point on their schedules. The project schedules are established between each design group and the TA. Concerning these schedules, we have found that it is best to have the students alternate between logic entry and simulation as they progress through the project schedule, rather than doing all the logic entry, followed by all the simulation. The latter approach typically results in the students forgetting much of what they learned about AUSSIM simulation due to the time lag between the AUSSIM tutorials and their own use of the AUSSIM simulator. Project documentation, in the form of reports required for the first tutorial project and the final project, is considered a vital part of the course. Some educators have suggested that a good approach to teaching this skill is to let the students use their own format and make sugges-

TABLE I1 EE 357 F A B R I C ~ T S ~T D ~ UDtSlCiNS ~ ~ T

AYNllmbPr
AV-1 AV-2 AV-3 AV-4 AV-5 AV-6 AV-7 AV-8 AV-9 AV-10

T i t L e
VLSI: Technical and Educational Opportunities (B. Hwfflinger) VLSl Implementation ol a Fast Rank Order Filter Algorithm (R.G. Harber) Introduction to VLSl Design Methodologies (C.W. Neudeck) VLSl Design Organization (C.W Neudeck) Expert Systems Approaches to Design lor Testability (M.A. Samad) Design lor Testability (T. Storey) Level Sensitive Scan Design Rules (T. S ~ o r e y ) Lee's Algorithm: A Mare Runner lor Automatic Routing (S.C. Bass) A Pipelined Sorting Algorithm (S.C. Bass) MVISA's Role in the Personal Arryhthmia Monitor (A. Gutierrez)

1. e n e t h l m l n l b 60 26
30 30

none
none
yes

yes
none

28 60
46 55 45

Y"1

yes
none
none

22

none

tions only after the students have made a first, usually unsuccessful attempt [SI. We have taken a different approach: the students are given a highly detailed outline describing exactly what is required in each report.' Students are also given the grading form for the reports so they are aware of the critical points in the grading. This approach has two advantages: the students are exposed to a good example of project documentation through their use of the outline, and the uniformity of the format used in reports helps in making the grading fair and reasonably fast. In addition, students are required to submit certain sections in the outline that comprise a proposal for their final project. This proposal allows the instructor to evaluate the student's choice of design project early in the semester, give advice on any necessary changes, monitor progress on the final design, and ensure that rigorous testing of the design is performed to guarantee complete functionality. Both proposals and reports must be generated on a computer. This facilitates proofreading and allows students to quickly incorporate changes necessary to their proposal as the final design project progresses. By the end of the semester, the students already have 75 percent of their final report completed in the form of revised sections of the proposal. These reports also contain the documentation required for chip fabrication by IBM. The flow of events in the class schedule is given in Fig. 4. This schedule evolved out of two previous schedules which were used in the first two years of the course. During the discussion on the evolution of the course, reference will be made to Fig. 5, which shows the results of student responses to survey questions given at the end of each semcster. The responses to three question relating to the overall class rating, understanding of lab procedures, and assignment length and complexity were averaged for all students for each semester. The data points for the regular semesters are joined together; the overall class rating
'This is not an unrealistic approach. Requests for proposals often require a specific format.

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Week 1 2 3
4

Scheduled Events LAB LAB CKPT LAB CKPT LECT LAB CKPT DUE LAB RETURN LAB DUE LAB DUE LAB DUE LAB Kevboard Scanner Loeic Entry Tutorial Keyboard Scanner Simulation Tutorial and Editor Logic Entry In-depth Simulation Tutorial Design of Keyboard Scanner Circuitry Group Projects - Individual Group Meetings with Instructor Logic Entry for Keyboard Scanner Keyboard Scanner Simulation Project Proposal Sections I, 11, 111, IV: lntro (1st Draft) Keyboard Scanner Simulation Project Proposal Sections I, 11, 111, IV: Intro (1st Draft) Kevboard Scanner Simulation Project Proposal Section V: Design (1st level blocks only) Keyboard Scanner Physical Design Keyboard Scanner Report In Class Project Design Project Proposal Section V: Design (All blocks) Project Proposal Section I , II, 111, IV: Intro (2nd Draft) Final Project Project Proposal Section VII: TestingjTimeline Final Project Final Project Adherence t o Droiect timeline #1 Final Project Final Project Adherence t o project timeline #2 Final Proiect Final Project Report Lab Practical

l6
7 8 9

10

I I

DUE LAB LAB CKPT LAB LAB CKPT LAB DUE LAB

11

12 13
14

15

Fig. 4 . Flow of events in EE 357 class schedule.

complexity

2'5

t
Fig. 5 . EE 357 student survey results.

data points for the summer course are placed on a separate curve, as the course schedule is different during the summers. The vertical scale goes from one to five: one is strongly negative, two is negative, three is neutral, four is positive, and five is strongly positive. The first course schedule consisted of three projects. A very simple design, consisting of a two-bit up/down counter, was employed as an example in three short tutorials on logic entry, simulation, and physical design. All steps in each process were shown in the tutorials. The next project was intermediate in size, and the requirements for the design were given to the students. They were required to do the logic design, and then the three steps in design once again, logic entry, simulation, and physical design. The third project was then the final project of their own choosing. The idea behind this format was that the students would be thoroughly familiar with all MVISA procedures, and could use it effectively. The drawback was that the first two projects used up much of the semester, leaving little time for the final project. In addition, students expressed great dissatisfaction with the IBM manuals, and the level of expertise in the student use of the AUSSIM simulator was not high. By the Fall of 1986, several factors had changed since the course was first introduced. The instructors themselves had become very familiar with the MVISA system and the IBM computing environment, many of the software problems associated with system startup had been brought under control, and the new manuals and other procedure notes were available. At this point, it seemed natural to make the final student projects more complex and sophisticated, and stress this aspect of design rather than hierarchical design methodology, which emphasizes modularity, partitioning, and hierarchy. Some educators have suggested that the degree of design sophistication, and hence, "realworld" significance, is an important motivational factor [2], [4]. However, we soon learned there are limits to what can be done by undergraduates in a single semester. In the 1987 Spring semester, it was decided to remove the intermediate project and let the students use the simple design to learn MVISA, and apply the remainder of the semester to the final design project. The idea was to encourage bigger and more sophisticated designs by giving students more time for their final project. Unfortunately, the results were not what we had expected. Students used the first four weeks to do the tutorials associated with the simple design and a separate AUSSIM tutorial. They then spent the next two to three weeks deciding on their final projects, with the instructors emphasizing relatively large design projects. The final weeks were spent in logic entry and simulations, but the students had several difficulties. The three-week delay between the introduction to MVISA and their use of it for the final projects caused many of them to forget most of what they learned in the first few weeks. In addition, the lack of an intermediate project which exercised the students' knowledge of digital design

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and MVISA contributed to a lack of understanding of the difficulties involved in the whole process. The ultimate result was great difficulties near the end of the semester for most groups in finishing their projects. As shown in Fig. 5 , the overall class rating fell into the negative range, as did the student opinion of the assignment lengths and complexity. Fig. 5 also show a general trend toward student dissatisfaction with assignment length and complexity, which was partially a result of the instructors pushing the students harder as they themselves become more familiar with the MVISA system. We would expect such a tendency in new design courses. The curve showing lab procedure understanding also fell during this semester, reversing a trend toward improved understanding of lab procedures that had begun when the system was first introduced. This trend was a result of a better understanding of the MVISA system by the TAs, the new manuals developed at Purdue, and the continual refinement of class notes and support materials provided by IBM. The current schedule was developed after reviewing the experience with previous class schedules. It was decided that a good compromise would be to combine the simple and intermediate project into a single intermediate project. The keyboard scanner is the result: students are given the design of the scan generator section and led through the steps needed to enter this logic and simulate it. This corresponds loosely to the simple project. They are given the specifications for the decode logic and keyboard reader blocks, and design, enter, and test this logic themselves. The final step, physical design of the keyboard scanner chip, is performed. The keyboard scanner is designed and tested using the hierarchical design methodology, and the students are immediately immersed in this way of thinking. We also changed the emphasis from design complexity and sophistication to adherence to the hierarchical approach to design and testing. The final projects are simpler, but they are very well structured and provide a better learning experience for the students. Results using this approach were very favorable in the 1987 Summer semester, and as can be seen in Fig. 5, in the 1987 Fall semester, the overall class rating and the lab procedure understanding curves showed significant improvement. From the previous discussion, the goals of EE 357 can be narrowed down to the following: Expose the student to the whole VLSI CAD process, and the different levels present in VLSI design. Teach hierarchical, modular design concepts and favor adherence to these principles as opposed to design complexity and sophistication. Emphasize complete, well-written technical reports and provide a format that the students should follow for their reports. Teach a disciplined, structured approach to testing that includes adherence to a schedule that is developed by the student. Describe design for testability techniques in general and LSSD in particular.

B. Graduute Course Description The graduate course, EE 595M-Automated VLSI Design and Design Algorithms, has two objectives. The first
is to provide students with the experience of designing a large digital VLSI system. The second objective is to acquaint students with the inner workings of the algorithms that commonly support the standard cell and gate array approaches to integrated circuit design. The students in EE 595M work in teams of two, and use the 8 . 0 X 8.0 mm chip image to realize designs of 20 000 or more transistors. The course has been taught once, and the format at that time consisted of two 3 h lab sessions per week. A 30-min lecture was given at the beginning of each lab session covering the CAD algorithms used for automated VLSI design. The remainder of the lab time was used for project design, logic entry, simulation, and physical design (placement and wiring). The students were able to understand and use the MVISA system quite quickly, due to the higher level of engineering expertise found in graduate students, the small class size (eight students), and the fact that several students had taken the undergraduate course using the MVISA system. The course format has been changed to include a 1 h lecture per week, in addition to the two 3 h lab periods, which are now devoted to chip design and implementation. This change was suggested by several students in the first offering of the course, who wanted more focus placed on the design algorithms used by CAD systems. We now describe several designs from the first course offering to give an impression of the level of design complexity and sophistication in the class. These included a 32-bit floating-point multiplier, a chip that emulates the 6502 microprocessor architecture, an implementation of a systolic sorting algorithm [ I O ] , and a chip that implements an eight-bit microprocessor slice. These chips were of considerable complexity, and demonstrated to the students the power of the CAD software in implementing sophisticated designs in a relatively short period of time. For example, the 32-bit pipelined floating-point multiplier was designed to conform to the IEEE 754 standard format for floating-point representations. The chip throughput is 2.5 MFLOPS (million floating-point operations per second) with a 10 MHz clock; the latency before the first result appears is 2 ps. Of a possible 2952 internal cells in the 8.0 X 8.0mm chip image, 2833 were used, and 89 of a possible 178 I/O cells were needed. There were 28 699 transistors in the multiplier chip design. To see where MVISA fits into the graduate curriculum, we briefly mention other graduate courses in VLSI, including EE 588-Integrated Circuit Layout and Design and EE 559-MOS VLSI Design. EE 558 is a project course on the design, layout, evaluation of digital and analog circuits. Layout design rules for bipolar, NMOS, and CMOS technologies are described and studied, and several small-scale and medium-scale IC designs in each

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technology are completed by the students. EE 559 focuses on large-scale MOS integrated circuit design, considering such issues as device fabrication and modeling, useful circuit building blocks, system considerations, and algorithms to accomplish common tasks. In EE 559, students design and implement two large integrated circuits in NMOS and CMOS technologies. Both of these courses focus on the custom design and layout of VLSI; the layout of every transistor and its location on the chip must be described precisely by the chip designer. EE 595M enhances the graduate curriculum by providing a VLSI CAD system that exemplifies the semicustom, standard cellbased approach to VLSI design. Also, students are exposed directly to the algorithms required in placement and wiring, in addition to studying a variety of these algorithms during the lecture period; they gain an understanding of the difficulties, problems, and potential associated with large CAD software systems; and they can concentrate on the system design and architectural issues involved in VLSI design.
C. Discussion

The experience at Purdue of integrating the MVISA system and VLSI CAD into the curriculum has provided information on many of the issues involved in this process. The course materials that must be developed to accelerate the students journey up the learning curve are extensive, and experience usually provides a good guide on what is required. Interactive learning materials seem to work best in this environment. It is useful for the students to complete more than one design in a semester; the mistakes and lessons learned in the first design contribute significantly to the better quality of the second and third. It is more realistic to emphasize design methodology over design complexity given the time constraints of undergraduates. Software and hardware maintenance costs are significant for such systems, and it is best to spread these costs across several course offerings in the VLSI CAD area. This approach has the added advantage of single design environment thread throughout the curriculum. We have attempted to treat the VLSI CAD issues in a generic way as much as possible within the framework of a single system. IV. RESEARCH A N D DEVELOPMENT PROJECTS BY MVISA SUPPORTED Several research and development projects have been supported by the MVISA system at Purdue. Some were funded directly or indirectly by IBM. These include an expert system that adds scan paths to MVISA design automatically, programs to plot student designs on an IBM 7375-1 plotter, a masterimage chip used in the design of a personal arrhythmia monitor, and a translator that generates test vectors for a test workstation using the AUSSIM simulation programs used to test the design before fabrication. DEFT [ 111 is a knowledge-based expert system which accepts as input the description of a circuit that

has been designed without any testability features and modifies it into an easily testable circuit. DEFT was designed to work with the MVISA system; it accepts as input a chip description generated by MVISA, adds hardware and makes other modifications to the circuit, and then returns a modified description of the chip to MVISA. Another research task that was aided by MVISA was the implementation of a pocket-sized electrocardiograph, known by the acronymn PAM (personal arrhythmia monitor) [ 121. The small size of the PAM was made possible by a 4.2 mm integrated circuit designed and simulated via the IBM MVISA facility. The chip performs three major functions: addresddata demultiplexing, key debouncing and prioritizing, and address decoding. Among several development tasks associated with the MVISA system at Purdue was development of software to drive a color plotter. The plotter generates hardcopy plots of the different photoplate levels in a chip physical image. Another project involved developing an integrated simulation and testing package for MVISA. The goal here was to integrate the simulation tools used by the design engineer with the test system, yielding a complete simulation and testing package. The main component of this project is a translator which converts the high-level language description of the simulation into a set of binary vectors which can be used by the DAS tester. These projects serve several purposes: they enhance the labs taught with the MVISA facility, they provide feedback to IBM concerning improvements that could be made to MVISA, and they increase the pool of knowledge and level of expertise at Purdue of those using the system. These projects are particularly useful at the beginning stages of introducing a new CAD system into the curriculum: they provide a means for quickly climbing the learning curve on a the new system, and the pool of experts that result can guide the development of the course and suggest new directions that may be possible. V. SUMMARY This paper has described a case study in the introduction of VLSI CAD into the EE curriculum. The MVISA system has been applied at Purdue in two EE courses, and their structure, philosophy, and goals have been examined. Several lessons learned in this process are spread throughout the paper. The best approach for each issue depends on the circumstances of a particular school. The size of the school and its financial resources, availability of financial support from industry or government, the current curriculum, present computing resources, faculty interests, and many other factors play a part in deciding which options to choose. The case study discussed in this paper highlights many of these issues and describes what decisions were made at Purdue. The goal of introducing VLSI CAD into the curriculum will become even more important as VLSI densities continue to increase in the future, and these tools become indispensable to VLSI design.

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ACKNOWLEDGMENT Numerous individuals have contributed significantly to the, successful introduction of the MVISA system at Purdue. K. Salsburg, R. Alvarodiaz, and C. FerrainoloDworak, all from IBM FSD, Manassas, provided crucial support, especially at the beginning stages of the project. N. Klimavicz and W . Thirtle, also from FSD-Manassas, have continued the tradition of excellent IBM support for student designers and teaching staff. Prof. F. Mowle and Prof. G. Neudeck of the School of EE at Purdue also spent much time and effort on getting the MVISA system to Purdue, and up and running once it was here. Several teaching assistants have contributed significantly to developing the course materials and current schedule. M. Feldman was the principal author of the Circuit Data Book and devised the Keyboard Scanner design and the notes on modular design. P. Subramaniam wrote the CAI programs. C. Hughes helped out on several of these tasks and also evaluated new software and hardware from IBM. S. Everett also helped with the development of the class notes.

John C. Lindenlaub (S60-M62-SM73) received degrees in electrical engineering from the Massachusetts Institute of Technology, Cambridge, and Purdue University, West Lafayette, IN. He is a Professor of Electrical Engineering at Purdue University and teaches i n the area of coniputer engineering. He also serves as Director of instructional development for the department. He is interested in applying the use of electronic technology to engineering education. In the late 1960s. he pioneered the use of audio-tutorial instruction in engineering. He has produced video segments for courses in circuit theory and digital logic design and is currently directing a program in computer-based instruction research which seeks to enhance his departments capability in automated evaluation of student work. electronic submission of assignments, and the incorporation of engineering workstations into the curriculum. Dr. Lindenlaub is a past Chairman of ASEE PIC IV and the ERM Division. He has served as Secretary-Treasurer, Vice-president. and President of the IEEE Education Society and is a frequent participant in ASEE Annual Meetings and Frontiers in Education Conferences. Steven C. Bass (S67-M71) received the B.S.E.E.. M . S . E . E . , and Ph.D. degrees in electrical engineering in 1966, 1968, and 1971, respectively, from Purdue University. West Lafayette. IN. In 197 I , he joined the faculty of the School of Electrical Engineering at Purdue University where he attained the rank of Professor specializing in VLSI circuit design, CAD, and digital signal processing. Together with Prof. L. Jamieson, he was Co-Director of the Schools One-Dimensional Signal Processing Laboratory. He has developed graduate level courses in VLSI design. computer-aided circuit design, and digital signal processing. He has also developed a senior level course on digital filtering. In 1988 he joined the faculty of George Mason University. Fairfax. VA. where he is presently Professor of Electrical and Computer Engineering. He has published approximately 60 technical papers and reports in the above areas and has presented his work at conferences in the United States, Canada. and Europe. He has received research grantsicontracts from the Federal Aviation Administration, the U.S. Air Force Rome Air Development Center, Philips Laboratories. the Indiana Corporation for Science and Technology, and the National Science Foundation. He has consulted for a number of companies in the areas of CAD of circuits and digital signal processing. He currently holds two U.S. and five foreign patents in the field of digital signal processing. while one U.S. and one foreign patent are pending. Dr. Bass is a member of the Audio Engineering Society, Eta Kappa Nu electrical engineering honorary society and the Tau Beta Pi engineering honorary society. He is a past editor of Circuits and S w e m s , a bimonthly publication of the lEEE Circuits and Systems Society. During 1980-1981, he served as Chairman of the Societys Technical Committee on Digital Signal Processing. He was also elected to the Administration Committee of the IEEE Circuits and Systems Society for the three-year period 19791981. During 1981 he served as Vice President of this committee. He has organized workshops for the IEEE Solid State Circuits Committee (4. 10) as well as the IEEE-CAS Technical Committee on Digital Signal Processing in the areas of CAD and signal processing. He is currently an Associate O N CIRCUITS A N D SYSTEMS in the Digital Editor of the IEEE TRANSACTIONS Signal Processing area.
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REFERENCES
[ I ] J . W. Gault and W. E. Snyder. An undergraduate design project course using a microcomputer, lEEE Trcins. Educ., vol. E-21. pp. 240-243. Nov. 1978. [2] J . A. Orr and G. E. Stannard, The role of project work in the EE curriculum: Experience at Worcester Polytechnic Institute. IEEE Trcins. Educ., vol. E-22, pp. 99-104, May 1979. [3] J . Law, An electrical engineering undergraduate design course. IEEE Trans. E d u r . , vol. E-22, pp. 138-142. Aug. 1979. [4] R . J . Niederjohn and R . J. Schmitz, The case for project-oriented courses with educationally useful student design projects. IEEE Trans. Educ., vol. E-25, pp. 65-70, May 1982. [5] J. M. Feldman and M. B. Silevitch, Design as a regular component in regular lecture courses-incentives and disincentives. IEEE Trrriis. Educ.. vol. E-28. pp. 85-91, May 1985. [6] W. H. Elder, P. P. Zenewicz, and R. R. Alvarodiaz. An interactive system for VLSI chip design. IBM J . Res. Develop.. vol. 28, pp. 524-536, Sept. 1984. 171 E. M. Seymour, K. A. Salsburg. D. Landis. and G . Sobelman. IBM VLSI academic program. in Proc. 7rh Bieniiiul (in;\,. /Gov./Ind. Microelectron. Syinp. Rochester, NY. June 1987, pp. 5-9. 181 R. L. Donze and G. Sporzynski. Masterimage approach to VLSI design, lEEE Coinput. vol. 16. pp. 18-25. Dec. 1983. [9] E. B. Eichelberger and T . W . Williams. A logic design structure for LSI testability, J . Design Auromarion Fault-Toleranr Coinput., vol. 2 , pp. 165-178, May 1978. [IO] G . Miranker, L. Tang, and C . K. Wong. A zero-time VLSI sorter. IBM J . Res. De1,rlop.. vol. 27, pp, 140-148, Mar. 1983. [ I I ] M. A. Samad and J . A. B. Fortes. DEFT-A design for testability expert system,in Proc. ACM-IEEE Fall Joinr Compur. Conf., Dallas, TX, Nov. 1986. [ 121 A. Gutierrez, A personal arrythmia monitor, M.S.E.E. thesis, School of Elec. Eng. Purdue Univ.. West Lafayette, I N . Dec. 1986. [ 131 G L / / L m i g u n p Spec<ficarion, IBM Document GE45-I 127-1, Feb. 1985.

Matthew T. OKeefe (S88)was born on January 22. 1962. He received the B.S.E.E.E. degree from North Dakota State University. Fargo, in 1985 and the M.S.E.E. from Purdue University. West Lafayette. IN. in 1986. He is currently a Ph.D. student at Purdue. His current research interebts include parallel processing. especially automatic parallelism detection and packaging. VLSl design. combinatorial optiniization. and number theory.

Timothy P. Wahlen received the B.S. degree in physics and the M . S . degree in electrical engineering from Purdue University. West Lafayette. IN. in 1982 and 1985. respectively. He joined IBM in 1985. working i n the Federal Systems Division on VLSI design software and device modeling. While at the Federal Systems Division. he served as the technical coordinator for IBMs VLSI Academic initiative program. He remains at IBM. but is now with the Marketinc and Service Group. and is currently an M.B.A. student at Carnegie-Mellon University, Pittsburgh. PA.