Documente Academic
Documente Profesional
Documente Cultură
• Research:
FPGA, PSoC, embedded systems
Trí tuệ nhân tạo
• Education:
K37 điện tử-ĐHBK Hà nội (1997)
Master về trí tuệ nhân tạo 1999, Đại học K.U. Leuven,
vương quốc Bỉ
Đề tài: Nhận dạng chữ viết tay
Tiến sỹ kỹ thuật chuyên ngành điện tử-tin học, 9/ 2004, Đại
học K.U. Leuven, Vương Quốc Bỉ
Đề tài: quản lý chất lượng dịch vụ trong các ứng dụng đa
phương tiện tiên tiến
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Outline
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• Introduction
Definition
Categories of embedded systems
Characteristics of embedded systems
Constraints of embedded systems
Trends
• Embedded hardware
• Embedded software
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Definition
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Definition
*Engine
Performance and
Emission Control
(Traction Control)
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Definition
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Definition
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Characteristics of Embedded
systems
• Part of a larger system
Limited peripherals
• Application-specific
Both hardware and software is tailored to applications,
which are well defined
However, re-programmability is a requirement
• Interaction with the physical world
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Trends
Number of transistors
1M
100K
10K
55%/year
1K
100
10
1 Time
1980 1985 1990 1995 2000 2005
1000 10 1
+ Communications
+ Ambient
Intelligence
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Now + 5 Years
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• Introduction
• Embedded hardware
Overview
Microcontroller
DSP
PSoC
RSoC
• Embedded software
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• Introduction
• Embedded hardware
Overview
Microcontroller
DSP
PSoC
RSoC
• Embedded software
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• New trend:
System-On-Chip (SOC)
Usual (or desired) specs:
32-bit RISC CPU
Built-in interfaces to RAM and ROM
Built-in DMA, interrupt and timing controllers
Built-in interfaces to disk or flash memory
Built-in Ethernet/802.11 interfaces
Built-in LCD/CRT interfaces
New SOCs appearing almost every week!
Examples
Intel StrongARM SA-1110
Motorola PowerPC MPC823e
NEC VR4181
Many, many more
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• New trend:
Reconfigurable System-On-Chip (RSOC)
Processor core + (re)Programable logic
E.g. FPGAs
Changing the system behavior at the hardware level
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50 GIPS-500GOPS
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gps RF / Analog
• Flexibility Voice
Pen
Vision
Bio
200MHz
< Watt
Reconfigurable interconnect Display
Motion Sound
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• Introduction
• Embedded hardware
Overview
Microcontroller
DSP
PSoC
RSoC
• Embedded software
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Microcontrollers
• Vi điều khiển = CPU + Bộ nhớ + các khối ghép nối ngoại vi +
các khối chức năng
EEPROM
RAM
ADC/DAC
Timer
Bộ tạo xung nhịp
PWM
UART
USB
...
• Word length
4 bit: 2%
8 bit: 36%
16 bit: 25%
32 bit: 34%
64 bit: 3%
• Not pushing the limits of performance for cost reasons
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Microcontroller facts
• Shipments- > 8 Billion in 2000, 8 bit > 1/2 market
• Major Players: Microchip 16Fxx, Intel 8051, Motorola
MC68HC05, National COP800, SGS/Thomson ST62, Zilog
Z86Cxx
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PIC16C5x
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PIC16C5x
• High-Performance RISC CPU:
Only 33 single word instructions to learn
All instructions are single cycle (200 ns) except for
program branches which are two-cycle
Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
12-bit wide instructions
8-bit wide data path
Seven or eight special function hardware registers
Two-level deep hardware stack
Direct, indirect and relative addressing modes for
data and instructions
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PIC16C5x
• Peripheral Features:
8-bit real time clock/counter (TMR0) with 8-bit
programmable prescaler
Power-On Reset (POR)
Device Reset Timer (DRT)
Watchdog Timer (WDT) with its own on-chip
RC oscillator for reliable operation
Programmable code-protection
Power saving SLEEP mode
• Applications:
high-speed automotive and appliance motor control
low-power remote ransmitters/receivers
pointing devices and telecom processors.
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Motorola MC68331
32 bit 16
2 Timers
integer CPU data
1 Serial asynch. FT unit: watchdog 24
Buffered I/O clock&bus monitor address
12
Programmable
chip selects
7
Interrupt logic
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Motorola MC68332
32 bit 16
Timer PU
integer CPU data
1 Serial asynch. FT unit: watchdog 24
Buffered I/O clock&bus monitor address
12
Programmable
2 Kbyte RAM
chip selects
7
Interrupt logic
≤ 48
Parallel I/O
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Motorola MC68340
32 bit 16
2 Timers
integer CPU data
2 Serial asynch. FT unit: watchdog 32
I/O clock&bus monitor address
4
Programmable 2 channel
chip selects DMA controller
7
Interrupt logic
≤ 16
Parallel I/O
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Motorola MC68HC05
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Motorola MC68HC05
Hardware features
• Fully static design featuring the industry standard M68HC05
family CPU core
• On chip crystal oscillator with divide by 2 or a software
selectable divide by 32 option (SLOW
mode)
• 2.1 MHz internal operating frequency at 5V; 1.0 MHz at 3V
• High speed version available
• 176 bytes of RAM
• 5936 bytes of user ROM plus 14 bytes of user vectors
• 256 bytes of byte erasable EEPROM with internal charge pump
and security bit
• Write/erase protect bit for 224 of the 256 bytes EEPROM
• Self test/bootstrap mode
• Power saving STOP, WAIT and SLOW modes
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Motorola MC68HC05
• Three 8-bit parallel I/O ports and one 8-bit input-only port
• Software option available to output the internal E-clock to port pin
PC2
• 16-bit timer with 2 input captures and 2 output compares
• Computer operating properly (COP) watchdog timer
• Serial communications interface system (SCI) with independent
transmitter/receiver baud rate
selection; receiver wake-up function for use in multi-receiver systems
• 8 channel A/D converter
• 2 pulse length modulation systems which can be used as D/A
converters
• One interrupt request input plus 4 on-board hardware interrupt
sources
• Available in 52-pin plastic leaded chip carrier (PLCC), 64-pin quad flat
pack (QFP) and 56-pin
shrink dual in line (SDIP) packages
• Complete development system support available using the MMDS05
development station with
the M68HC05B32EM emulation module
•37 Extended operating temperature range of -40 to +125 °C
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MCS-51
• 8051 thuộc họ vi điều khiển MCS-51.
• MCS-51 được phát triển bởi Intel và các nhà sản
xuất khác (như Siemens, Philips) là các nhà cung
cấp đứng thứ hai của họ này.
• Tóm tắt một số đặc điểm chính của họ 8051:
4K bytes ROM trong
128 bytes RAM trong
4 cổng I/O 8-bit
2 bộ định thời 16 bit
Giao diện nối tiếp
Quản lý được 64K bộ nhớ code bên ngoài
Quản lý được 64K bộ nhớ dữ liệu bên ngoài
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Ram trong
Thanh ghi 128 byte FF
chøc n¨ng ram
®Æc biÖt
80
§iÒu khiÓn Nguån
128 byte 7F
Ng¾t
ng¾t
Trong RAM
00
CPU
128x8 Bé so s¸nh
EEPROM analog
15 ®−êng dÉn
vµo/ra
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• Introduction
• Embedded hardware
Overview
Microcontroller
DSP
PSoC
RSoC
• Embedded software
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Texas Instruments TMS320C20x
Low end consumer Fixed Point
Dual access fixed MAC 16
data RAM 16x16+32->32 data
PROM Selection of 18
peripherals: address
serial comm.,
Loop controller timers,...
I/O
16
data
16
address
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Texas Instruments TMS320C24x
Low end consumer Fixed Point
Dual access fixed MAC 16
data RAM 16x16+32->32 data
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Texas Instruments TMS320C3x
Floating Point
32 bit 32
XRAM
floating add data
32 bit 24
YRAM
floating multiply address
PRAM ACU
I/O
32
Loop controller ACU data
Selection of 24
peripherals: address
serial comm.,
timers, DMA, ...
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Texas Instruments TMS320C4x
Floating Point Message Passing
20 MB/s
32 bit 32
4KByte XRAM
floating add data
32 bit 32
4KByte YRAM
floating multiply address
8 PRAM ACU
32
Loop controller ACU data
12 channel 32
DMA controller Serial link, address
timers
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Texas Instruments TMS320C54xx
High end consumer Fixed Point
Dual access Fixed ALU 32
XRAM 32+32->40 data
Fixed Add 17
YRAM
32+32->40 address
Fixed multiply
PROM
17x17->34 I/O
16
Loop controller Viterbi data
6 channel 16
ACU
DMA controller address
Buffered serial
ACU
links, timers, ...
6 channel 16
ACU
DMA controller address
Buffered serial
ACU
links, timers, ...
2 Kbyte I-cache4
General purpose
4 Kbyte D-cache
RISC processor
Transfer
2 KByte RAM
controller
• Series discontinued; typical app.: video phone, video conferencing,
multimedia workstations
• Introduced: 1995, 50 MHz, 305 pin
• Multiprocessor-on-a-chip; sub-word SIMD for each DSP
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Texas Instruments TMS320C6201
High end Fixed Point
fixed MUL
16KByte D-SRAM External memory
16x16->32
fixed MUL 23
16KByte D-SRAM address
16x16->32
fixed ALU data
16KByte D-SRAM
32+32->40 32
fixed ALU
16KByte D-SRAM
32+32->40
64KByte fixed ALU/branch
P-SRAM/cache 32+32->40
JTAG / clock pump fixed ALU/branch
Host interface
4 channel DMA 32+32->40
Ext. memory integer ACU 17
address
interface 32+32
2 Serial ports integer ACU data
2 Timers 32+32 16
• Series continued; typical app.: modems, multimedia
• 1997, 0.25 µm, 5ML, 352 pin, 200 MHz, 2.5V, 1.9W, $85
• Super scalar (8 Instr./cycle), 1600 MIPS
•
50
VLIW: 256 bit instruction word
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Texas Instruments TMS320C6202
High end Fixed Point
2x16KByte D-RAM fixed MUL
(Shadow load) 16x16->32 External memory
2x16KByte D-RAM fixed MUL 23?
(Shadow load) 16x16->32 address
2x16KByte D-RAM fixed ALU data
(Shadow load) 32+32->40 32
2x16KByte D-RAM fixed ALU
(Shadow load) 32+32->40
2x128KB P-RAM fixed ALU/branch
(Shadow load) 32+32->40
JTAG / clock pump fixed ALU/branch
Expansion bus
4 channel DMA 32+32->40
Ext. memory integer ACU 17?
address
interface 32+32
2 Serial ports integer ACU data
2 Timers 32+32 32
• Series continued; typical app.: modems, multimedia
• 1999, 0.18 µm, 5ML, 352 pin, 250 MHz, 1.8V, 1.9W, $130
• Super scalar (8 Instr./cycle), 2000 MIPS, scales well till 700 MHz
(6000 MIPS)
•
51 Optimum choice when all data fits in on-chip memory
© DHBK 2008
Texas Instruments TMS320C6203
High end Fixed Point
2x64KByte D-RAM fixed MUL
(Shadow load) 16x16->32 External memory
2x64KByte D-RAM fixed MUL 23?
(Shadow load) 16x16->32 address
2x64KByte D-RAM fixed ALU data
(Shadow load) 32+32->40 32
2x64KByte D-RAM fixed ALU
(Shadow load) 32+32->40
256KByte P-RAM fixed ALU/branch
128KB P-cache/RAM 32+32->40
JTAG / clock pump fixed ALU/branch
Expansion bus
4 channel DMA 32+32->40
Ext. memory integer ACU 17?
address
interface 32+32
2 Serial ports integer ACU data
2 Timers 32+32 32
• Series continued; typical app.: base stations
• 2000, 0.15 µm, 5ML, 18 mm2 package size, 300 MHz, 1.5V, 1.5W
• Super scalar (8 Instr./cycle), 2400 MIPS
• Optimum choice when all data fits in on-chip memory
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Texas Instruments TMS320C6211
High end Fixed Point
4KByte L1 Dcache fixed MUL
(2 way set assoc.) 16x16->32 External memory
4KByte L1 Pcache fixed MUL 30
(2 way set assoc.) 16x16->32 address
4x16KByte L2 fixed ALU data
cache (direct map) 32+32->40 32
fixed ALU
32+32->40
fixed ALU/branch
32+32->40
JTAG / clock pump fixed ALU/branch
Host port
16 channel DMA 32+32->40
Ext. memory integer ACU 17
address
interface 32+32
2 Serial ports integer ACU data
2 Timers 32+32 16
• Series continued; typical app.: modems, multimedia
• 1999, 0.18 µm, 5ML, 256 pin, 150 MHz, 1.8V, 1.5W, $25
• VLIW, 1.2 GIPS; cheap (25$ in ‘99, 5$ in ‘01)
• Optimum for random access to large memory space
•
53 80% of performance of C6x with infinite on-chip memory
© DHBK 2008
Texas Instruments TMS320C6416
High end Fixed Point
16 Kbyte L1P fixed MUL
direct mapped 16x16->32 External memory
16 Kbyte L1D fixed MUL 30
2way dual access 16x16->32 address
1 Mbyte RAM/L2 fixed ALU data
4way 32+32->40 64
Dual EMIF & HPI & fixed ALU
PCI & Utopia 32+32->40 30
address
JTAG / clock pump fixed ALU/branch
64 channel DMA 32+32->40 data
3 Serial ports fixed ALU/branch 16
3 Timers 32+32->40 HPI
Viterbi decoder integer ACU ?
accelerator 32+32 address
Turbo decoder integer ACU
data
accelerator 32+32
32
• Samples June 2001, 0.12 µm, 6 LM, 532 pin, 400 MHz-600 MHz, 1.2V,
starts at 95$ in volume
• Super scalar (8 Instr./cycle), 3200-4800 MIPS
• Sub-word (8bit or 16bit) parallelism
•
54 Specialized instr.: Galois Field Mult, bit manipulation
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Texas Instruments TMS320C6701
High end Floating Point
Fixed/Float MUL
16KByte D-SRAM External memory
32x32/64x64
Fixed/Float MUL 23
16KByte D-SRAM address
32x32/64x64
Fixed/Float ALU data
16KByte D-SRAM
32+32/64+64 32
Fixed/Float ALU
16KByte D-SRAM
32+32/64+64
64KByte Fixed ALU/Branch
P-SRAM/cache Float 1/x & √x
JTAG / clock pump Fixed ALU/Branch
Host interface
4 channel DMA Float 1/x & √x
Ext. memory integer ACU 17
address
interface 32+32
Serial interface integer ACU data
2 Timers 32+32 16
• Series continued; typical app.: video compression
• Introduced: 1998, 0.18 µm, 5ML, 352 pin, 167 MHz, 1.8V
• Super scalar (8 Instr./cycle); VLIW; 1 GFLOP
•55 Foreseen for ‘00: 50$ (cf. C6211) & 3 GFLOP (cf. C6202)
© DHBK 2008
Texas Instruments TMS320C6711
High end Floating Point
4KByte L1 Dcache Fixed/Float MUL
(2 way set assoc.) 32x32/64x64 External memory
4KByte L1 Pcache Fixed/Float MUL 23
(2 way set assoc.) 32x32/64x64 address
4x16KByte L2 Fixed/Float ALU data
cache (direct map) 32+32/64+64 32
Fixed/Float ALU
32+32/64+64
Fixed ALU/Branch
Float 1/x & √x
JTAG / clock pump Fixed ALU/Branch
Host interface
4 channel DMA Float 1/x & √x
Ext. memory integer ACU 17
address
interface 32+32
Serial interface integer ACU data
2 Timers 32+32 16
• Series continued; typical app.: video compression
• 2000, 0.18 µm, 5ML, 256 pin, 100 MHz, 1.8V, 2W, $20
• VLIW, 600 MFlops
• Optimum for random access to large memory space
•
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© DHBK 2008
Motorola MC56xxx
Audio Fixed Point
16 or 24 bit 24
XRAM
integer CPU data
YRAM ACU 18
address
PRAM ACU
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Philips VSP-1
Fixed Point Video
12
512x12 bit 12 bit
Memory element integer ALU
512x12 bit 12 bit
Memory element integer ALU
12 bit
10x18 cross-bar
integer ALU 12
10
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Philips VSP-2
Fixed Point Video
12
512x12 bit 12 bit
Memory element1 integer ALU1
512x12 bit 12 bit
Memory element2 integer ALU2
12
512x12 bit 12 bit
Memory element4 integer ALU12
22x50 cross-bar
22
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• Introduction
• Embedded hardware
Overview
Microcontroller
DSP
PSoC
RSoC
• Embedded software
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• PSoC là gì?
Do hãng Cypress sản xuất
Một loại công nghệ IC mới phát triển trong vài năm gần đây.
Khả năng tích hợp động các loại linh kiện số và tương tự để
tạo ra các khối số hoặc tương tự với chức năng tuỳ thuộc
người dùng.
Kết hợp với một vi điều khiển trung tâm.
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Ứng dụng
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Tài
nguyên
hệ
thống
Chọn Hướng
linh dẫn sử
kiện dụng
linh
kiện
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Thiết kế
Thông
số
chung
n IC
S
BU
Thông
Châ
số linh
Số
kiện
Tương tự
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Lập trình
Quản lý
theo dự
án
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• Introduction
• Embedded hardware
Overview
Microcontroller
DSP
PSoC
RSoC
• Embedded software
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RSoC
• Reconfigurable System-on-Chip
Processor core + (re)Programable logic
E.g. FPGAs
Changing the system behavior at the hardware level
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• Introduction
• Embedded hardware
• Embedded software
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Basic Concepts
Main Features
Timeliness
Concurrency
Embedded Software Liveness
User Input Output
Heterogeneity
Reactivity
Robustness
Low power
Scaleable
Interaction with the physical world
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Basic Concepts
Its principal role is not the transformation of data but rather the interaction
with the physical world
Since it interacts with the physical world must acquire some properties of
the physical world. It takes time. It consumes power. It does not terminate
until it fails
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Basic Concepts–More Challenges
The engineers that write embedded software are rarely computer scientists
The designer of the embedded software should be the person who best
understands the physical world of the application
Therefore, better abstractions are required for the domain expert in order to
do her job
On the other hand, applications become more and more dynamic and their
complexity is growing rapidly
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