Learning FPGA and Verilog A Beginner's Guide

Learning FPGA and Verilog A Beginner's Guide
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Links So far we learned a few things about Verilog and how to create a module in Verilog and run simulation. While simulation can tell us a lot of things about the correctness of our module, nothing like putting it on a piece of hardware and see it working. In this part of the tutorial, I'll walk you through the steps of synthesizing our module and implementing it on hardware. As I mentioned in part 3 of this tutorial, the test bench code is used only for simulation. To synthesize our module, we have to remove the test bench code. For those who don't know, HDL Synthesis is the step where the HDL ( Verilog/VHDL or any other HDL for that matter) is interpreted and an equivalent hardware topology is generated. This hardware topology will be very specific to the target FPGA selected. Synthesis is a very complex process and we don't need to know the internals to get our simple module up running. We have selected to implement our module. This board has a Xilinx Spartan 3A FPGA on board. The exact part number used is XC3S50A-VQ100. This is a 100 pin VQFP chip with 50K gates. See the below image for pinout for this particular FPGA.
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Let's come back to our module and think about how we can implement the same on the hardware. The module in question is a NOT gate. As we know, the output of a NOT gate is always the negation of the input. We can have many possible hardware configurations to test this module. The easiest would be with a switch and a LED. See this hardware configuration in the picture below.
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In the above diagram, a switch is connected to an input which is pulled up to VCC by using a resistor. The output is connected to a LED. Let's take a moment to understand how this circuit is going to behave. When the switch is in open position, there will be a positive voltage ie; a logic 1 at the input (A) of the NOT gate. That means, the output (B) will be at logic 0. So the LED will be in OFF condition. When the switch is closed, the input of NOT gate will become logic 0 and the output will switch to logic 1 state. And the LED will glow. Now we know the basic hardware requirements. We need the following in our prospective hardware. 1. An input capable IO with a pull-up resistor and a switch attached. 2. An output capable IO with an LED attached. Let's take a closer look at the . The following image shows the IOs and peripherals available on Elbert.
As we see in the image above, Elbert has four general purpose push button switches and eight LEDs for the user's convenience. We can now take a look at the and learn a little bit more about where the switches and LEDs are connected. Let's choose push button switch SW0 and LED0 for our purpose. Looking through the schematics revels that SW0 is connected to IP_3 (Pin No. 7) and LED0 is connected to IO_L01P (Pin No. 3) of the AFPGA respectively. Notice that IP_3 is an input only pin. But it will be sufficient for our purpose here. We now have a Verilog module that we want to implement, selected a hardware platform and decided what IOs to use for implementation. Let us revisit our module. I'm reposting the module code here handy.
1. module myModule(A, B); 2. input wire A; 3. output wire B; 4. assign B = !A; 5. endmodule
Our module has two ports. Port A, which shall be an input and Port B, which shall be an output. An attentive reader would be asking now, how are we going to attach Port A to IP_3 (Pin No. 7) of the hardware and Port B
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to IO_L01P (Pin No. 3) of the hardware. We will do this by defining user constraints. User constraints tell the router and the placement logic (which is a part of HDL synthesizer) on which physical pins the module signals are to be connected. We make a list of constraints and place it in a file and include that file in the project. This file is often called a User Constraints File. For Xilinx tools, it is a text file with .ucf extension. Fortunately, the user constraints file for Elbert is already . This file has definitions for all IOs available on Elbert. But we don't need all of them. So I'll remove the unused part and post the required file contents here.
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. # User Constraint File for NOT gate implementation on Elbert # Onboard LEDs NET "LED[0]" LOC = P3; # Push Button Switches. # Internall pull-ups need to be enabled since # there is no pull-up resistor available on board NET "SW0" PULLUP; NET "SW0" LOC = P7;
The content of this file is pretty self explanatory. On line No.4 it says the net LED[0] (net is equivalent to wire/connection in physical circuit) is connected to the physical pin P3. You might have noticed the "NET "SW0" PULLUP" part. This means that the net SW0 needs to be pulled up to VCC. Many of the FPGA IOs have built in pull up resistors available. These resistors can be activated by mentioning it in the user constraints file. That is what exactly this particular line does. At last, on line No. 11 connects the net SW0 to physical IO P7. Well, this still doesn't answer how the ports of our module is going to be connected to the switch and LED. Like I have mentioned before, the ports of a module is equivalant to wires going in and out of the module. That in turn is equivalent to a net. So we can use the port names as net names in the user constraints file. So if we modify above user constraints code for our NOT gate module, it will look something like this.
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.
# User Constraint File for NOT gate implementation on Elbert # Onboard LEDs NET "B"; LOC = P3; # Push Button Switches. # Internall pull-ups need to be enabled since # there is no pull-up resistor available on board NET "A" PULLUP; NET "A" LOC = P7;
Now we have pretty much everything we need to synthesize the design and test it. Open our simulation project in Xilinx ISE Webpack and change the mode to Implementation and add the user constraints file in the project as shown in the picture below. Don't forget to remove the test bench code from the Verilog source file.
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Save project and right click on the module and select "Implement Top Module" from the popup menu. Synthesis may take a few seconds to a minute. And if everything goes right you will see many green circles with a tick mark in the Process view right beneath the Hierarchy view (refer to the image below).
If any item turns yellow that means there is some kind of warning. Warnings are OK for time being. If any item turns red, there is something that went wrong. Please go back and verify all steps. We have successfully synthesized the design. Now it is time to program the output on to the hardware. Our hardware platform Elbert requires the bit file (the final output of synthesis process) to be in raw binary format. But ISE doesn't generate raw binary bit file by default. We can do this by following the steps below.
1. Right click on the Generate Programming File option in Processes window.
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2. Select Process Properties from the popup menu. In the dialog box, check Create Binary Configuration File check box and click Apply.
3. Click OK to close the dialog box. Right click on Generate Programming File option in the process view on the left and select Run. Now you will be able to see a .bin file in the project directory and that file can be directly used for ELBERT configuration. Now download myModule.bin (should be in the project directory if everything goes well) to Elbert Spartan 3A development board. . Once downloading is complete, press the switch SW0 and you should see LED0 light up.
This concludes part 4 of the tutorial. Keep watching for more tutorials with more complex designs.
Ok, we have a module and tools, so let's try to run simulation on the module
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and see if it works as expected. In order to simulate the module, we need to give some input to the module, how we do that? The answer is, we need to create a test bench! The test bench will generate the necessary inputs for the module under analysis (Here mymodule). A test bench is nothing but another Verilog module which generates some signals and feed it to the module under test. During simulation, the test bench should be a top module (top level module) with no I/O ports. But when it comes to implementation on real FPGA, the top module can have I/O ports and test benches wont be the top modules there (we will talk about this in detail later). Here goes the test bench code.
1. module myModule_tb(); 2. wire out; 3. reg clock; 4. 5. always begin 6. #1 clock =!clock; 7. end 8. 9. initial begin 10. //Initialize clock 11. clock = 0; 12. 13. //End simulation 14. #10 15. $finish; 16. end 17. 18. myModule notGate(clock, out); 19. 20. endmodule
Let me break down the test bench code and explain. The test bench is just another module, with no I/O ports as I said. I have created a wire named out and a reg named clock. We will create a clock on reg clock" by periodically inverting it and feed it to the input (port A) of myModule. The wire "out" is connected to the output port (port B) of myModule. The result should appear on the wire out in the simulation. The "always" block is something worth special mention here. As the name implies, "always" block will keep on executing as long as the simulation is running. In real world designs, "always" blocks are a little more complicated with sensitive lists etc.. . But for this simulation, the simplest form of "always" should suffice. I'll discuss this in details in later chapters. In the "always" block the reg clock is inverted after every one time unit delay. The symbol # is a way to specify delay in Verilog. So the always block executes always, and inside the block, clock is inverted continuously so that the waveform on clock looks like a square wave. Remember that # symbol is not a synthesizable element. We have to find some other way if delay needed in our design when we synthesize the code. But it works just fine for simulation. The next block is an initial block. As its name suggest, this block will be executed only once at time t = 0. So anything that we need to initialize should go here. Initial block also is usually used only in test benches. Initial blocks are rarely used in synthesizable code, instead reset logic is created if initialization is required. Then we initialize the reg clock to zero. This is very important. If we dont initialize a register, its value is considered as unknown and no matter how many times an unknown is inverted, the result
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will be unknown itself. So if we leave clock uninitialized, clock wont be generated. The last part of the initial block is the $finish directive. The $finish directive is placed after a 10 time unit delay, this means after simulating the design for 10 time units, stimulator will stop running. All functions start with $ symbol is called tasks. Tasks are merely commands to the simulator, they dont alter the circuit behavior. Last but not the least, the module instantiation. The statement myModule notGate(clock, out) creates an instance of the module myModule with name notGate. You can create as many instances as you want from a module. One really important thing here is the wiring. If you look at the code, you can see the reg clock placed as first parameter and the wire out is placed as second parameter. This literally means that the reg clock is connected to port A of the module instance and wire out is connected to port B of the module instance. Now it is time to run the simulation. Download the complete and save it in to a directory. Follow the steps below to run the simulation in Xilinx ISE Webpack (Images are based on Xilinx ISE Webpack 12.1). 1. Runs ISE Project navigator from the Windows program menu.
2. From the File menu, select "New Project" 3. Name your project and select a directory to save the project and click next (refer the picture below).
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4. Change the project settings as required. You can select the FPGA family and device based on the board you use. For it should be set as in the image below. Click "next" and finish.
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5. Now we have created an empty project in Xilinx ISE Webpack.Now right click on the project ands select "Add source" from the popup menu and select the Verilog file.
6. Now make sure that we are running simulation by selecting "Simulation"
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in design view.
7. Start simulation by right clicking on "ISim" process in the process view and selecting "Run".
8. Now the ISim simulator will start and you will be presented with a simulation waveform like the one below.
Inspect the waveform and make sure that our Verilog module worked as expected. As you can see in the image above, the output is the inverted form of the input clock. This is exactly what we expect from a NOT gate. In part 4 of this tutorial, we will implement this module on a real hardware.
Learning Verilog itself is not difficult task, but creating a good design can
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be. But we focus on simple designs here and I will try my best to explain things as simple as possible. If you had been programming with procedural languages such as C, C++, you will have to make up your mind to understand that not all things happen sequentially in digital world. A lot of things happen parallel too. When I started learning Verilog, I used to write code sequentially as if I was writing a C program. C programs are running on microprocessors, which execute one instruction at a time sequentially. So it is easy to write program in a way how you want things to happen one step at a time. And if you look closely, this is the weak point of microprocessors/microcontrollers. They can do only one thing at a time, one and only one thing. But unlike microprocessors, digital circuits (FPGAs, CPLDs, and ASICs) can do many things at the same time. And you need to learn how to visualize many things happening at the same time in contrast to many things happening at different times in procedural language. Verilog Modules Verilog deals with digital circuits. In Verilog, modules can be considered as a component in digital circuit, as simple as a gate or a complex entity like ALU, memory etc Modules are analogous to classes in C++ in a way that it is self contained and give a finite number of methods (ports) to interact with external world. Modules can be instantiated like classes are instantiated in C++ too. But beware; modules are not 100% similar to classes when it is implemented. A module can be simply represented graphically as a box with a number of ports. the ports can be inputs, outputs or bidirectional. Ports can be single bit or multiple bits in width. The image below represent a module with a few inputs and outputs. The number of inputs and outputs, their width and direction will depend solely on the functionality of the module.
The ports can be inputs or outputs or bidirectional. Basically Verilog is all about creating modules, interconnecting them and managing the timing of interactions. Enough talk, we didnt even write a Hello World program yet. So how do we get our hands dirty with Verilog? Let us design a NOT gate in Verilog, simulate it and test it in a real hardware. A NOT gate (a.k.a an inverter) would be the simplest of all gates. The output of an inverter is always the negation of the input. ie; B = !A, where A is the input and B is the output. Below table summarize the behavior of NOT gate as a truth table.
INPUT A OUTPUT B = NOT A
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INPUT A
OUTPUT B = NOT A
NOT gate can be considered as a module with one input and one output with an internal behavior of B=!A. See the graphical representation of inverter module below.
Let us see how we would represent this in Verilog.
1. module myModule(A, B); 2. input wire A; 3. output wire B; 4. assign B = !A; 5. endmodule
Very simple isn't it ? let us go through each and every line and try to understand what is going on in this bit of code. The name of the module is myModule and is declared using the module keyword. The keyword module in Verilog defines our module (called myModule) and assign two ports to it. Everything that goes in to this module is placed in between module and endmodule keywords. myModule has two ports- each one bit wide. The ports' size or direction is not known at this step. In the two lines, port A and port B are declared as input and output respectively.I'm sure you are curious about what the keyword wire is doing there! Well, in Verilog there are two fundamental data types, wire and reg. There are many other data types like int, real etc But wire and reg plays very important roles in Verilog, that without learning them we cannot progress much. As I mentioned before, knowing a little digital electronics will come handy here. wire is as just like a physical wire that we use to connect two different things electrically. If a potential is applied to one end of a copper
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wire, it will be present on the wire as long as you keep applying the potential. As soon as you remove the input, the potential is gone. This is true for a wire in Verilog also. It will have a particular logic state as long as it is driven by some other entity. If nobody is driving the wire, it will be in unknown state. In Verilog, 'wire' can be used to connect things within a module or between two modules. On the other hand, reg can store a logic state and maintain it until someone changes it (think about a register in a microcontroller). This is similar to a flip-flop. If you put flip-flop in one state, it will remain in that state until somebody changes it. So you can use wire as input or output for a module and reg can be used as output of a module. When wire is used as output, there should be a reg that drives the wire from within the module so that wire will have some meaningful information on it. If reg is used as output, no other mechanism is necessary since it can hold data on its own. Then why myModule has both input and output declared as wires? Good question, the answer is, because the module represents a NOT gate. Gates never store any state. Gates are purely combinational; i.e. its output always depends on the current input. If there is some logic state applied to its input then there will be a corresponding output (B = !A in this case). If no logic state is applied to the input it is considered as unknown state and the output state will also be unknown. And this also implies that to have any useful output from this module, some other entity should be driving its input from somewhere else (keep this in mind, we will touch this subject later when talking about test bench). One more important thing about the above code is the keyword assign. The assign keyword is used to create combinational circuits. Whatever written in the right side of equal sign in the statement will be evaluated and the result will be assigned to the entity on the left side and this happens asynchronously. As soon as any changes happen on the right side, the result will reflect on the left side. If you find it difficult to understand this, you may want to read a little about combinational digital circuits. Now that we have a piece of code, we may want to simulate the code to see if it is working as expected. Simulation, in a broad sense, is the process giving some known input and generating the output. When the output is verified against expected output, it is called verification. There are many tools available for simulation and verification. Here we will be using iSim (part of Xilinx ISE Webpack) for simulation and waveform inspection.
Introduction Learning electronics can be a bit challenging sometimes, but it is real fun if you have a little patience to read, understand and experiment. FPGAs need not be any different. Let us give it a try and see how fast and easily we can learn. To get the best out of this tutorial series, I strongly recommend to download the tools listed at the end of this document and try doing every step as you read along.
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Some time back, I wanted to learn about programming FPGAs. I started googling only to find that there is no tutorial on the web (at least I couldn't find any, maybe it is time to refine my googling skills!) that can get you started with learning an HDL and take you all the way through design, simulation and implementation. There are many tutorials online that will help you learn HDLs, some tutorials tell you how to do simulation, some may tell you about implementation, but no single tutorial that guides you step by step from basics to implementation. I write this tutorial in the hope that it may help our readers to learn Verilog (The HDL I chose to learn first because of its syntax similarity to C), simulate your code and implement it on real hardware. This tutorial expects you to have basic knowledge in Digital Electronics, Familiarity with some programming language (preferably C). This tutorial is not meant be an in-depth study about Verilog or FPGAs or anything, but just a guide to walk you through different basic things you need to know to design a simple digital circuit in Verilog, simulate it and implement it on hardware. We will be using Xilinx ISE for simulation and synthesis. The final design will be programmed to an (below picture) to make sure our code works on real hardware as well.
What is FPGA ? FPGA stands for "Field Programmable Gate Array". As you may guess, FPGA essentially is a huge array of gates which can be programmed and reconfigured anytime anywhere. "Huge array of gates" is an oversimplified description of FPGA. FPGA is indeed much more complex than simple array of gates. But the point is, there are many gates inside the FPGA which can be arbitrarily connected together to make a circuit of your choice. FPGAs are manufactured by companies like Xilinx, Altera, Actel etc.. . FPGAs are fundamentally similar to CPLDs but CPLDs are very small in size and capability compared to FPGA.
What is Verilog? Verilog is a Hardware Description Language (HDL) which can be used to describe digital circuits in a textual manner. We need to write our program for FPGA using an HDL like Verilog (as if you write microcontroller programs in C and Assembly). Before HDLs were popular, engineers used to design everything with schematics. Schematics are wonderfully easy for small designs, but are painfully unmanageable for a large design (think
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about Intel engineers drawing schematics for Pentium, which has millions of gates! it is unacceptably complex). If you have some electronics background, your initial tendency will be to use schematics to realize your design instead of learning a new language (This happened to me, honestly). But learning Verilog is easier than drawing 10 pages of schematic, especially if you have some programming background. VHDL is also another popular HDL used in the industry extensively. Verilog and VHDL share more or less same market popularity, but I chose Verilog since it is easy to learn and it's syntactical similarity to C language. Once you are comfortable with Verilog, it should be easy learn VHDL as well. Want to read more about Verilog? Check out this wiki page ( ) or check this tutorial ( ). What tools do we need? 1. A good text editor (I use 2. Xilinx ISE Webpack (Download at ) for free. Registration required).
3. A good FPGA development board ( is used in the examples here ) 4. (Required only if is used)
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Learning FPGA and Verilog A Beginner's Guide

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