ECE/CS 5720/6720

R.R. Harrison

nMOS transistor top view (layout)

Active Polysilicon Contact Metal drain

gate

source

Layout Examples

ECE/CS 5720/6720

R.R. Harrison

nMOS transistor cross section across channel

drain

gate cross section

Metal

source

polysilicon SiO2

p- substrate

Layout Examples

ECE/CS 5720/6720

R.R. Harrison

nMOS transistor cross section along channel

gate

source

cross section drain

polysilicon Metal SiO2 Metal

n+

n+ p- substrate

Layout Examples

ECE/CS 5720/6720

R.R. Harrison

substrate tie layout and cross section

cross section substrate

Metal

p+ p- substrate

Layout Examples

ECE/CS 5720/6720

R.R. Harrison

pMOS transistor top view (layout)

Active Polysilicon Contact Metal Well

drain

gate

source

well

Layout Examples

ECE/CS 5720/6720

R.R. Harrison

pMOS transistor cross section across channel

drain

gate cross section

source

well

Metal polysilicon SiO2

n- well p- substrate

Layout Examples

ECE/CS 5720/6720

R.R. Harrison

pMOS transistor cross section along channel

gate

cross section drain

well
Metal

source
Metal SiO2

polysilicon Metal

n+

p+

p+

n- well p- substrate

Layout Examples

ECE/CS 5720/6720

R.R. Harrison

poly resistor layout and cross section

Polysilicon Contact Metal

cross section

Metal

polysilicon

Metal

SiO2

p- substrate

Typical resistance: 3-30 /square for heavily doped poly (standard) 120-1200 /square for undoped poly (requires extra dopant block layer)

Layout Examples

ECE/CS 5720/6720

R.R. Harrison

well resistor layout and cross section

Active Contact Metal Well

cross section

Metal

Metal

n+

n+

n- well p- substrate

Typical resistance: 700-1300 /square Note: Resistance increases slightly with voltage due to the widening depletion layer between the n-well and p-substrate! (This is the same effect that leads to pinch off in jFETs.)

Layout Examples

ECE/CS 5720/6720

R.R. Harrison

poly/poly2 capacitor layout and cross section

Polysilicon (poly) Second-layer Polysilicon (poly2) Contact Metal

cross section

Metal

polysilicon

Metal SiO2

SiO2

p- substrate

Typical capacitance: 0.5-0.9 fF/m2 Note: There is also a bottom plate capacitance between the lower poly layer and the substrate that is typically about 10% of the poly/poly2 capacitance.

Layout Examples

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ECE/CS 5720/6720

R.R. Harrison

Example layout nMOS current mirror

in out

ground

Active Polysilicon Contact Metal in out

ground

Layout Examples

11

ECE/CS 5720/6720

R.R. Harrison

Example layout multiple metal layers

Metal3 via2 Metal2 via polysilicon Metal1 SiO2 Metal1 contact n+ n+ p- substrate

Contacts connect bottom-layer metal (metal1) to active (n+ or p+ regions), poly, or poly2. Metal2 can be connected to metal1 using a via. Metal3 can be connected to metal2 using a via2. Thus, if we want to connect metal1 to metal3, we must go through metal2 using a via and a via2. In some processes (including the one we use in this class), vias/contacts may be stacked vertically. In other processes, they must be offset from one another. Neither contacts nor vias should be placed over transistor gates.

Layout Examples

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