An75320 001-75320 PDF

AN75320
Getting Started with PSoC 1

Author: Robert Murphy Associated Project: Yes Associated Part Family: All PSoC 1 Families Software Version: PSoC Designer 5.3 Related Application Notes: For a complete list of the application notes, click here.
Abstract
The PSoC 1 family combines the benefits of an ASIC with the convenience of an off-the-shelf device, but without the limitation of a fixed implementation. This application note describes the capabilities of PSoC 1 devices and the PSoC Designer development environment used to configure and program those devices. Included are introductory projects to help you develop PSoC 1 applications.
Contents
Introduction ....................................................................... 2 What is PSoC? .................................................................. 2 The PSoC Product Portfolio .............................................. 3 Choosing a PSoC 1 Device ............................................... 4 PSoC 1 Feature Set .......................................................... 4 M8C Processor ............................................................. 4 Digital Subsystem.............................................................. 5 Digital Basic Blocks (DBBs).......................................... 5 Digital Communication Blocks (DCBs) ......................... 5 Digital Routing in PSoC 1 ............................................. 5 Auto Routing................................................................. 8 Logic Lookup Table (LUT) ............................................ 8 Clocking System ............................................................... 9 Phase-Locked Loop (PLL) ............................................ 9 Slow IMO (SLIMO) ....................................................... 9 Analog Subsystem ............................................................ 9 Continuous Time (CT) Blocks ..................................... 10 Switched Capacitor (SC) Blocks ................................. 10 Analog Routing in PSoC 1 .......................................... 11 Differences with the CY8C28xxx Parts ....................... 12 Analog Routing Considerations .................................. 13 I/O System ...................................................................... 14 CapSense ....................................................................... 15 PSoC System Resources ................................................ 16 Switch Mode Pump (SMP) ......................................... 16 Multiply Accumulate (MAC) ........................................ 16 Dedicated I2C Hardware ............................................ 17 PSoC Designer IDE......................................................... 17 PSoC Designer Layout .................................................... 18 PSoC Designer Code Editor ........................................ 20 PSoC Designer Compilers ........................................... 21 PSoC Designer Debugging .......................................... 21 Debugging in PSoC Designer .................................... 22 Programming................................................................... 22 PSoC Programmer ..................................................... 22 Programming Hardware .................................................. 23 MiniProg1 ................................................................... 23 MiniProg3 ................................................................... 23 CY3215A-DK .............................................................. 23 CY3207-ISSP ............................................................. 23 Third-Party Programmers ........................................... 23 Other Programming Methods ..................................... 23 Available Resources ....................................................... 24 For Engineers Just Getting Started ............................ 24 For Engineers Seeking More ...................................... 25 My First PSoC 1 Design .................................................. 26 About the Design ........................................................ 26 Creating My First PSoC 1 Design .............................. 26 Setting Up the CY3210-PSoCEval1 Board ..................... 30 Setting Up the CY8CKIT-001 Board................................ 30 Summary ......................................................................... 31 Compiled Application Notes List...................................... 32 Worldwide Sales and Design Support ............................. 34
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Document No. 001-75320 Rev. *B
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Getting Started with PSoC 1 ________________________________________________________________________________________________________________
Introduction
Cypresss Programmable System-on-Chip (PSoC) integrates a microcontroller with programmable analog and digital peripherals. Because you can configure the resources of a PSoC, you can develop a device that is customized and tuned for your application. Moreover, as the needs of the application change during development and in production, you can reconfigure the device to adapt to these new requirements with minimal effort.
act as a blank slate with the potential to be configured as a variety of peripherals. Additionally, you can route these configured peripherals to multiple pin locations on the device, providing flexible routing and eliminating the use of dedicated fixed function pins. Figure 2 shows a block diagram of PSoC 1. Figure 2. Block Diagram of PSoC 1
General I/O General I/O
General I/O
What is PSoC?
A typical off-the-shelf microcontroller comes with a fixed peripheral set, including ADCs or ADC channels, timers, and specific communication blocks, such as I2C, SPI, or UART, as shown in Figure 1. Figure 1. Block Diagram of Typical MCU
General I/O
Digital System
System Interconnect
General I/O
General I/O
M8C Processor
System Interconnect
Analog I/O
Analog I/O
Analog System
The disadvantage of this methodology is that it requires the developer to know what the design will look like before the design work begins. Additionally, the fixed number of resources and static pin placement put extreme limitations on the design. For example, UART signals can be present only on two fixed pins, which the semiconductor manufacturer chooses. The design may require two DACs when the part chosen contains only one DAC. You may incur unnecessary cost to incorporate the new requirements. However, PSoC 1 distinguishes itself from the typical MCU by its flexibility; no PSoC design is set in stone. In the real world, design specifications change constantly. PSoC allows those new specifications to be implemented quickly. New specs may take the form of a parameter adjustment, such as the duty cycle of a PWM or an additional ADC to monitor external sensors. This is made possible through an array of programmable analog and digital resources on each PSoC device. These resources
Typically, when you create a hardware application, you need to have an idea of what the end application will look like so that you can choose the part with the appropriate resources. However, PSoC lets you start a design without knowing the end product and then add resources as needed. As long as the digital or analog resources are available, you can adjust, adapt, and grow. Even in instances where the resources have been consumed in a design, PSoC can be dynamically reconfigured during run time to perform a different function. Take, for example, a soda machine. All day, it performs tasks such as I/O for buttons, counting money, keeping track of inventory, and controlling temperature. At night, PSoC can reconfigure itself as a modem to communicate the machines status and inventory to the headquarters of the soda company. The beauty of PSoC is that these analog and digital blocks can be configured to be just about anything. The digital blocks can implement timers, counters, PWMs, UART, SPI, IrDA, and so forth. The analog blocks can implement ADCs, DACs, filters, amplifiers, comparators, and so forth. All of those components can be added as needed. Because of its configurable analog and digital resources, a single PSoC 1 device can replace multiple part numbers that a competing semiconductor manufacturer offers. Figure 3 shows an example of one device that is configured in two different ways.
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Getting Started with PSoC 1 ________________________________________________________________________________________________________________
Figure 3. Block Diagram of PSoC 1 Showing Configurability
The PSoC Product Portfolio

PSoC 1 is the first PSoC family. Additional product families have since been created, including PSoC 3 and PSoC 5. In general, the differences among PSoC families (PSoC 1, PSoC 3, and PSoC 5) are characterized primarily by their subsystem features. Specifically, the digital and analog, quantity, performance, functionality and configurability all are scalable. There are also differences in the switch capacitor hardware architecture, which we will discuss later. Additionally, each device contains a different processor core. In addition to the performance differences, each device family has some features and capabilities that the other PSoC devices do not have. For example, PSoC 1 can implement low-pass filters (LPFs) and band pass filters (BPFs) with analog resources, while PSoC 3 and PSoC 5 cannot. PSoC 5 contains a dedicated SAR ADC, while PSoC 3 and some PSoC 1 devices do not. Other key differences include the following: 1) CPU: PSoC 1 has a 4-MIPS, 8-bit M8C CPU, PSoC 3 has a 33-MIPS, 8-bit single-clock-per-instruction 8051 CPU, and PSoC 5 incorporates a high-performance 100-MIPS 32-bit ARM Cortex M3.
2)
Analog subsystem: PSoC 1 has as many as 12 switched capacitance (SC) and continuous time (CT) blocks, which you can use to implement analog user modules, including analog filters. PSoC 3 has dedicated ADCs, DACs, comparators, and opamps, along with the SC/CT blocks. PSoC 5 incorporates the same analog features of PSoC 3 but adds as many as two additional SAR ADCs. Digital subsystem: PSoC 1 has as many as 16 digital blocks, which can be used to implement digital user modules, including communication protocols. PSoC 3 and PSoC 5 have as many as 24 universal digital blocks (UDBs), which can be used to implement digital components as well as programmable digital logic using Verilog or by using logic gates, such as AND, OR, NOT, or DFF.
3)
As noted earlier, this application note focuses on PSoC 1 devices. To learn more about PSoC 3 devices, refer to www.cypress.com/go/psoc3. Additionally, you can read AN54181: Getting Started with a PSoC 3 Design Project. To learn more about PSoC 5 devices, refer to www.cypress.com/go/psoc5. Both websites, which are the landing pages for their respective PSoC devices, provide information on the device family and how to get started.
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Getting Started with PSoC 1 _________________________________________________________________________________________________________________
Choosing a PSoC 1 Device

As a new user, if you looked at all of the approximately 13 PSoC 1 device options to select a device for an application, you might feel intimidated. In reality, the differences among the parts are large enough to make Table 1. PSoC 1 Device Selector Summary Table
Part Number 29x66 28xxx 27x43 24x94 24x33 24x23/A 23x33 22x45 21x45 21x34 21x23 20xx6/A 20x34/ 20x24 Digital Blocks 16 12 8 4 4 4 4 8 4 4 4 4f 2f Analog Blocks 12 12+4e 12 6 4 6 4 6e 6e 4e 4e 1f 1f Flash (KB) 32 16 16 16 8 4 8 16 8 8 4 32 8 SRAM (Bytes) 2048 1024 256 1024 256 256 256 1024 512 512 256 2048 512 CapSense N Y N Y N N N Y Y Y N Y Y
your selection easier. In fact, if you have a general idea of the flash and RAM required, or certain device features that are needed, picking a part can be easy using the Cypress Product Selector Guide. For a summary of the differences among part families, see Table 1.
USB N N N FS N N N N N N N FS N
SMP Y Y Y N N Y N Y Y Y Y N N
Analog Mux Bus N Y N Y N N N Y Y Y N Y Y
Dedicated SAR N SAR10 N N SAR8 N SAR8 SAR10 SAR10 N N N N
MAC 2 2 1 2 1 1 1 1 1 0 0 0 0
ECO Y Y Y N Y Y Y Y Y N N Y N
FS = Full Speed, SMP = Switch Mode Pump, ECO = External Crystal Oscillator, MAC = Multiply Accumulate
PSoC 1 Feature Set

A broad range of capabilities and a unique feature set distinguish PSoC 1 from the competition and even from other PSoC parts. Let us look at the core features of the device.
For a more detailed diagram, refer to the PSoC Technical Reference Manual. Figure 4. M8C Microcontroller Structure
M8C Processor
The M8C is a Harvard architecture 8-bit RISC single-chip microcontroller, which is capable of up to 4 MIPS. The M8C has 37 instructions. Connected to the M8C processor is the device RAM, which is composed of multiple pages of 256 bytes. Knowing what page of RAM to address is the job of a register called the Page Pointer (STD_PP). Along with RAM, the M8C is connected to the device ROM, which is made up of Supervisory ROM (SROM) and the flash program memory. While the flash is used to retain the application program code, the SROM retains code to perform functions for reading and writing to flash, booting the PSoC device, and reading calibration information. See Figure 4 for a block diagram of the CPU core of PSoC 1.
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Digital Subsystem
The digital subsystem of PSoC is unique because of its programmability and routing systems. Table 1 lists the various PSoC parts along with the number of digital resources. Note that the digital blocks are broken into Digital Basic Blocks (DBBs) and Digital Communication Blocks (DCBs). The number of DBBs and DCBs are always equal in a design. For example, Table 2 shows that a CY8C29xxx device contains 16 digital blocks, eight of which are DBBs and the other eight are DCBs. A block diagram of a digital system with eight digital resources, similar to the CY8C27xxx devices, is shown in Figure 5. Figure 5. PSoC 1 Digital System Block Diagram
Digital Basic Blocks (DBBs)

As the name implies, DBBs are a basic configurable digital resource that can be programmed to function as a timer, counter, or PWM. Each DBB allows you to place an 8-bit resource. Adding a 16-bit, 24-bit, or 32-bit resource requires the consumption of two, three, or four digital blocks, respectively. Fortunately, cascading the 8-bit timers to create a larger digital resource does not require all of the digital blocks to be placed on the same row; they can be spread out over two rows.
Digital Communication Blocks (DCBs)

DCBs not only allow you to place basic digital resources (timer, counter, and PWM), but they also allow you to place communication resources, such as SPI and UARTs. When developing a PSoC 1 design, keep in mind the digital resources. Remember that while DBB components can be placed in DCBs, DCB resources cannot be placed in DBBs.
Digital Routing in PSoC 1

Digital signals in PSoC 1 are routed through a matrix of digital connection lines, as shown in Figure 6. In the center of the figure are four digital blocks (two DBBs and two DCBs). The digital routing capability of each PSoC device varies depending on the number of digital blocks and GPIO count.
Figure 6. Digital System Routing Matrix
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A series of internal connections allows you to route a digital signal from an input pin into the core of the digital subsystem and back out through an output pin. Figure 6 shows a high-level view of the routing diagram for the PSoC 1 digital system. To get a signal into the device, connect an available GPIO pin on the left side of the chip to one of the Global Input columns. The columns are divided into two sections: Global Input Odd and Global Input Even. Only pins on ports with odd numbers (such as Port 1 or Port 3) can connect to the Global Input Odd, and only pins on even port numbers (Such as Port 0 or Port 2) can connect to Global Input Even. There are eight columns for each Global Input group. Some of the Global Input Columns have numbers on top of them, as shown in Figure 7. Use these numbers as a guide to understand all of your options in choosing a pin number to connect to a particular Global Input. For example, on the Global Input Odd column (designated by GIO), GIO 0 connects to Port 1[0] (or Port 3[0]) and GIO 7 connects to Port 1[7] (or Port 3[7). The other pins connect to their respective GIO columns, as shown in Figure 7. Figure 7. Input Pin Connections to Global Input Columns
Figure 8. Row Input Multiplexer
On each Row Input is a multiplexer, which selects a certain Row Input. Understanding which Row Input can connect to each Global Input is shown in Table 2 and Figure 9. Table 2. Row Input to Global Input Connections
Row Input Row 0 Input Row 1 Input Row 2 Input Row 3 Input Global Input Connection Options GIE 0 GIE 1 GIE 2 GIE 3 GIE 4 GIE 5 GIE 6 GIE 7 GIO 0 GIO 1 GIO 2 GIO 3 GIO 4 GIO 5 GIO 6 GIO7
Figure 9. Row Input Multiplexer Connections
The next step in routing is to connect the Global Input columns to the Row Inputs. For each grouping of four digital blocks, there will be four Row Input buses and four Row Output buses. Devices such as the CY8C29xxx family, which contains 16 digital blocks, have a total of 16 Row Inputs and 16 Row Outputs. Each Row Input can connect to one of four Global Input columns, as seen in Figure 8. The Row Inputs also can synchronize the input to the internal main oscillator or let it remain asynchronous.
After a signal is on a Row Input, a digital peripheral can use it in one of two ways: as a clock signal (for example, DBB01 in Figure 10) or as an input signal (example DBB00 in Figure 10). Getting a signal to an output pin is similar to getting it into the device. Each digital resource has two possible outputs, as shown in Figure 10. Each output can connect to any of the Row Outputs. Just as there are four Row Inputs, there are four Row Outputs.
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Figure 10. RI and RO Digital Block Connections
Table 3. Row Output to Global Output Connections

Row Input Row 0 Output Row 1 Output Row 2 Output Row 3 Output Global Input Connection Options GOE 0 GOE 1 GOE 2 GOE 3 GOE 4 GOE 5 GOE 6 GOE 7 GOO 0 GOO 1 GOO 2 GOO 3 GOO 4 GOO 5 GOO 6 GOO7
Figure 13. Single Row Output to Multiple Global Outputs Similar to the Row Inputs, the Row Outputs have multiple connection options, as shown in Figure 11. This allows for flexibility of the digital output routing. Figure 11. Row Output to Global Output Circuitry
A multiplexer in the output circuitry allows the output buffers to be tied directly to a Row Input, as shown in Figure 14. This helps you pass a signal through the PSoC device in a two-layer board, eliminating the need for vias or a multiple-layer PCB. Figure 14. Row Input to Output Pin Connection Connecting a Row Output to a Global Output Column is different. You use an output driver, which is hardwired to a particular Global Output. Each buffer can be individually enabled, as shown in Figure 12. Figure 12. Row Output to Global Output Configuration
Additionally, this allows for a single Row Output to be routed to multiple Global Outputs and then out to pins, as shown in Figure 13 and listed in Table 3.
Another digital routing option available with PSoC is the ability to directly route the signal on a Global Input to a Global Output, and vice-versa. This can be seen in Figure 15. Practical uses include routing an input directly to an output to avoid PCB routing situations, such as the PCB routes being blocked by other traces or wanting to avoid vias. Another practical use is to route an output back to a Global Input Column to feed it back into another digital resource.
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Figure 15. Global to Global Connections
To clear an existing route from a PSoC block output/input to a pin or resource, press Shift and select a block or input of an existing route. PSoC Designer, then, highlights the existing routes and the remaining available outputs, pins, and resources. When you click the destination of an existing route, it is disconnected.
Another multiplexer option allows a single Row Output to be routed to two Row Output interconnects, as shown in Figure 16. Figure 16. Single Row Output for Eight Possible Global Outputs
Logic Lookup Table (LUT)

The PSoC 1 digital subsystem can implement various digital logic functions on the signals located on the Row Inputs and Row Outputs. Referencing Figure 18, the portion of the digital routing that allows you to implement the digital logic is highlighted. This is the same section of the digital routing that allows for a single Row Output to be tied to eight output buffers. For a list of the possible logical operations you can use, see Table 4. Figure 18. PSoC 1 Digital Logic Options
Auto Routing
The previous section discussed how to route a signal manually. This routing can be simplified by using the Auto Routing feature, which is available from PSoC Designer 5.3 and later versions. This feature allows you to connect block inputs and outputs directly to pins and other resources without manual routing. To route a signal from a block output or input to a pin or a resource, press Shift and select a source (point A) and destination (point B) of the route. When you click the source route, the PSoC Designer engine finds all possible routes for a chosen point and highlights the destination of the routes as shown in Figure 17. When you click the destination, the route is complete. Figure 17. Possible Routes for a Chosen Point
Table 4. PSoC 1 Digital Logic Options

PSoC 1 Digital LUT Selection Logic A B ~A ~B A AND B ~A AND B A AND ~B A OR B A NOR B A OR ~B ~A OR B A XOR B A XNOR B TRUE FALSE
Point A
In Table 4, A refers to Row Output n, where n is the Row Output number, which will be between 0 and 3. B refers to Row Output n+1, where n is the Row Output number of A. Since there are only four Row Outputs, if n exceeds 3, then it rolls back over to 0. For example, if A was Row Output 0, then B would be Row Output 1. In the example of A as Row Output 3, then B would be Row Output 0.
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Clocking System
PSoC includes an advanced clocking system with multiple clock sources, many of which are programmable. Main clock sources can be derived from either the internal 24-MHz internal main oscillator (IMO) or an external clock source of up to 24 MHz. In addition, for a low-speed oscillator, use either a 32-kHz oscillator circuit or an internal low-speed oscillator (ILO). See Table 5 for a list of digital clocks used in PSoC 1, along with a brief description of each. For more information on clocks available in PSoC 1, refer to AN32200 - PSoC 1 - Clocks and Global Resources. Table 5. PSoC 1 Digital Clock Options
Clock Signal SYSCLKX2 SYSCLK CPUCLK Description Twice the frequency of SYSCLK. Either the output of the IMO or a clock input on the EXTCLK pin. SYSCLK is divided down to one of eight possible frequencies, to create CPUCLK, which determines the speed of the M8C. SYSCLK is divided down to create Variable Clock 1 (VC1). Division range is 1 to 16. VC1 is divided down to create Variable Clock 2 (VC2). Division range is 1 to 16. Divides down SYSCLK, VC1, VC2, or SYSCLKX2 to create Variable Clock 3 (VC3). Division range is 1 to 256. Either the output of the internal low-speed oscillator or the output of the external crystal oscillator. The internally generated 24-MHz clock by the IMO. The IMO may be put into a slow mode using the SLIMO bit, which changes the speed of the IMO and the CLK24M to either 6 MHz or 12 MHz in some PSoC devices. One of four sleep intervals may be selected, ranging from 1.95 ms to 1 second.
Figure 19. PSoC 1 Digital Clock Tree
Phase-Locked Loop (PLL)

PSoC lets you use a phase-locked loop (PLL) to generate a system clock with high accuracy. To take advantage of the PLL, an external 32-kHz XTAL circuit is required. The result of using the PLL is a main oscillator with a 0.001 percent error in frequency, depending on the crystal used, at the cost of increased power consumption. That compares with a 2.5 percent error in frequency when not using the PLL.
VC1 VC2 VC3
CLK32K
Slow IMO (SLIMO)

To reduce power consumption, PSoC has a low-poweroscillator capability known as the SLIMO, or slow IMO. This mode allows the IMO to operate at 12 MHz or 6 MHz, depending on the device being used, rather than the default 24 MHz. The benefit of using SLIMO is reduced power consumption.
CLK24M
SLEEP
Figure 19 shows a diagram of the clocking tree in PSoC 1 from a higher-level perspective. Observe how many clocks are derived from the main clock sources.
Analog Subsystem
The analog subsystem of PSoC 1 is unlike anything you will ever see in another embedded microcontroller device. The subsystem is composed of analog blocks arranged in a column configuration. These analog blocks are either continuous time (CT) or switch capacitor (SC) blocks. Figure 20 shows a block diagram of the analog subsystem on PSoC 1. Notice how the blocks are stacked in columns, with CT denoting a Continuous Time block and SC denoting a Switched Capacitor block.
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Figure 20. PSoC 1 Analog System Block Diagram
value of the resistor is dependent on CA and frequency of the switching by using Equation 1. Figure 21. Switched Capacitor Model
1 Vin CA 2 Vout
Equation 1. Calculating Resistance from Switch Cap
Continuous Time (CT) Blocks

The CT blocks inside PSoC are programmable analog blocks that you can configure as comparators or programmable gain amplifiers. The CT blocks are built around low-noise and low-offset opamps. The key to the configurability is the number of analog multiplexers in the block. These multiplexers are controlled by registers, and how they are configured will adjust the topology of the block to create various peripherals. Additionally, a series of resistor strings in the feedback path of the block provide gain in certain components. These blocks are denoted by ACBx, where x is a number, in PSoC Designer. For more information on the structure and composition of CT blocks, refer to Chapter 22 of the PSoC 1 Technical Reference Manual.
The idea of the charge transfer can be used to approximate many circuits depending on how the phases are controlled. For example, you can create an integrator, differentiator, delta-sigma modulator, and more. Figure 22 shows an example where switched capacitors are used with an opamp to create an integrator. Figure 22. SC-Based Integrator Circuit
f1
CF
f2
CA Vin
f1 f2
Vout
Sign
Switched Capacitor (SC) Blocks

The SC blocks truly make PSoC unique among its competitors. Similar to CT blocks, SC blocks are built around low-noise, low-offset opamps surrounded by analog multiplexers. These blocks are unique because the surrounding opamps and multiplexers are groups of capacitors and switches. There is no resistor array, as there are in the CT blocks. The reason this methodology is beneficial is not complicated. Using Figure 21 as a reference, if various switches are put into a static opened or closed state, then the result is a capacitor attached to the circuit. However, if the switches 1 and 2 are opening and closing alternatively at a certain frequency, then the switched capacitor begins to behave like a lossless resistor. The
By using switched capacitors, PSoC can implement filters, DACs, ADCs, integrators, and differentiators in a design, internal to the PSoC device. SC block architectures differ by PSoC device. These blocks are denoted by ASA, ASB, ASC, or ASD in PSoC Designer, and the letters A, B, C, and D refer to the architecture of the SC block. For additional information on SC block architectures, refer to Chapter 23 of the PSoC 1 Technical Reference Manual. Additional information can also be found in AN2041 Understanding PSoC 1 Switch Capacitor Analog Blocks and AN2168 PSoC 1 Understanding Switched Capacitor Filters.
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Analog Routing in PSoC 1

When you study the analog routing for the PSoC 1 devices, you might be intimidated by all of the columns and muxes present, as shown in Figure 23. However, after you understand the basics of the analog routing, what appeared confusing is actually simple and versatile. To begin, let us look at the different components of the analog routing system. Figure 23. Analog System Routing Matrix in PSoC Designer
1 . An a l o g C o l u m n C l o c k S e l e c t The Analog Column Clock Select is a configurable mux used to select the clock source that will be distributed to a specific analog column. Each column has an individual Analog Column Clock select, which allows the choice between VC1, VC2, and the Analog Clock Selects. 2 . An a l o g C l o c k S e l e c t The Analog Clock Select is a configurable mux that lets you select from multiple clocking options for the analog resources. Clocks that pass though this mux are generated by the digital subsystem (Digital Basic Blocks and Digital Communication Blocks). For example, you may
want to use a PWM to generate a clock source to configure an ADC for a desired sample rate. The output of the Analog Clock Select feeds into the input Analog Column Clock Select. 3 . An a l o g C o l u m n I n p u t M u x The Analog Column Input is a configurable mux used to select an analog input pin for a particular column. Notice that in Figure 23 there are two analog columns. As a result, there are two Analog Column Input muxes: one analog input pin for each analog column. Devices that have more than two analog columns also have additional input muxes.
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Each PSoC 1 device has a set of GPIOs that supports analog input. To find the appropriate pins, consult the device datasheet. Looking at the device pinout diagrams, you can expect to see an A if the pin has a direct connection to the analog subsystem. Additionally, following the A, you will see an I denoting an analog input, and/or an O denoting an analog output. An example is shown in Figure 24. Figure 24. Identifying Analog Pins on Device
6. Comparator Bus Each analog column has a dedicated comparator bus associated with it. Every analog PSoC block has a comparator output that can drive this bus. However, only one analog block in a column can actively drive the comparator bus for a column at any one time. The output on the comparator bus drives into the digital blocks as a data input. It also serves as an input to the decimator, as an interrupt input, and is available as read only data in the Analog Comparator Control register (CMP_CR0). 7 . An a l o g O u t p u t B u s The Analog Output Bus is internal and can route an analog signal out to an analog I/O pin using one of the analog buffers, which can source 40 mA of current.
Differences with the CY8C28xxx Parts

The CY8C28xxx family of PSoC 1 devices has a different analog system than the one seen in Figure 23. While the CY8C28xxx does contain multiple analog columns and a combination of CT/SC blocks, it also includes Type-E analog blocks. Those blocks offer dual-channel capacitive touch-sensing capabilities, comparators with programmable DAC references, or up to 10-bit singleslope ADCs. The Type-E analog blocks provide limited functionality; they cannot perform the same functions of the other analog CT and SC blocks. Figure 25 and Figure 26 show the positioning of these Type-E analog blocks in a CY8C28xxx device, along with a four-column traditional analog system. Notice there are ACE blocks, which are a CT type of block, and ASE blocks, which are a SC type of block. On these devices, the Type-E blocks comparator outputs can connect to the Global Input Bus, instead of to the Global Output Bus. Figure 25. CY8C28xxx Analog Subsystem
4 . An a l o g M u x B u s S w i t c h The Analog Mux Bus Switch is a simple two-input mux that lets you choose between the input from the Analog Column Input Mux or an Analog Mux Bus. Referring back to Figure 6 in the digital subsystem section, the Analog Mux Bus allows all I/Os on a device to connect to a common internal analog bus. The analog mux bus is useful for applications in which an ADC needs to measure multiple channels across multiple analog I/Os. The analog mux bus provides a centralized and direct connection of the I/O to the analog columns. Refer to Table 1 to see a list of devices that supports an analog mux bus. 5 . An a l o g C o l u m n I n p u t S e l e c t The Analog Column Input Select is a configurable mux that allows you to choose between the input signal of an adjacent analog column and the input signal from an analog I/O. Using Figure 23 as an example, note there are two inputs into the Analog Column Input Select. One connects to the Analog Column 2 Input Mux and the other input connects to Analog Column 1 Input Mux. In a practical example, pretend that P0[0] was routed to Analog Column 1. The Analog Column Input Select will allow P0[0] also to be routed to Analog Column 2.
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Figure 26. Close-up of Type-E Analog Blocks
Analog Routing Considerations

Although the analog routing system of PSoC 1 is flexible, take care when placing analog peripherals. While the analog subsystem can accept inputs from a variety of analog inputs, analog buffers can connect only to certain pins, and analog blocks can connect only to certain blocks. The routing methodology is shown in Figure 27. For more information on analog routing on PSoC 1, refer to the application note, AN74170 PSoC 1 Analog Structure and Configuration with PSoC Designer.
Figure 27. Analog Routing of PSoC 1

Analog Buffers GPIOs P0[7] P0[4] P0[5]
ACI0[1:0] ACM0 ACI1[1:0] ACM1 ACI2[1:0] ACM2 ACI3[1:0] ACM3
GPIOs P0[6]
Analog Buffers
Array Input Configuration
P0[2]
P0[3] P0[0]
ACOL1MUX AC1 AC2 ACOL2MUX
P0[1] ACB00 P2[3] ASC10 P2[1] ASD20

Analog Column 0
Array
ACB01 ASD11 ASC21
Analog Column 1
ACB02 ASC12 ASD22

Analog Column 2
ACB03 ASD13 ASC23

Analog Column 3
RefIn
P2[6]
AGNDIn
P2[4]
P2[2]
P2[0]
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I/O System
The I/O system of a microcontroller device is critical. After all, it is how you interface with the outside world to get information in and out of the device. In PSoC, because you can configure the I/O to perform a variety of functions, you need a versatile system behind it. PSoC must support anything required of the GPIO, whether the pins are an analog/digital input or analog/digital output. Additionally, any special pin configurability options, such as internal pull-up or pull-down resistors, need to be available whenever the application calls for it. Each GPIO, when used as a digital I/O, can source 10 mA per pin and can sink 25 mA per pin. In total, the device is capable of sinking 200 mA, with 100 mA per side. That means that the even number pins on any port can handle a total of 100 mA, and the odd number pins on any port can handle an additional 100 mA. Additionally, the device can source a total of 80 mA, or 40 mA per side. For an example, see Figure 28 and Figure 29. Figure 28. Identifying Pin Sides on Two-Sided Package
To properly use the GPIO on PSOC 1, you need to understand it and its capabilities. The structure of a GPIO pin on PSoC 1 is shown in Figure 30, with input and output paths. Note that not all I/O pins on PSoC have this layout. While all pins have the digital system, only some pins have the analog input path, while others may have the analog output path. For the functionality details of specific I/Os, refer to the PSoC device datasheet. Figure 30. PSoC 1 GPIO Diagram
Figure 29. Identifying Pin Sides on Four-Sided Package
Let us start with the input section. There is a direct internal connection to the analog subsystem through a restive path of ~300 ohms. Digital signals first pass through a Schmitt trigger, which determines the logic high and logic low. The output of the Schmitt trigger then routes to a variety of options through digital buffers, such as the I2C block, data bus for software polling, global bus for digital routing, and the interrupt controller (see Figure 31). Figure 31. GPIO Input Path
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The output and input paths are similar, in that there are separate paths for analog and digital. The analog has a direct connection from the output buffers to the GPIO pin. The digital portion of the output path uses multiplexers to route the digital logic options, such as the Global Output Bus, I2C hardware, or direct writes to the ports data register, which will be done through software as shown in Figure 32. The Drive Logic and Slew Control logic control four FETs (two N-Channel and two P-Channel). These FETs, combined with a pull-up and pull-down resistor, allow the wide variety of drive modes that PSoC offers. Figure 32. GPIO Output Path
Table 6. GPIO Drive Mode Information

Fig. 0 1 2 3 4 5 6 7 Drive Mode Resistive Pull-Down Strong Drive High Impedance Resistive Pull-Up Open Drain, Drives High Slow Strong Drive High-Impedance Analog Open Drain, Drives Low High Drive Strong Strong High Z Resistive Strong (Slow) Strong (Slow) High Z High Z Low Drive Resistive Strong High Z Strong High Z Strong (Slow) High Z Strong (Slow)
To configure the PSoC 1 GPIO drive modes, use a drive mode register. There are three registers for every port of a device. These registers are PRTxDM0, PRTxDM1, and PRTxDM2, where the x represents the port number. Each bit of the drive mode registers corresponds to a pin on the port. For example, bit 0, or PRT1DM0/PRT0DM1/ PRTDM2, corresponds to Port1[0]. You can configure the GPIO in one of eight possible drive modes, with some PSoC devices having fewer options. Figure 33 shows the diagrams of the available drive modes in PSoC 1 devices. Table 6 describes the drive modes and the configuration of the high-side and low-side FETs. Figure 33. GPIO Drive Modes
Pull-Up, Pull-Down, Open Drain Drives High, and Open Drain Drives Low all are drive mode types that can be applied to both inputs and outputs. When to use these drive modes depends on the application and what is attached to the pins. For example, if I2C is being used on a pin, then use Open Drain Drives Low with external pullup resistors. If a push button is on a pin, you may want to use either pull-up or pull-down if there are no external pullup or pull-down resistors. The Strong and Strong Slow drive modes are used for output signals. The difference between the two is that the Strong Slow drive mode uses the Slew Control logic in the GPIO pin to increase the rising and falling slope of the particular signal being routed out. High-Impedance (or High-Z) drive mode is used on both inputs and outputs of analog and digital signals. Note that Table 6 shows two versions of the High Impedance Drive Mode: High Impedance and High Impedance Analog. The difference is that in High Impedance Analog, the Schmitt Trigger is disabled. The advantage is that leakage current is reduced. The downside is the inability to use the digital system on the signal. If a digital input is required on the same pin as an analog input, then use High Impedance.
CapSense
Some PSoC 1 devices incorporate capacitive sensing or CapSense. CapSense is the process of measuring a change in capacitance (by monitoring capacitive coupling) to determine proximity of an object, such as a human finger. However, CapSense goes beyond that. Anything that you can measure using capacitive coupling also can be measured using CapSense. The advantage is that you
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can replace expensive and unreliable mechanical buttons with capacitive buttons using copper traces on a PCB, as shown in Figure 34. These CapSense buttons can act as standalone buttons or they can be put together in a matrix to create sliders and track pads. Figure 34. CapSense
Figure 35. Switch Mode Pump Circuit
For more information about getting started with CapSense designs in PSoC, refer to the Getting Started with CapSense design guide.
Multiply Accumulate (MAC)
PSoC System Resources

So far, we have looked at the core of PSoC: the analog system, the digital system, and the GPIO. However, other capabilities are just as important in improving a design.
Switch Mode Pump (SMP)

The switch mode pump (SMP) is a DC/DC boost circuit used with PSoC to allow the device to operate off of a single 1.5-V battery. PSoC includes an internal FET and independent PWM hardware to run the boost. You need to provide only an external battery, inductor, diode, and capacitor. Figure 35 shows the circuit for the SMP.
The Multiply Accumulate, or MAC, provides an 8-bit multiplier of signed numbers along with a 32-bit accumulate for summing numbers. The MAC is extremely useful in performing math operations and implementing digital filters. You use the MAC by writing to and reading from certain registers in the device. After multiplication, you can either read the value out of the register or store it in the accumulator. The accumulator can be cleared and reset to a value of zero by writing to clear registers (MACx_CL1 and MACx_CL2). A block diagram of the MAC is shown in
Figure 36. Figure 36. MAC Block Diagram
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Voltage Reference PSoC contains many options for voltage references. There are three main terms:
Following are the major features and capabilities of the PSoC I2C hardware controller:
AGND RefHi RefLo
Industry-standard interface
Philips
I2C
bus-compatible
Master and slave operation, multi master capable Only two pins (SDA and SCL) are required to interface to I2C bus Standard data rate of 100/400 kbps, also supports 50 kbps 7-bit addressing mode, 10-bit addressing supported
Analog signals in the device are biased to analog ground (AGND). The voltage location of AGND depends on the developer, who has a range of options. Analog signals higher than AGND are considered positive, while voltages below it are considered negative. RefHi and RefLo refer to the upper and lower limits of the analog system. Table 7 lists the available reference voltages of the analog system. In addition, PSoC contains a bandgap voltage reference of 1.3 V, denoted by Vbg, which is used to generate many of the reference voltages. Table 7. Reference Voltage Table (VDD at 5 V and 3.3 V)
Reference Vdd/2 Vbg Vdd/2 Vdd/2 Vbg Vbg 1.6Vbg 1.6Vbg 2Vbg Vbg 2Vbg P2[6] P2[4] Vbg P2[4] P2[6] RefLo (V) 1.2 or 0.35 0 0 0 1.3 2.6 - P2[6] P2[4] - 1.3 P2[4] - P2[6] AGND (V) 2.5 or 1.65 2.5 or 1.65 1.3 2.08 2.6 2.6 P2[4] P2[4] RefHi (V) 3.8 or 2.95 5.0 or 3.3 2.6 4.16 3.9 2.6 + P2[6] P2[4] + 1.3 P2[4] + P2[6]
Additional information on using I2C can be found in AN50987: Getting Started with I2C in PSoC 1.
PSoC Designer IDE

PSoC Designer is an integrated development environment (IDE) used to customize, configure, and program PSoC 1 devices. Cypress maintains and updates this software, which you can download at the website http://www.cypress.com/go/psocdesigner. PSoC Designer is a fully contained environment where you can create your PSoC application by configuring the analog and digital peripherals, write application code, and perform other functions discussed in this application note. In addition, this software lets you program a PSoC device and debug a project using the PSoC ICE-Cube debug platform, which we will discuss later.
Dedicated I2C Hardware

The I2C communications block is a serial-to-parallel processor, designed to interface the PSoC device to a two-wire I2C serial communications bus. To eliminate the need for excessive M8C microcontroller intervention and overhead, the block has I2C-specific support for status detection and generation of framing bits.
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PSoC Designer Layout

There are several menus and subsystems in PSoC Designer. To help new users, let us look at the PSoC Designer IDE from a high-level and then discuss in detail about the individual components of the software. Figure 37 shows the layout of PSoC Designer and a
description of each section of the IDE. Note that this is not the default layout of PSoC Designer. Any windows seen, in the following figure, that do not appear when you open Designer can be added by navigating through the View dropdown menu in the toolbar.
Figure 37. PSoC Designer Layout
1. Chip View Editor The Chip View Editor contains an abstract view of the inner workings of the PSoC 1 device, including the analog and digital blocks and routing and clocking options. You can have full control of how the chip is routed and how user modules are placed. 2. Workspace Explorer The Workspace Explorer lists all user modules in a design, along with each firmware file associated with the design. From here, you can right-click on the user modules to bring up options and to open a C or ASM file for editing. Generated files also appear here after the project is compiled.
Figure 38. PSoC Designer Workspace Explorer
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3. User Module Catalog Earlier in this application note, we noted how to configure digital and analog blocks to become specific peripherals. Rather than require the user to know how to configure the silicon to make digital and analog blocks function a specific way, such as an ADC or a PWM, you can choose easy-to-use peripherals that enable the software to configure the hardware appropriately. In PSoC 1 terminology, these configured blocks are referred to as user modules. In the User Module Catalog, you can browse through an organized list of predefined peripherals that Cypress has developed. This list is updated as new content is created. Additionally, the option to develop custom user modules is available for more advanced users. 4. User Module Parameters This window contains the parameters for the peripherals in a PSoC Designer application. As you click on a peripheral in either the chip view editor or the Workspace Explorer, the information in the window changes. For example, in Figure 39, PWM is selected as a peripheral. As a result, the User Module Parameter window allows me to configure parameters such as the clock, period, compare value, interrupt output, and digital routing options.
Figure 40. PSoC Designer Global Resources
For more information on global resources available in PSoC 1, refer to AN32200 - PSoC 1 - Clocks and Global Resources. 6. Pin Editor This window allows you to configure parameters related to the pins of the device. Each GPIO in a selected device is listed here. Each pin can be expanded to allow you to configure the pin name, port connection options, drive mode, GPIO interrupt type, and initial pin state. Figure 41. PSoC Designer Pin Editor
Figure 39. PSoC Designer Parameter Window
5. Global Resources Global Resources are the hardware settings that determine the operational characteristics of the PSoC device. This is the place to configure settings such as the device speed, device voltage, enabling/disabling of the switch mode pump, and Analog Ground (AGND).
7. Output Window The Output Window also is referred to as the Build Window. It shows information on compiler warning/errors and design rule checks (DRCs), as well as general information about PSoC Designer. This window is often hidden by default and appears when the project is built. You may choose to show this window constantly.
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8. User Module Data Sheet Window Every user module comes with a datasheet, which describes features, resource requirements, electrical specifications, registers, sample code, and a list of code functions in both Assembly and C. As a result, you can make dynamic adjustments of the user module in firmware during run time. The user module datasheet can be viewed as a side window in the main PSoC Designer window or as a PDF in an external viewer. 9 . D e vi c e R e s o u r c e M e t e r Every PSoC device differs in the number of resources it has available. Table 1, shown earlier, lists the various PSoC 1 devices with an overview of their resources. As a design is being developed, the Device Resource meter helps to ensure that the project is not expanding beyond the available resources. For each user module that you add, the system updates the data in the Resource Meter with the number of occupied PSoC blocks, along with estimated RAM and ROM usage for the current set of selected user modules.
function call you want an interrupt to jump to, must be done to the TPL file so that the changes are applied to the ASM file when the PSoC Designer project is built. For more information on the boot files and the role they play, refer to AN73617 PSoC Designer Boot Process, from Reset to Main. Library Files The library files are generated by PSoC Designer. They support the custom functions provided for the device and the user modules. These functions are also called application programming interfaces, or APIs. There are two folders, which contain the library files. One is for the source files (.ASM and .C), and the other is for header files (.h, and .inc). As a user module is added and the project is built, the library files for the new user module will be added automatically. Users can look into these files to see the code associated with user module functions. Flash Security The flash security file is where users can select the security settings for the device flash. Always protect the flash, whether with full flash protection or limited flash protection in the instance of a bootloader. For an example of a Flash Security file in PSoC Designer, see Figure 42.
PSoC Designer Code Editor

The code editor is the section of PSoC Designer that stores the program code for the application. There are four main files:
Figure 42. Flash Security File
Main.c/Main.asm Boot.tpl/Boot.asm Library Files Flashsecurity.txt
Main.c/Main.asm Main.c and main.asm are the two possible source files where your main body of code is located. This is where your main function will be located, which PSoC will jump to after completing the startup process. Two files are listed (main.c and main.asm) because PSoC Designer supports assembly and C programming. When you create a new project in PSoC Designer, you have an option to select one of these programming languages. After your selection, one of these two files will be created. Boot.tpl/Boot.asm The boot file is an assembly source file that houses the device initialization routines for the PSoC device, such as loading the IMO trim values. You will also find the interrupt vector table in this file. The difference between the TPL and ASM file is that the TPL file is a template used to generate the ASM file. Any edits, such as inserting a
The Ws listed in Figure 42 refer to the flash protection setting, with each letter referring to a block of flash. A flash block is 64 bytes of flash on all PSoC 1 devices, except the CY8C20xx6 devices. The CY8C20xx6 devices have flash blocks of 128 bytes. The available flash protection options, which are invoked by placing the following letters at the proper location, are listed in Table 8.
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Table 8. Flash Protection Settings

Flashsecurity.txt Protection Level External Reads External Writes Internal Reads Internal Writes
PSoC Designer Debugging

Debugging requires a special piece of hardware called an in-circuit emulator (ICE) and a module called a Pod. Both are shown in Figure 43. The Pod contains an on-chip debug device, which has special pins for debugging. Figure 43. PSoC Debug Pods
Unprotected Factory Upgrade Field Upgrade Full Protection
0 1 2 3
Y Y Y Y
Y N N N
Y Y Y N
Y Y N N
U F R W
You can configure each of the PSoC flash blocks with a flash security setting independent of the other blocks. Let us clarify the definition of external writes. Disabling an external write does not refer to the inability to program a device, but, rather, the inability to externally program a block or set of blocks without erasing the entire flash memory. If a flash protection mode is used where external writes are disabled, the flash must be erased first before the device can be programmed. PSoC Programmer erases the device flash prior to each program. For more information on flash writes and flash security, refer to AN2015 -- PSoC 1 Reading and Writing Flash.
PSoC Designer Compilers

PSoC Designer uses the Imagecraft C compiler for its application code. There are two versions: Imagecraft Light and Imagecraft Pro. The Light version is included free with all downloads of PSoC Designer, while Pro can be purchased directly from Imagecraft. The Pro version provides greater optimizations, which can improve the code size by 10 percent to 15 percent over the free version. For more information on the Imagecraft compiler, go to the Imagecraft website.
The benefit to Pods is that you buy them for the family on which you want to debug, such as the CY8C29xxx, and you can use the part on any device in that family, regardless of the I/O count. The OCD device will always take the form of the largest package in that family. Therefore, if the largest device you can get is a 100-pin TQFP, that will be the package in which the OCD comes. The OCD is the device that is present on the Pod. Two examples of Pods are shown in Figure 44. Figure 44. PSoC Debug Pods
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The OCD Pod replaces the device that is currently present on a PCB in the PSoC footprint location, using the Pod shown on the left of Figure 44. To get the Pod to fit on a PCB, use a foot kit, which acts as an adapter between the footprint on the PCB and the debug Pod. Cypress offers foot kits to support the chosen package type. Figure 45 shows DIP and QFN examples of a foot kit. Figure 45. PSoC Debug Foot Examples
Programming
PSoC offers a variety of options, both in hardware and software, for programming a device. Your best method depends on certain factors and conditions.
PSoC Programmer
PSoC Programmer programs PSoC devices and performs other functions, such as reading out the flash, performing checksums, and erasing flash. There are two versions of PSoC Programmer for programming PSoC 1 devices: a standalone PSoC programmer and a simplified version of PSoC Programmer that is integrated into PSoC Designer. The integrated version eliminates the need to swap between two applications to program the device. Figure 47. Standalone PSoC Programmer Application
Debugging in PSoC Designer

The menu bar of PSoC Designer has special buttons for using the debugger, which allow for ease of navigation through debugging application code. The PSoC Designer debug bar is shown in Figure 46. Figure 46. PSoC Designer Debug Bar
Various buttons will be active depending on whether a debug session is active. Upon clicking Connect/ Disconnect and then Download to Emulator, PSoC Designer programs the OCD to execute your application code. For more information on PSoC 1 debugging, refer to AN73212 Debugging with PSoC 1.
The PSoC Designer Programmer application is a simplified interface that gives you the basics to program a device. Included is the ability to choose an acquire mode and to decide if you want the flash verified. Figure 48. PSoC Designer Programming Application
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Programming Hardware
Programming hardware can take the form of multiple devices, depending on whether the programming device is third-party (that is, not developed by Cypress) or first-party (developed by Cypress). Cypress offers four first-party programming devices: MiniProg1, MiniProg3, ICE-Cube, and CY3207-ISSP.
Figure 51. PSoC ICE-Cube
MiniProg1
The MiniProg1 is the ISSP programmer that is included with many PSoC 1 kits. You can use this programmer for all PSoC 1 devices, except the CY25/26xxx devices. The MiniProg1 cannot be used to program PSoC 3 or PSoC 5 devices. Figure 49. PSoC MiniProg1
CY3207-ISSP
The CY3207-ISSP was developed before the MiniProg1, but this older production programmer still has practical applications. The CY3207-ISSP can program either insystem or in-socket by placing PSoC DIP devices (or devices in a DIP adapter) in the ISSP programmer. The programmer also allows the hex file to be loaded on to the internal memory, letting you program devices by pressing a button on the CY3207-ISSP. Figure 52. PSoC CY3207-ISSP
MiniProg3
The MiniProg3 is the ISSP programmer that comes with the CY8CKIT-001 Development Kit. The MiniProg3 is an all-in-one programmer for PSoC 1, PSoC 3, and PSoC 5 devices, a debug tool for PSoC 3 and PSoC 5 architectures, and a USB-I2C bridge for debugging I2C serial connections and communicating with PSoC devices. Figure 50. PSoC MiniProg3
Third-Party Programmers
There is also a list of third-party programmer tools, at http://www.cypress.com/?rID=2543, that Cypress has designed, tested, and qualified to support programming of PSoC 1 devices.
CY3215A-DK
CY3215A-DK In-Circuit Emulation Lite Development Kit includes an in-circuit emulator (ICE). While the ICE-Cube is primarily used to debug PSoC 1 devices, it can also program PSoC 1 devices using ISSP. Rather than using the blue CAT5 cable or the flex cable to interface with debug pods, you can use the yellow ISSP cable (see Figure 51) to program devices. This makes the ICE-Cube useful for both debug and production environments.
Other Programming Methods

Using Cypress-provided programming applications and hardware is not the only way to program PSoC devices. The following sections discuss the other methods. In-System Serial Programming (ISSP) You can use ISSP for programming a device after it has already been installed in a system. The advantage is that it allows assembly-line programming of a device. As a result, you do not need to buy chips preprogrammed from a distributor. For more information on ISSP, refer to the
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PSoC 1 ISSP Programming Specifications in AN2026a or AN2026b, depending on which part is being used. See the Compiled Application Notes List at the end of this application note for details on which devices are covered in each application note. Host Sourced Serial Programming (HSSP) HSSP is an implementation of ISSP using a host device, such as a PSoC, to program another PSoC device. This method is useful for field firmware upgrades and calibration. For more information on HSSP, refer to AN44168 - Host Sourced Serial Programming. Bootloaders Bootloaders let you update device firmware in the field. Cypress offers a variety of bootloader options, which allow you to issue firmware upgrades to customers online. Customers can take this upgrade firmware and update the device themselves though a PC interface. Devices can be bootloaded through a variety of interfaces; however, Cypress offers USB and I2C bootloaders as standard components.
The PSoC Designer IDE User Guide trains new users on how to use the many features of PSoC Designer in more detail. This is an essential guide. Figure 53. Access to Documentation in PSoC Designer
PSoC 1 Training Videos: Here are three instructional videos to help new users get started: PSoC Designer 210: Chip Level Designs provides an overview of the PSoC Programmable System-on-Chip, the chip-level design of PSoC Designer, and a hands-on example design project. It takes you deep into various types of PSoC Designer datasheets, explains how to optimize designs with flexible routing resources, and shows you various PSoC design considerations in the chip-level view using an example project and the CY3210PSoCEval1 Kit. PSoC Designer Module 3: Debugging with PSoC is a course that introduces the powerful PSoC Designer debugging tools, which can save you hours in troubleshooting. This video reviews debugging features, such as trace buffers, watch variables, breakpoints, and dynamic event points. The last part of the module walks you through debugging of a real project. For this project, you need the CY3215-DK Basic Development Kit, which an ICE. PSoC Designer Module 4: Dynamic Reconfiguration is a course that looks at the register map and configuration files used with PSoC user modules. Then, the video describes how to implement dynamic reconfiguration, which allows you to reuse resources in PSoC and maximize the integration value proposition.
Available Resources
Many resources are available for PSoC 1 developers, including datasheets, reference manuals, videos, and application notes.
For Engineers Just Getting Started

In addition to this application note, engineers who are new to PSoC can explore the resources listed in Table 9. Table 9. Beginner Resources
Resource PSoC Designer IDE User Guide Location PSoC Designer Bar: Help -> Documentation -> Designer Specific Documents -> IDE User Guide http://www.cypress.com/?rID=17763
PSoC Designer 210: ChipLevel Designs (Video) PSoC Designer Module 3: Debugging with PSoC (Video) PSoC Designer Module 4: Dynamic Reconfiguration (Video)
http://www.cypress.com/?rID=1084
http://www.cypress.com/?rID=1085
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For Engineers Seeking More

For engineers exploring PSoC 1 for a project or simply to learn, many resources are available (see Table 10). Table 10. Advanced Resources
Resource Device Datasheets Device Errata Location http://www.cypress.com/?id=1573&rtID=107 http://www.cypress.com/?app=search&searchT ype=advanced&keyword=&rtID=111&id=1573& applicationID=0&l=0 http://www.cypress.com/?id=1573&rtID=117
datasheets include information about the user module, how it functions, electrical specifications, and software functions (also known as APIs) that allow for dynamic adjustments to the user module configuration during run time. To access these datasheets, use the link in Table 10 or in PSoC Designer by right-clicking on a user module and selecting Datasheet. From there, select your design method for viewing the datasheet. Figure 54. User Module Datasheet in PSoC Designer
Technical Reference Manual User Module Datasheets Application Notes Knowledge Base Articles Development Kit Information Training & Webinars Cypress Developer Community
http://www.cypress.com/?app=search&searchT ype=advanced&keyword=&rtID=116&id=1573& applicationID=0&l=0 http://www.cypress.com/?id=1573&rtID=76 http://www1.cypress.com/?id=1573&rtID=118 http://www.cypress.com/?id=1573&tabID=5474 9 http://www.cypress.com/?id=1573&rtID=135
Application Notes, such as this one, broaden your understanding of PSoC 1 and PSoC Designer features and capabilities. These notes cover many system-level design problems. Knowledgebase (KB) Articles are a database of frequently asked technical support questions and their associated answers. Often, users can find answers to their questions here. The Development Kit Information page gives you information on PSoC 1 development kits and their capabilities, and provides links to download example projects that utilize the board features. Customers also can find links to download schematics to the development kits. The Training and Webinar page provides information on upcoming live webinars and training events hosted by Cypress employees on specific topics. This is an opportunity to receive instruction from PSoC experts and to ask questions. The Cypress Developer Community is the newest addition to www.cypress.com. It provides a place for PSoC developers to communicate and share ideas via online forums. Find Blogs written by Cypress employees, along with PSoC project ideas and applications shared with others.
http://www.cypress.com/?id=2203
Device Datasheets can be used to become more familiar with the part and its capabilities. Included is information on features, package pinouts, electrical specifications, and device ordering. Device Errata is a document that lists any specification of the device that deviates from either the device datasheet or the Technical Reference Manual. Technical Reference Manual (TRM) contains advanced information about device features and how they operate. The TRM also includes a register list that helps you to understand the various PSoC 1 registers and how to use them. User Module Datasheets provide information on the various user modules that you can place in a design. Competing devices, which have fixed capabilities, include peripheral specifications in their device datasheets. However, because PSoC is configurable, Cypress has created individual datasheets for each user module. Those
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My First PSoC 1 Design

This section discusses how to create a simple PSoC 1 project, program it into a PSoC device, and configure various PSoC 1 demonstration boards to view the results of the application.
About the Design

To become familiar with how to create a project on a PSoC 1 using PSoC Designer, let us create a simple project that produces two PWM outputs, one hardware and one software, on a GPIO. One GPIO will display a blinking LED at a fixed rate, while another GPIO will show a pulsing, or heartbeat, LED.
Creating My First PSoC 1 Design

1. Begin by creating a PSoC Designer project, by navigating to File -> New Project and name it Project1_HelloWorld, as shown in Figure 55. Figure 55. Creating a New PSoC Designer Project
Note that if you are developing this project with another kit, use the following part numbers:

2.
CY3214-PSoCEvalUSB: CY8C24994-24LTXI CY3271-PSoC First Touch: CY8C20634-12FDXI
Locate the User Modules window in PSoC Designer. By default, it may be located on the right side of the screen. If you do not see it, find it by navigating to it via the toolbar (View -> User Module Catalog). After you find the User Module Catalog, expand the PWMs folder. Locate the PWM8 User Module, right-click on it, and select Place. Repeat the placement process to place two PWM8 User Modules in the design. Finally, locate the Misc Digital User Module folder, and place a LCD user module. Figure 57. PWM User Module Placement
Select the part number for the device and the preference of coding language for the main program file as shown in Figure 55. You can click on Device Catalog to open the Device Catalog and then select the device by browsing through it as shown in Figure 56Figure 56. Device Catalog. For this project, we have selected a CY8C29466-24PXI, because that is the part that accompanies the CY3210-PSoCEval1 kit. After the device is selected, click on Create Project with CY8C29466-24PXI. C is my language of main.c, as shown in Figure 55. After you have made all the changes, click OK. Figure 56. Device Catalog 3. Click on PWM8_1 in either the Workspace Explorer or the Chip Editor to configure the user module properties. After clicking on PWM8_1, on the left-hand side of PSoC Designer, the parameters windows allow you to edit the various properties of the PWM. Rename the User Module to LED1_PWM and make the configuration changes shown in Figure 58 for it.
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Figure 58. PWM_1 User Module Parameters
Figure 61. Global Resources Parameters
4.
Click on PWM8_2 to configure that User Modules properties. The required settings are shown in Figure 59. Figure 59. PWM_2 User Module Parameters
7.
To see the signal on a GPIO pin, you must implement the routing for the PWM signals. You will see a line from PWM8_1 to Row_0_Output_0 and from PWM8_2 to Row_0_Output_1, as shown in Figure 62. Figure 62. PWMs Connected to Row Outputs
5.
Click on the LCD user module and configure it according to the settings below (see Figure 60). The LCD is used to display a static message string while the application is running. Figure 60. LCD Parameters
Connect the output of PWM8_1 to Port_0_0 using auto routing. Press shift and select the CompareOut pin of PWM8_1. The PSoC Designer engine finds all the possible routes and highlights the destination of the routes as shown in Figure 63.
6.
To set source clock VC3, configure the Global Resources based on the following.
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Figure 63. Possible Routes between CompareOut of PWM_1 and Port_0_0
Figure 66. Digital Interconnect Configuration
8.
Continue holding the shift key and click on the destination, which is Port_0_0, and the route is complete as shown in Figure 64. Figure 64. Connection between CompareOut of PWM_1 and Port_0_0
11. Confirm that the digital routing diagram looks as shown in Figure 67. If they match, then the configuration of the pulsing heartbeat LED is now complete. What you see in PSoC Designer should look like Figure 67. Figure 67. Final Digital Routing Diagram
9.
We will also implement logic in the row outputs by feeding the two PWM outputs into an XOR. The difference of the period of the two PWM signals, XORed together, will create the effect of pulsing, or a heartbeat. Click on the Row_0_Output_0 Digital Interconnect to open the configuration options as shown in Figure 65. Figure 65. RO0[0] Digital Interconnect View
12. Implement a software LED that will produce a constantly blinking LED. This will demonstrate the ability of PSoC to implement hardware and software functionality in unison. In Workspace Explorer, locate the Source Files folder, which is under the Project1_HelloWorld Folder and open main.c. In this file, we will place our source code for the project. After main.c is open, place the c code listed below.
10. Start by clicking on the LogicTable_Select, which is denoted by the square box in the middle. Click on it and locate A_XOR_B as shown in Figure 66. Then click on Close to save the settings.
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Code 1. Project 1 main.c

#include <m8c.h> #include "PSoCAPI.h void main(void) { static unsigned int index; LCD_Start(); LCD_Position(0,0); LCD_PrCString("Hello World!"); LCD_Position(1,0); LCD_PrCString("I am Alive!"); LED1_PWM_Start(); LED2_PWM_Start(); while(1) { PRT0DR ^= 0x02; for(index = 0; index < 22000; index++); } }
Figure 69. Build and Generate Option
15. After the project completes the build process without warnings or errors, the next step is to program a Cypress development kit. In PSoC Designer, locate Program in the menu bar and click on Program Part (see Figure 70). Figure 70. Program Part Option
13. Configure the GPIO drive mode for the pin, to ensure we can drive the LED. Return to the chip-level view by double-clicking on Project1_HelloWorld [Chip]. Locate the Pinout Window and expand the options for P0[0] and P0[1]. Configure the pins as shown in Figure 68. Figure 68. Pin Configuration
After you click on Program Part, the window shown in Figure 71 opens. The Acquire Mode is set to Power Cycle if the MiniProg is supplying power to the device and it can acquire the device by cycling power. It must be set to Reset if the device is externally powered and the MiniProg can only acquire the device by resetting it. After ensuring the settings in Figure 71, click the download button to program the device. Figure 71. Programming Status
14. Now that the project is configured, build and generate the project. Locate the Build drop-down menu in the toolbar and select Build -> Generate/Build Project1_HelloWorld Project. Alternatively, press F6 (see Figure 69).
PROGRAM
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Setting Up the CY3210-PSoCEval1 Board

This demonstration is compatible with the CY3210PSoCEval1 hardware. For more information on this kit, go to http://www.cypress.com/?rID=2541. Figure 72. A View of the CY3210-PSoCEval1 Kit
Connect a 12V DC power supply to J10 on the kit. Alternatively, you can connect a 9V battery to J12. In addition, connect a programming device to J11. The board connections can be seen in Figure 74. Figure 74. Power and Program Connections
POWER
PROGRAM
Setting Up the CY8CKIT-001 Board

Perform the following steps to configure and program the CY3210-PSoCEval1 kit. Note that this kit requires a programming device, such as a MiniProg or IceCube. 1. 2. With no cables connected to the demo board, ensure that J1, J2, and J3 are not in position. Place a wire connecting P0[0] to LED2 and another wire connecting P0[1] to LED3 (see Figure 73). Figure 73. CY3210-PSoCEval1 Pin Connections When you use a CY8C29x66 processor module, this demonstration is compatible with the CY8CKIT-001 hardware. For more information on this kit, go to http://www.cypress.com/?rID=37464. Perform the following steps to configure and program the CY8CKIT-001 kit. Note that this kit requires a programming device, such as a MiniProg or IceCube. Additionally, this kit supports on-chip debug when using the IceCube. Figure 75. A View of the CY8CKIT-001 Kit
3.
Ensure that a CY8C29466-24PXI is the device currently on the board.
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1.
With no cables connected to the demo board, set the following jumpers to configure the development board as follows: VDD Select (SW3) -> 5-V (Up Position) 5-V Source (J8) -> VREG (Upper two pins VDD Digital (J7) -> VDD (Upper two pins) VDD Analog (J6) -> VDD (Upper two pins) LCD Power (J12) -> ON (Lower two pins) VDDIO Select (J2-J5) -> VDD (Upper-left two pins) Place a wire connecting P0[0] to LED2 and another wire connecting P0[1] to LED3 (see Figure 76). Figure 76. Alternative View of Pin Connections

2.
Regardless of which development kit you use to test the application, you will observe two blinking LEDs. One will blink rapidly, while the other will blink much more slowly, but will pulse with the light intensity alternatively and slowly increasing and decreasing.
Next Steps
This application note covers the basic details about PSoC 1. You can refer to specific Application Notes for more information and projects regarding to a specific topic. 1. Analog AN2219 - PSoC 1 Selecting Analog Ground and Reference AN74170 PSoC 1 Analog Structure and Configuration with PSoC Designer AN13666 - PSoC 1 Driving Analog Buffer Output to the Rail AN2096 - PSoC 1 - Using the ADCINC Analog to Digital Converter 2. Switched Capacitor Blocks AN2041 Understanding PSoC 1 Switch Capacitor Analog Blocks AN2168 PSoC 1 Understanding Switched Capacitor Filters AN16833 - Signal Mixing with PSoC Switched Capacitor Blocks 3. GPIO AN2094 - PSoC 1 - Getting Started with GPIO
3.
Connect a programming device, such as a MiniProg or ICE, to J5 on the PSoC 1 processor module. Then, connect power to the board with either a 12-V DC power supply or a 9V battery. The board connections can be seen in Figure 77. Figure 77. Power and Program Connections
4.
Digital AN2141 - PSoC 1 Glitch Free PWM
5.
Flash AN2015 - PSoC 1 Reading and Writing Flash
6.
I2C AN50987 Getting Started with I2C in PSoC 1
POWER
7.
SPI AN51234 - Getting Started with SPI in PSoC 1
8.
Sleep Mode AN47310 - PSoC 1 Power Savings Using Sleep Mode
9.
LCD AN56384 - PSoC 1 Segment LCD Direct Drive AN2152 - PSoC 1 Graphics LCD and PSoC Interface
PROGRAM
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Summary
This application note described the tools you need to start PSoC 1 projects. For more information on any of the topics mentioned, refer to any of the links or references made, or visit www.cypress.com/go/psoc1.
AN32200 AN32200 - PSoC 1 - Clocks and Global Resources
AN2141 - PSoC 1 Glitch Free PWM AN56384 - PSoC 1 Segment LCD Direct Drive AN2152 - PSoC 1 Graphics LCD and PSoC Interface AN47310 - PSoC 1 Power Savings Using Sleep Mode AN51234 - Getting Started with SPI in PSoC 1 AN2219 - PSoC 1 Selecting Analog Ground and Reference AN13666 - PSoC 1 Driving Analog Buffer Output to the Rail AN2096 - PSoC 1 - Using the ADCINC Analog to Digital Converter
Compiled Application Notes List

The following list summarizes the application note resources mentioned throughout this document.
AN73617 PSoC Designer Boot Process, From Reset to Main AN2041 Understanding PSoC 1 Switch Capacitor Analog Blocks AN2168 PSoC 1 Understanding Switched Capacitor Filters AN74170 PSoC 1 Analog Structure and Configuration with PSoC Designer AN2015 - PSoC 1 Reading and Writing Flash AN2026a - PSoC 1 ISSP Programming Specifications - CY8C21x23, CY8C21x34, CY8C23x33, CY8C24x23A, CY8C27x43, CY8CTMG110, CY8CTST110 AN2026b - CY8C21x45, CY8C22x45, CY8C24x94, CY8C28xxx, CY8C29x66, CY8CTST120, CY8CTMA120, CY8CTMG120, CY7C64215 PSoC 1 ISSP Programming Specifications AN44168 - Host Sourced Serial Programming AN73212 Debugging with PSoC 1 AN50987 Getting Started with I2C in PSoC 1
About the Author

Name: Title: Background: Robert Murphy Application Engineer Sr. Robert Murphy graduated from Purdue University with a Bachelors Degree in Electrical Engineering Technology. rlrm@cypress.com
Contact:
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Document History
Document Title: Getting Started with PSoC 1 AN75320 Document Number: 001-75320
Revision ** *A ECN 3498585 3846596 Orig. of Change RLRM GULA Submission Date 1/17/2012 12/19/2012 New application note Updated project to PSoC Designer 5.3. Updated all the relevant screenshots. Removed incorrect mention of PSoC Creator Added references to all Application Notes and Technical Reference Manual. Corrected the SC-based Integrator circuit. Minor content edits. *B 4064460 GULA 07/16/2013 Updated the UM parameters screenshots Updated the board images Added a section on Auto-routing Added links for the App Notes and kits Replaced section on CY3215-DK with details about CY3215A-DK. Added Next Steps section for details about the specific App Notes Description of Change
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All other trademarks or registered trademarks referenced herein are the property of their respective owners. Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone : 408-943-2600 Fax : 408-943-4730 Website : www.cypress.com
Cypress Semiconductor Corporation, 2012-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress product in a life -support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
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AN75320

Getting Started with PSoC 1

Document No. 001-75320 Rev. *B

Document No. 001-75320 Rev. *B

Figure 3. Block Diagram of PSoC 1 Showing Configurability

The PSoC Product Portfolio

Document No. 001-75320 Rev. *B

Choosing a PSoC 1 Device

Analog Mux Bus N Y N Y N N N Y Y Y N Y Y

Dedicated SAR N SAR10 N N SAR8 N SAR8 SAR10 SAR10 N N N N

PSoC 1 Feature Set

Document No. 001-75320 Rev. *B

Digital Basic Blocks (DBBs)

Digital Communication Blocks (DCBs)

Digital Routing in PSoC 1

Figure 6. Digital System Routing Matrix

Document No. 001-75320 Rev. *B

Figure 8. Row Input Multiplexer

Figure 9. Row Input Multiplexer Connections

Document No. 001-75320 Rev. *B

Figure 10. RI and RO Digital Block Connections

Table 3. Row Output to Global Output Connections

Document No. 001-75320 Rev. *B

Figure 15. Global to Global Connections

Logic Lookup Table (LUT)

Table 4. PSoC 1 Digital Logic Options

Document No. 001-75320 Rev. *B

Figure 19. PSoC 1 Digital Clock Tree

Phase-Locked Loop (PLL)

VC1 VC2 VC3

Slow IMO (SLIMO)

Document No. 001-75320 Rev. *B

Figure 20. PSoC 1 Analog System Block Diagram

Equation 1. Calculating Resistance from Switch Cap

Continuous Time (CT) Blocks

Switched Capacitor (SC) Blocks

Document No. 001-75320 Rev. *B

Analog Routing in PSoC 1

Document No. 001-75320 Rev. *B

Differences with the CY8C28xxx Parts

Document No. 001-75320 Rev. *B

Figure 26. Close-up of Type-E Analog Blocks

Analog Routing Considerations

Figure 27. Analog Routing of PSoC 1

Array Input Configuration

P0[1] ACB00 P2[3] ASC10 P2[1] ASD20

ACB02 ASC12 ASD22

ACB03 ASD13 ASC23

Document No. 001-75320 Rev. *B

Figure 29. Identifying Pin Sides on Four-Sided Package

Document No. 001-75320 Rev. *B

Table 6. GPIO Drive Mode Information

Document No. 001-75320 Rev. *B

Figure 35. Switch Mode Pump Circuit

Multiply Accumulate (MAC)

PSoC System Resources

Switch Mode Pump (SMP)

Figure 36. Figure 36. MAC Block Diagram

Document No. 001-75320 Rev. *B

AGND RefHi RefLo

PSoC Designer IDE

Dedicated I2C Hardware