Lab 01

Basics of Hardware Verilog Design

Execute in Week of: Report due Week of: 01/21/13 01/28/13

EE-3173

1 Introduction
1.1 Purpose
The purpose of this lab is to give students a basic understanding of hardware design and implementation using the Verilog hardware description language. In addition, the students will also be familiarized with the Altera Quartus II development suite. For this assignment, you will be responsible for three tasks: Designing a simple circuit using Verilog that increments a counter and displays the value on the seven segment displays using the default pin assignments. Designing the same circuit using custom input and output pin names and assignments. Modifying the circuit to alternate between incrementing and decrementing the counter whenever a button on the DE2 board is pressed.

1.2 Background
Quartus II is the software that allows you to design, compile and download files to the hardware board to reconfigure special custom hardware units, whole processors such as the Nios II, peripheral units, and I/O devices. Hardware Description Languages (HDLs) such as Verilog are indispensable to the design of hardware functions. In particular, behavioral module descriptions are much more efficient and much less error prone than schematic design methods.

1.3 Equipment for This Lab

Quartus II software suite and Altera DE2 Development Kit

1.4 Team Size

One person per team (youre on your own for this one).

2011, R.M. Kieckhafer & C.M. Cischke

2 Hardware Design using Verilog

1. Open Quartus II. 2. From the New menu, select New Project Wizard. 3. Work your way through the wizard, filling out the forms as follows: a. Choose some other working directory for Quartus. The default directory is part of the Quartus install and is a bad place to work. A suggestion would be: C:\EE3173 1. Make sure to clean up after yourself when you are done with this folder. b. Choose a representative project name beginning with QP_, such as QP_Lab1 2. c. We're not going to add any external files to the project (yet). d. Choose the Cyclone II EP2C35F672C6 as the target device. e. We're not using any external EDA tools. 4. The very first thing you must do after creating a new project is to: a. Select AssignmentsImport Assignments from the menu and b. Import the DE2_pin_assignments.csv file. This will generate all of the default pin assignments you will use on the DE2 development board. This file can be found on the 3173 course web page in directory LAB_Downlad_Files. c. Next, click DE-2 Resources and download the DE-2 Pin Assignments (csv File) from the screen that appears. d. Save this file in your project directory.

2.1 Design an Incrementing Counter

5. Navigate to the FileNew menu and select Verilog HDL File under the Design Files section, as shown in Figure 1. Click OK.

It doesn't really matter where you put it, as long as there aren't spaces in the path. Somehow, despite the fact we got rid of 8.3 filenames in Windows 98, Altera software still can't handle long filenames or paths with spaces in them. The convention of naming a Quartus Project QP_<project-name> is a 3173 convention. Quartus does not care what you name it. But, if you want a TA to help you debug something, naming conventions like this really help.

2011, R.M. Kieckhafer & C.M. Cischke

Figure 1: Generating a New Verilog File 6. To generate a top-level hardware module for the project, copy in the counter/driver Pre-Lab file from your flash drive, and name the module with the same name as your project. Any other lower-level modules that you incroporate into the project later may have any name. 7. Edit your module to display only the eight most significant bits (2 most significant digits) in hexadecimal using the seven-segment displays. Note: a. The 50 MHz Clock input pin is called CLOCK_50 using the default pin assignments. b. The pins for the 7-segment displays are called HEX0 through HEX7. 8. When your design is complete, navigate to ProcessingStart Compilation to compile your hardware design. If there are any compiler errors, correct them and compile again. Your TA is available to help you if necessary. 9. From the Tools menu, select Programmer.

2011, R.M. Kieckhafer & C.M. Cischke

10. We now need to select the pathway for downloading to the DE2 board. a. Click Hardware Setup in the upper-left-hand corner of the screen. b. In the dialog box, Currently Selected Hardware menu, choose USB Blaster [USB 0]. c. Click Add Hardware and then Close. 11. Make sure the Program/Configure box is checked, and click Start. NOTE: if you get an error after you click Start saying Error: Cant access the JTAG chain, that means there is a hardware or power problem with the DE2 board you are using. If you receive this error, ask your TA for assistance, as the DE2 board may be faulty. Show the TA your functioning board and have him sign off on your data sheet.

2.2 Generate the Incrementing Counter using Customized Pin Assignments

It is extremely important that Pin Assignment is done right, or your design will not function. There are specific pins that are already connected to various peripherals on the DE2 board including, but not limited to, the LEDs, the buttons, and the 50 MHz system clock. Pin Assignment proceeds as follows. 12. Either rewrite your Verilog code from phase 2.1 or change the names of your input and output pins to some other descriptive name and save the file. 13. From the Assignments menu, select Assignment Editor. 14. Highlight all of the assigned pins and press the delete key to clear them. Save the assignment editor. 15. Recompile your project to refresh the pin names in the Assignment Editor. 16. Return to the Assignment Editor. Next to the Category: button, there is a drop-down menu. Open it and Select Pin. 17. Double click where it says new under the heading To. This should give you a list of all of the input and output Pin Names that you used in your design. 18. Assign each pin listed to the appropriate location given in the list that you brought to lab with you. Your pin assignments should look similar to Figure 2, though it is an incomplete listing.

Figure 2: Custom Pin Assignments

2011, R.M. Kieckhafer & C.M. Cischke

19. Save your design 20. Recompile your project, now with real pin assignments in place. Show the TA your pin assignments screen and have him/her sign off this step on the Data/Signoff Sheet. 21. Download your counter to your development board and verify that it works correctly. Show the TA that your design functions correctly.

2.3 Generate an Incrementing and Decrementing Counter

22. Modify your design from section 2.2. In addition to the 50 MHz clock and the seven-segment display pins, add a new input pin to represent one of the blue pushbuttons on your development board (again, you can download and edit code from your Pre-Lab design. 23. Use one of the pushbuttons to control the direction of the counter. Every time you push the button, your counter should toggle between increment and decrement. 24. Compile your code to refresh the pin assignment list and then assign your new pushbuttons pins using the Assignment Editor. 25. Show the TA your pin assignments and have him/her sign off this step on the Data/Signoff Sheet. 26. Show the TA your functioning system and have him/her sign off this step on the Data/Signoff Sheet.

2011, R.M. Kieckhafer & C.M. Cischke

3 Considerations
1. Explain the advantage(s) of using a soft-core architecture instead of a Commercial Off the Shelf (COTS) microcontroller in this course (HINT: remember the course title). 2. What are some of the benefits of using the seemingly counter-intuitive active-low signaling protocol? 3. Design a way to connect two 32-bit up-counters together to create a single 64-bit up-counter module. Keep additional logic to a minimum. Write the Verilog statements to implement this, assuming there is a module called UpCounter32 you can instantiate. 4. What was the most difficult portion of this process to understand? Why?

4 Deliverables
No later than the beginning of the next lab section, turn in a Short Form Lab Report, comprising: The completed Data/Signoff sheet, Typed answers to the Considerations questions adhering to the style specified in [1, Sec. 2]. Hardcopies of all final working Verilog modules adhering to the style specified in [1, Sec. 3].

5 References
1 R. M. Kieckhafer, Laboratory Procedures and Style Guides, Current Version.

2011, R.M. Kieckhafer & C.M. Cischke

Lab 01

Data/Signoff Sheet
Each laboratory team must complete a copy of this sheet.

EE-3173

____________________________________________________________________________________ Names of All Team Members

Step 12: Counter circuit is functioning correctly.

TA Initials ______________

Step 21: Pin assignments are correct.

TA Initials ______________

Step 22: Counter circuit is functioning correctly.

TA Initials ______________

Step 26: Pin assignments including pushbutton are correct.

TA Initials ______________

Step 27: Counter both increments and decrements.

TA Initials ______________

2011, R.M. Kieckhafer & C.M. Cischke

Intentionally Blank

2011, R.M. Kieckhafer & C.M. Cischke

Lab 01

Pre-Lab Assignment
Due at beginning of the laboratory session

EE-3173

Name of Individual: __________________________________________________________________ Create Verilog files for each question below, adhering to the style specified in [1, Sec. 3]. Attach a hardcopy of each file generated. Save all files to a Flash Drive and bring it to Lab with you. 1. Create a Verilog module for a 32-bit rollover up-counter. It will have a one-bit input for the clock and 32-bits of output pins. (this is just the one designed for Homework 1). 2. Create a module to translate a 4-bit binary number into the correct 7 output signals to display the (one digit) hexadecimal value of the input number on a 7-segment display. Note: be careful that your display scheme visually differentiates between 6 and b, and between 0 and d. 3. Combine your counter module and eight 7-segment modules into a single module to permit the counter value to be displayed in hexadecimal on an 8-digit display 3. 4. Modify the Verilog design from the previous problem as follows: a. Add a one-bit input pin labeled reverse. In lab, this pin will be connected to a pushbutton on the DE2 board. b. Edit the logic such that each time the button is pushed, the direction of the counter toggles between up-counting and down-counting. 5. Combine the new counter module with the 7-segment driver modules, as you did with the original counter in step 3. 6. Go to the references section on the course website and download the DE2 Users Manual (DE2-Users-Man.pdf). Make a note of the many pin assignment tables and bring the file to lab you will need it.

Multiple modules can be defined in a single Verilog (.v) file, making it easy to instantiate one or more lower-level modules into a higher-level module, all in the same file.

2011, R.M. Kieckhafer & C.M. Cischke