OUTPUT_ICC.

TCL
The purpose of this script is to output the final Design in various formats for back annotations, hierarchical timing closure, for third party design tool and for LVS and timing check. In this script we are generating outputs as follows: Create_ilm: Create an interface logic model (ILM) for the current design Stores signal integrity (SI) and coupling capacitance information with the ILM views This option is honoured only when the design is track assigned or detail routed. It is ignored for unrouted or global routed designs

Write_def: Writes the design data of the specified design to a file in DEF format, including the physical layout, netlist and design constraints

Write_parasitics format SPEF|SBEF : This command writes the parasitics for the current design to a disk file is SPEF standard parasitic exchange format or SBEF standard Binary exchange format

Change_names: Specifies a name rule set that details the rules for modifying names to which the object names conform. The name_rules file is defined by using the define_name_rule command. By default, this value is the name_rules file specified by the default_names_rules variable. The tool ignores the rules option if you specify the name_file option.

Set_physical_signoff_options [-exec_cmd icv|Hercules] :

Specifies the name of the executable. To use IC Validator , specify icv, to use Hercules, specify Hercules. The default is none. The tool uses the standard search path to search for the specified executables [-drc_runset filename] specifies the foundry runset (rule Dheck) to use for design rule check(DRC). The default is none. This command must me run before signoff_drc or sign_off_metal_fill.

Write_verilog: Outputs a hierarchical Verilog file for the current design.

Write_stream: Outputs GDSII file for the current design.

Create_macro_fram: It creates a macro view of the current design.

Write_sdc: Writes sdc file for various scenarios.

Extract_hier_antenna_property: This command extracts the hierarchical antenna properties of all the top-level ports in the given cell routed by Astro of IC compile. The Hierarchical antenna properties include gate size , routing area and diode protection for all the ports of the macro. These properties can be used by the tool for checking antenna rules on the net connected to the macro pins.

FLOW CHART:
Copy &open cell

Metal fill cell

Change name & save cell

Write GDSII file

Write Verilog netlist

Check for DRC runset & set the DRC-engine

Create ILM Model

Set map files in existing Write SDC file

Create macro view

Run DRC signoff Write SBPF file after RC extraction

Extract Antenna properties

Write DEF file