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Instruction Cycle
Fetch
1.
2.
3.
Fetch an instruction from memory Decode the instruction to determine the operation Fetch data from memory if necessary
Execute
4. 5.
Perform the operation on the data Store the result in memory if needed
Contd..
Program Counter (PC) = Address of instruction Instruction Register (IR) = Instruction being executed Accumulator (AC) = Temporary Storage
Contd..
Fetch the instruction from the memory Address in the Program Counter register Program Counter (PC) holds address of next instruction to fetch Increment the Program Counter Unless told otherwise Instruction loaded into Instruction Register (IR) Decode the type of instruction Fetch the operands Execute the instruction Store the results
Interrupts
Changing Program Flow
Interrupts
Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Program
Timer
I/O
Hardware failure
Interrupt Cycle
Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program
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Multiple Interrupts
Disable interrupts
Processor will ignore further interrupts whilst processing one interrupt Interrupts remain pending and are checked after first interrupt has been processed Interrupts handled in sequence as they occur
Define priorities
Low priority interrupts can be interrupted by higher priority interrupts When higher priority interrupt has been processed, processor returns to previous interrupt
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References
Chapter 1, Ytha Yu and Charles Marut, Assembly Language Programming and Organization of IBM PC Chapter 3, William Stallings, Computer Organization & Architecture
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