UNCONVENTIONAL TRANSISTOR SIZING FOR REDUCING POWER ALLEVIATES THRESHOLD VOLTAGE VARIATIONS

Azam Beg, Valeriu Beiu, and Walid Ibrahim

Faculty of Information Technology, United Arab Emirates University, Al Ain 17551, Abu Dhabi, UAE E-mail: {abeg, vbeiu, walidibr}@uaeu.ac.ae

AbstractDigital circuits can be synthesized with only NANDs or NORs, while delay and power can be quite different. Scaling transistors increases their sensitivity to variations and in particular to threshold voltage variations (VTH). Sizing transistors trades delay versus power, while unconventional sizing (e.g., L > Lmin, W/L < 1, fine-grained increments, multifinger FETs) was proposed recently for reducing power and also VTH. Using Monte Carlo simulations we perform an analysis of how sensitive the output voltages of NAND-2 and NOR-2 are to increasing L over Lmin, and examine how such sizing affects delay, power, and power-delay-product of these two gates.

consumption. Yet another adverse result of scaling is the increased sensitivity to noises and variations, which has a negative effect on both reliability and performances. In particular, as dimensions are scaled, it is becoming harder to controls the spread of the threshold voltages (VTH) across a large chip (intra-die variations). For standard CMOS, the variations of VTH occur mainly due to the randomness of the number and the location of the dopant atoms. The results in [3] have shown that VTH can be approximated as normally distributed, with a standard deviation of:
VTH 3.19 10 8
0.4 tox N A

1. INTRODUCTION
It is well-known that digital circuits can be designed using only NAND-2 or NOR-2 gates, and also that these two gates exhibit quite different characteristics. A standard CMOS NAND-2 gate has two pMOS in parallel, while a NOR-2 gate has two pMOS in series (see Fig. 1). Since a pMOS is weaker than an nMOS of the same size, VLSI designers increase the width of the pMOS (WpMOS) when balancing the pMOS and nMOS stacks, for equalizing the rise and fall times and maximizing the static noise margins (SNMs). This standard CMOS sizing approach increases the area of the pMOS over that of the nMOS, and the power consumption of the NOR2 over the NAND-2. This is one reason why VLSI designers tend to rely more on NAND-2 and less on NOR-2. In spite of these disadvantages, NOR-2 tends to be more reliable than NAND-2 [1], [2], a fact that can simplistically be understood as larger transistors are less sensitive to variations. The steady reduction of the transistors dimensions has resulted in a substantial increase of the performances and functionalities of modern VLSI circuits. However, the deep scaling of CMOS transistors has also caused an increase in leakage power, and containing leakage became paramount for reducing power
978-1-4673-0738-3/12/$31.00 2012 IEEE
429

Leff Weff

(1)

where tox is the oxide thickness, NA is the channel doping, Weff is the effective channel width, and Leff is the effective channel length. VTH can be contained by increasing either Leff or Weff, or both. For standard CMOS sizing, VLSI designers start with LnMOS = LpMOS = Lmin. Then WnMOS and WpMOS are upsized to balance the pMOS and nMOS stacks. Doing so leads to WpMOS > WnMOS, and makes the area of pMOS (WpMOSLmin) larger than the area of nMOS (WnMOSLmin). This makes the pMOS more reliable than the nMOS, which are less reliable than the pMOS to start with (due to different tox and NA [4], [5]). Unfortunately, this means that despite increasing the pMOS, there is almost no improvement of the overall gates reliability which is affected by the less reliable nMOS [1], [2]. One way of mitigating this, and enhancing the reliability of a CMOS gate, is represented by unconventional sizing methods, including methods based on upsizing L. This paper evaluates and compares two standard CMOS gates: NAND-2 and NOR-2, when L is upsized beyond Lmin. Monte Carlo (MC) simulations were used to study the effects VTH have on the output voltage levels, delay, power and power-delay-product (PDP). The reset of the paper is organized as follows. Related work is presented in Section 2, followed by results and

(a)

(b)

Fig. 1. CMOS gates topology: (a) NAND-2; (b) NOR-2.

Fig. 2. Test circuits for NAND-2 and NOR-2 gates.

analyses in Section 3, and concluding remarks in Section 4.

2.

RELATED WORK

The effects of variations have been the subject of many publications. Mukhopadhyay and Roy [6] presented analytical models for estimating variation effects in 50 nm CMOS. Taylor and Fortes [7] showed how changes in VTH affect the output voltage levels of an inverter and a NAND-2 gate. Agarwal and Nassif [8] presented a detailed study of techniques for parameter measurements on silicon, in order to correlate analytical models with actual implementations. Asenov [9] studied VTH in MOS transistors due to random dopants (location and count), while later including line edge roughness, polysilicon granularity and oxide thickness [10]. The conclusions were that random dopants were the dominant parameter affecting VTH. Ibrahim and Beiu [11] studied the effects VTH play on NAND-2 gates using Bayesian networks. Remarsu and Kundu [12] characterized VTH in thermal sensors operating at different temperatures, while Tang et al. [13] incorporated a simplistic transistor model in a statistical simulation engine for the purpose of estimating the delay, power, and noise effects. VTH have emerged as very important, and not only due to scaling, but also for allowing to reduce power by reducing VDD to near-VTH or into sub-VTH. Unconventional sizing methods have been proposed to alleviate the effects of VTH, hence directly affecting performances (scaling) and power (reducing VDD). Unconventional sizing methods normally rely on increasing L. This was suggested for radiation hardened designs [14], and later advocated for sub-VTH designs [15][17]. Recently it was argued that increasing L leads to benefits for above-VTH as well [18], [19], with [20] showing that unconventional sizing changing the W/L

aspect ratio (including increasing L) is beneficial for reducing power and increasing reliability over the whole voltage range. Changing the W/L aspect ratio has been known and used in analog designs [21] as better matching can be obtained without consuming additional area. Another unconventional sizing is based on using multifinger FETs of minimum size [22], which allows increasing L in increments of Leff (similar to the discrete sizing of FinFETs).

3. RESULTS AND ANALYSIS

A MC-based analysis of standard CMOS NAND-2 and NOR-2 in 16 nm high performance (HP) v2.1, metal gate, high-k, and strained-Si predictive technology model (PTM) [4], [5], was performed using NG-Spice v.24. First, NAND-2 and NOR-2 with a fan-out of four were used (see Fig. 2). A square-wave (50% duty-cycle) of 0.1 GHz was used as stimuli, with VDD (700 mV) temperature (27C) set at nominal. All NAND-2 have one input at VDD, while all NOR-2 have one input at GND. A standard CMOS NAND-2 has LnMOS = LpMOS = Lmin, WnMOS/LnMOS = WpMOS/LpMOS = 4, while a standard CMOS NOR-2 has LnMOS = LpMOS = Lmin, WnMOS/LnMOS = 2, and WpMOS/LpMOS = 8 (better balancing is possible). For each circuit 1000 MC simulations were performed to capture the effects of VTH, which was estimated using eq. (1), and then incorporated in the PTM model. Fig. 3 presents the output voltages (Vout) of the two gates when the output logic should be 0, assuming that the input signal has 10% variations, i.e., input logic 1 is set at 630 mV (90%VDD) and input logic 0 is set at 70 mV (10%VDD). As we proceed increasing the channel length L (simultaneously for all nMOS and pMOS) from Lmin to 1.1Lmin, 1.2Lmin, and 1.4Lmin, we observe a clear shifting of Vout closer towards GND. Additionally, a sharpening of the histograms suggests that the distributions of Vout

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150 Count Count 100 50 0 -5 10

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150 L 1.1xL 1.2xL 1.4xL 10 10 NOR Vout [V]

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L 1.1xL 1.2xL 1.4xL 10 10 NOR |VDD - Vout| [V]

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10

-2

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150 Count Count

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150 100 50 0 -5 10
-4 -3 -2

100 50 0 -5 10

10

10 NAND Vout [V]

10

10 10 NAND |VDD - Vout| [V]

10

Fig. 3. Vout variations for logic 0 for transistors having different Ls: NOR-2 versus NAND-2.

Fig. 4. Vout variations for logic 1 for transistors having different Ls: NOR-2 versus NAND-2.

are getting tighter. For standard CMOS sizing, the NOR-2 has about 20 lower average Vout (0.1 mV) than the average Vout of the NAND-2 (2 mV). With only 10% increase in L, both gates show an order of magnitude improvement (drop) of the average Vout. For 20% and 40% upsizing of L, NOR-2 exhibits only marginal improvements, while NAND-2 sees Vout still improving. These suggest that the SNMs (which are related to reliability) are being improved. Fig. 4 shows the histograms for |VDD Vout| of NAND-2 and NOR-2 when the output logic should be logic 1, assuming that the input signal has 10% variations. In this case NOR-2 exhibits larger variations on Vout than NAND-2. Output voltages for both NOR-2 and NAND-2 get better as L is increased, albeit with different
700 600 500 Vout [mV] 400 300 200 100 0 0 Vout [mV] L = 1.0 700 600 500 400 300 200 100 0 NOR Vout = LO NAND Vout = LO NOR Vout = HI NAND Vout = HI L = 1.1

50 % nominal VTH

100

50 % nominal VTH

100

Fig. 5. Vout versus VTH variations for NAND-2 and NOR2 gates: L = Lmin (left) and L = 1.1Lmin (right).
700 600 500 Vout [mV] 400 300 200 100 0 Vout [mV] L = 1.3 700 600 500 400 300 200 100 0 NOR Vout = LO NAND Vout = LO NOR Vout = HI NAND Vout = HI L = 1.5

starting points and rates of return. Next, we looked into how tuning (modifying) VTH (e.g., using body bias) would affect Vout, in conjunction with changing L. Fig. 5 shows that for standard CMOS sizing both NAND-2 and NOR-2 start failing if VTH drops to 60%VTH. Here failure is defined as a Vout outside the 10%VDD margin (i.e., either above 70 mV or below 630 mV). If L = 1.1Lmin, both gates work down to 40%VTH (see Fig. 5), while if L = 1.5Lmin both gates work even at 20%VTH (see Fig. 6). We have also explored how delay, power and PDP for NAND-2 and NOR-2 vary when transistors are subjected to VTH tuning within 20%. The delays for both gates reveal nearlinear relationship to L (see Fig. 7). NOR-2 delays tend to be somewhat higher than NAND-2, even for standard CMOS sizing. With increasing L the divergence between the delays of the two gates is widening a bit. Power consumption for both gates reduces with increasing L (see Fig. 8). The power consumption of the NAND-2 remains consistently slightly higher than that of the NOR2, for all the VTH values considered (nominal and 20%), irrespective of L. Finally, the PDPs for both NAND-2 and NOR-2 show an increasing trend when L > Lmin, but both gates achieve very similar PDPs for all the cases considered here (see Fig. 9).

4. CONCLUSIONS
In this paper, we have shown how much increasing L > Lmin (e.g., in increments of Leff) could reduce the undesirable effects VTH play on Vout for NAND-2 and NOR-2. With minor upsized L, P is also reduced while minimally increasing the area. We intend to investigate how upsizing L affects the delays of larger circuits, and how

50 % nominal VTH

100

50 % nominal VTH

100

Fig. 6. Vout versus VTH variations for NAND-2 and NOR2 gates: L = 1.3Lmin (left) and L = 1.5Lmin (right).

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3 2.5 2 Delay [Sec] 1.5 1 0.5 0

x 10

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x 10

-10

NOR 0.8*Vthnom Vthnom 1.2*Vthnom

[6]

[7]
1.2 x Lmin 1.4

1.2 x Lmin

1.4

0 1

Fig. 7. Delay of NAND-2 and NOR-2 versus L.

5 4.5 4 3.5 Power [W] Power [W] 3 2.5 2 1.5 1 0.5 0 1 1.2 x Lmin 1.4 x 10
-7

[8] [9]

NAND

5 4.5 4 3.5 3 2.5 2 1.5 1 0.5

x 10

-7

NOR 0.8*Vthnom Vthnom 1.2*Vthnom

[10]

0 1

1.2 x Lmin

1.4

[11] [12]

Fig. 8. Power of NAND-2 and NOR-2 versus L.

2 1.8 1.6 PDP [W-sec] 1.4 1.2 1 0.8 0.6 PDP [W-sec] x 10
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NAND 2 1.8 1.6 1.4 1.2 1 0.8

x 10

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[13]

[14] [15] [16] [17]

1.2 x Lmin

1.4

0.6 1

1.2 x Lmin

1.4

Fig. 9. PDP of NAND-2 and NOR-2 versus L.

different input vectors affect both timing and power consumption. AcknowledgementsThis research was partly funded by Intel (2011-05-24G), SRC (2011-RJ2150G), and UAEU (NRF RSA 1108-00329 and NRF RSA 1108-00451). References
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