The Eighth International Conference on Electronic Measurement and Instruments

ICEMI2007

Development of Image Processing System Based on DSP and FPGA

Duan Jinghong, Deng Yaling Liang Kun
(School of Computer Science and Engineering, Xian University of Technology, Xian 710048 China)

Abstract: Real-time image processing system is widely used in many field, it is required to have high speed. In order to satisfy the demand, an image processing system structure based on DSP and FPFA is presented, that is DSP is used as advanced image processing unit and FPGA as logic unit for image sampling and display. The hardware configuration and working principle is introduced firstly, and then some key problems which include of image data stored mode, color space conversion and image transmission based on EDMA are described. Finally the program flowchart for developing image processing software is given. The developed system can acquire image, display image and make some image processing operations which include of geometry transform, orthographic transform, operations based on pixels, image compression and color space conversion. The developed system can meet the real-time requirement and has been used in our teaching. Keywords: real-time image processing, digital signal

This paper is organized as follows: section 2 first introduces the hardware configuration and its working principle of the system, which include of the designing idea, the image data stored mode and the color space. The image transmission method between DSP and FPGA is discussed in section 3. Section 4 gives the program flowchart for developing the image processing software based on the hardware. Finally the paper is concluded in section 5.

2 Hardware Configuration and Working Principle of the System

2.1 hardware configuration For real-time image processing system, it needs high speed because of mass image data, so we can use DSP to solve this problem. On the other hand, FPGA has capable of flexible logic control, large memory and fast executing speed. So the real-time image processing system can be constituted by the combination of DSP and FPGA, that is DSP is used as executing image processing algorithms and FPGA as logic control unit for image sampling and display. According to this idea, the developed image processing is shown in Fig.1.The system is composed of TMSC6713 DSP board, video board, CCD camera and VGA display. (1) CCD camera is used as capturing image. (2) TMSC6713 DSP board is used as executing image processing algorithms. The CPU on the board is TI DSP chip TMSC6713 which is a high performance float digital signal processor with 255MHz.There are 1Mbits RAM, 8Mbytes with 32bit exterior expanded memory SDRAM, 512Kbytes Flash, 4 user accessible LEDs and 4 DIP switches.

processing (DSP), field programmable gate array (FPGA), expanded direct memory access (EDMA)

1 Introduction
Image processing has been used in many fields, such as industry, military, medical image processing and so on. But most of the system is developed based on PC, it cant meet the requirement for real-time and high speed in some occasions, so the image processing and transmission system is increasingly developed along with the development of electronic technique, especially DSP and FPGA[1,2]. This paper introduces an image processing system based on DSP and FPGA. In the system the TMS320c6713 DSP is used as advanced image processing and FPGA as logic unit for image sampling and display.

1-4244-1135-1/07/$25.00 2007 IEEE.

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The Eighth International Conference on Electronic Measurement and Instruments

ICEMI2007

(3) Video processing board is shown as dashed frame in Fig.1, it consists of foreside decoding chip SA7111, FPGA, SDRAM and back-end coding chip AL250. The function of SA7111 is to change analog video signals from CCD into digital signal and the image data with the format of YUV4:2:2 are stored in

SDRAM. The image data after processed by DSP are sent to AL250 which can convert interlaced TV signal (NTSC/PAL SECAM) into non-interlaced RGB format
for CRT monitors. FPGA is used as logic unit for

(4) VGA display is used as displaying output image from AL250.

SDRAM (4Mh16bit)

CCD video camera

foreside decoding (SA7111)

FPGA

back-end coding (AL250)

VGA display

C6713 DSP board

Fig.1 hardware configuration of the image processing system

2.2 system working principle The system working involves image samples, image store, image transmission, image processing and image display. They are described detailed as follows: (1) Image acquisition is obtained by CCD camera. The output of the CCD camera is analog signals of PAL SEAM, it is transformed to digital image signals with YUV4:2:2 format by video decoding chip SA7111. (2) Image transmission between DSP and FPGA is gotten through EDMA method. The video data are first stored into OUTFIFO in FPGA, at the same time DSP is noticed to take away one row data from FIFO by interrupt signal caused by synchronization signal. After the image data are processed by DSP, they should be sent to video board. The transmission method is EDMA, the detail of this method will be discussed in section 3. (3) The third problem is the image store. A frame image data are divided into odd filed and even field and the start address of image store is 0x80000000. The image data format is YUV4:2:2, the stored order is shown in Fig.2, it can be seen from Fig.2 that every pixel has a Y data and two adjacent pixels only share
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one group of UV data. The image size is 625h720, so the data size of one row is 720h2Bytes. Because of the used color space is RGB in
Y data

10

11

U data V data Fig.2 YUV data order of one row image

computer, so the image data with YUV4:2:2 Format named as YCbCr color space should be transformed. The transform equations between RGB and YCbCr are as follows:

Y 0.257 Cb 0.148 Cr 0.439

R .164 G 1 1.164 B 1.164

0.504

0.098

 0.291 0.439  0.368  0.071

R 16 G  128 B 128

(1)

1.596

 0.391  0.813 2.018 0

16 CY  128  Cb 128 r

( 2)

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The Eighth International Conference on Electronic Measurement and Instruments

ICEMI2007

Gray image are often used in image processing, it can be got by setting Cb and Cr as 128 in the above equation (2). (4) The acquired image can be processed by software implemented by DSP. The detail of image processing software will be described in section 4.

Optional parameter(OPT) Source addressSRC Frame/Array count (FRMCNT) Element count (ELECNT)

Destination address (DST) Frame/Array index Element index (ELEIDX) Link address (LINK)

3 Image Transmission Based on EDMA

On considering the speed, EDMA method is used to transmit image between DSP and FPGA. It is a peculiar access way for C671X and there are 16 channels for C6713. The image data can be transmitted directly by EDMA controller but not CPU. EDMA controller include of four parts[4]: (1) event and interrupt handle register; (2) event encoder; (3) parameters RAM; (4) hardware address generator. The EDMA event is captured by event register and it can be distinguished by event encoder if there are many events occurring at the same time. The transmission parameters are stored at parameters RAM and are sent to hardware address generator to generate the addresses for reading and writing operations. There are two problems of using EDMA. The first is setting the DSP interrupt registers which include of CORE register, IER register, CIER register, EER register and ECR register. In the developed system, the 6th channel is used to transmit image from DSP to FPGA and the 7th channel is inverse, the image transmission is touched off by the EDMA transmission finished interrupt signal. So the correlative bit value of the above described register is set as follows: (1) The 0th bit of CORE register is set as 1 to enable exterior interrupt; (2) IER register should be set enabling EDMA interrupt; (3) The bits corresponding to interrupt 6 and 7 of in CIER register should be set as 1; (4) The 6th and 7th bit of EER register are all set as 1 in order to capture the event; (5) The 6th and 7th bit of ECR register are all set as 1. The second problem is the transmission parameters setting. The structure of parameters RAM is shown in Fig.3, the detailed parameters meaning can find in reference [4].
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(FRMIDX) Element count reload (ELERLD)

Fig.3 stored structure of parameter RAM

For our system, the image size is 625h720, 1D transmission is adopted by image source and destination. The source address is 0x80000000 for channel 6 and 0xa0000018 for channel 7, the destination address is 0xb0000014 for channel 6 and 0x80000000 for channel 7. So the parameters of channel 6 are: (1) OPT: 0x49160003; (2) SRC: 0x80000000; (3) FRMCNT and ELECNT: 0x027002D0; (4) DST: 0xb0000014; (5) FRMIDX and ELEIDX: 0x06c00002; (6) ELERLD and LINK: 0x00000210. For channel 7, the parameters are: (1) OPT: 0x48200003; (2) SRC: 0xa0000018; (3) FRMCNT and ELECNT: 0x027002D0; (4) DST: 0x80000000; (5) FRMIDX and ELEIDX: 0x03600001; (6) ELERLD and LINK: 0x00000630.

4 Program Flowchart and the Software Function

The reset button S2 in video board is used to control the image sampling, a frame image can be got when it is pressed. The 0th position of SW1 switch in DSP board is used to start de DSP program for processing the acquired image. Fig.4 gives the program flowchart for developing image processing software. From Fig.4, we can see that all the processes except the algorithms for image processing are the same. So the software development is to write the image processing program. The functions of the developed software are as follows: (1) image geometry transform, which include of transforms of mirror, translation, zoom and rotation. (2) image orthographic transform, which include

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The Eighth International Conference on Electronic Measurement and Instruments

ICEMI2007

of DCT transform and wavelet transform. (3) image pixels operation, such as negative image, image enhancement, edge extraction and so on. (4) image compression based on JPEG. (5) color space conversion, such as RGB and YCbCr conversion, color image and gray image conversion.
Begin

different level algorithms and large flexibility for expanding the system. It can meet the requirements for real-time image processing system. Acknowledgments This paper has been supported by the experiment technique foundation of Xian University of Technology. Reference
[1] H.X. Zhou, R. Lai, S.Q. Liu. A New Real Time Processing

Set the transmission parameters of EDMA

System for Imaging Signal Based on DSP&FPGA[J]. Infrared Physics & technology. 2005,46(4):277-281. [2] J. Batlle, J. Marti, P. Ridao. A New FPGA/DSP-Based

Open interrupt 7 for preparing image sampling

Parallel Architecture for Real-time Image Processing[J]. Real-Time Imaging, 2002,8(5):345-356 [3] Image Processing Board for 6713DSK [M]. Beijing Techshine Technology CO.,Ltd, 2004:1-12

Press the reset button to get a frame image

[4] F.H. Li, F. W. The Principle and Application of TMS320C000 Series DSP[M]. Publishing House of Electronics Industry, 2003:390-408

Get the status information of 0th position of SW1

Geometry transform

[5] C.Qi, Y.H. Chen, T.S. Huang. The Real-time Image Processing Technique Based on DSP[J]. Wuhan University Journal of Natural Sciences, 2005,10(6):1025-1029

N
Pressed?

Orthographic transform

Author Biography
Duan jinghong: received her B.Sc. degree from Xian

Y
The algorithms for Processing the acquired image in DSP

Image pixel operation

Polytechnic University, China, in 1991. From 1999 she is an engineer of School of Computer Science and Engineering in Xian University of Technology. Her current research interests

Image compression Open interrupt 6 for image transmission from DSP to FPGA Color space End conversion based on JPEG

include embedded system and digital image processing.

Fig. 4

program flowchart

5 Conclusions
The proposed image processing based on DSP and FPGA has the advantages of high speed, powerful image processing capability of easily implementing
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