Faculty of Electrical and Electronic Engineering Semester I, Session 2013/2014 PROGRAMMABLE ELECTRONICS MEE10203 Assignment (12% of total marks)

Important dates: 1. 2. 3. 4. Discussion / Progress 1: 8/10/2013 (week 4), Tuesday, 1.00 pm Discussion / Progress 2: 22/10/2013 (week 6), Tuesday, 1.00 pm Discussion / Progress 3: 12/11/2013 (week 8), Tuesday, 1.00 pm Discussion / Progress 4: 26/11/2013 (week 10), Tuesday, 1.00 pm

OVERVIEW: 1. Before attempting homework assignments, you should complete Quartus II tutorials. This is accessed from the Quartus II software under the Help -> Getting Stated Tutorial or Help -> PDF Tutorials menu. 2. The textbook Fundamentals of Digital Logic with VHDL Design, second edition, by S. Brown and Z. Vranesic offers an additional tutorial, located in Appendix B, on the Quartus II software. 3. Chapter 1 of the course textbook Rapid Prototyping of Digital Systems: SOPC Edition, by J. Hamblen, T. Hall and M. Furman gives an overview tutorial. 4. Finally, the Altera website offers extensive documentation on the Quartus II software. 5. Suggested reading would include the Quartus II Software Quick Start Guide, the Introduction to Quartus II Manual, and the Quartus II Development Handbook. 6. All this documentation is available at http://www.altera.com/literature/lit-qts.jsp. Make sure you read documentation for Quartus II 11.0.

PART A 1. Perform an Internet search and find the 74154 4-to-16 decoder datasheet. From the functional description given in the datasheet, write a VHDL description for a 74154 4-to-16 decoder. Use only STD_LOGIC and STD_LOGIC_VECTOR data types in constructing your design. Enter the design into the Quartus II software and verify the syntax correctness by compiling the design. The design should compile without error. Use suggested style guidelines for your VHDL source code. Turn in both the datasheet and the VHDL source. 2. Write a VHDL description for a 4-bit binary-to-gray code converter. Enter the design into the Quartus II software and verify the syntax correctness by compiling the design. Use suggested style guidelines for your VHDL source code. The design should compile without error. 3. Write a VHDL description for a 4-bit gray-to-binary code converter. Enter the design into the Quartus II software and verify the syntax correctness by compiling the design. Use suggested style guidelines for your VHDL source code. The design should compile without error. 4. Implement the following truth table-based design in VHDL code. A B C D Y1 Y2 000010 000110 001010 001110 010010 010110 011010 011110 100010 100101 101001 101111 110010 110110 111010 111110

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Verify the correctness of the entered design by simulation using the Altera Quartus II software. Include a functional timing simulation, a Vector Waveform File (.vwf), in your solution verifying the correctness of the design. 5. Perform a functional simulation of the designs for problems 7, 8, and 9. Submit a Vector Waveform File (.vwf) verifying the correctness of the design for each problem. (8/10/2013, week 4)

PART B Write a Word document discussing the following projects. Submit also the VHDL codes for each task. Demonstrate the working projects to the instructor (and class). If you are not able to complete this assignment by the specified date, submit a progress report documenting your work to that time. 1. Design and implement a DE2/DE1 project that demonstrates a binary to BCD converter. Use the switches SW[15:0] to define the input binary value and the seven-segment displays to show the resulting decimal equivalent. For example, if the first five switches are on: 0x1F, the sevensegment display should read 31. (22/10/2013, week 6) 2. Modify the binary to BCD converter project so that it handles and displays signed values. (22/10/2013, week 6) 3. Design and implement a DE2/DE1 project that generates simulated quadrature encoder pulses. Use SW[15:0] to set the quarter-period. Use the GPIO pins for the output. Use SW3 to change direction. In one direction, the pulse sequence is 00, 01, 11, 10. In the other direction the pulse sequence is 00, 10, 11, 01. (12/11/2013, week 8) 4. Design, implement, and test a DE2/DE1 project that handles quadrature encoder pulses using an up/down counter. Start with A and B low. If A goes high first, increment the count. If B goes high first, decrement the count. Use the results of the previous exercise to provide sample encoder pulses. (12/11/2013, week 8) 5. Design, implement, and test a DE2/DE1 project that performs a simple memory interface controller (implemented using a Finite State Machine, FSM) based on the following specifications: a. The controller interfaces a microprocessor and a memory buffer. The controller is used to enable and disable the write enable (WE) and the output enable (OE) signals of a memory buffer during read and write transactions, respectively. b. The inputs to the controller are signal RDY and RW, which are outputs of a microprocessor. c. A new transaction begins with the assertion of RDY following a completed transaction (or upon a power-up reset). d. One clock cycle after the commencement of the transaction, the value of RW determines whether it is a read or write transaction. If RW is asserted, then it is a read cycle; otherwise it is a write cycle. e. A cycle is completed by the assertion of RDY, after which a new transaction can begin. WE is asserted during a write cycle, and OE is asserted during a read cycle. (26/11/2013, week 10)

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