SUMMARY

Primary Skills FPGA, Verilog , VHDL, Simulation, Synthesis, RTL coding ,EDA EDA tools, PCB Design , front end VLSI cycle, DFT, Hardware design, Embedded software, Verification, Digital Design, analog design. Extensive experience in digital logic design, RTL coding, synthesis, timing closure, simulation , design verification(model sim) and FPGA design have got more than 8+yrs +yrs of experience in the field of VLSI ,ASIC and embedded design. design Worked in logical design for 5+yrs & rest in along with FPGA,PCB FPGA,PCB design. Moreover i have done my academic project in VLSI field. Proficient with component design, coding RTL & Behavioral using Verilog and VHDL. VHDL Proficient with developing test environment for functional verification. Proficient in developing appropriate test vectors using Verilog, VHDL and c language. Proficient in writing fully automated test benches, Validation , application engineering. Experience with synthesis and optimization of Verilog/VHDL code Experience with FPGA implementation with Xilinx , ALTERA. ALTERA In-depth working knowledge of ATM, IP, MPLS, SONET and related network protocols, and VLSI devices and theory, ASIC design, CPU architecture, PCI, DSP and firmware development Others: Mentor Graphics DA, Autologic II, Visual HDL. HDL Languages: C, C++, Unix, perl scripting . Operating Systems: Windows . Networking Protocols: TCP/IP, UDP, ICMP, NIS, NFS, RIP, OSPF Microsoft Office products, especially Word and Power Point, Excel, and some experience using Macromedia Flash, and PhotoShop or Paint Shop Pro . SPICE,Others: PCI. SPICE PCI Revision Control: CVS. CVS Worked on PCB design Mentor Graphics Schematic Entry Tool Design Architect. Familiar with 8085 and 8086 Architecture. Familiar with 8085 Assembly Language. Familiar with micro processors, software languages C ,Vxworks, WinCE and Fortran. Fortran

Excelllent interpersonal skills, demonstrated ability, Good communication skills

SKILLS Digital logic design using Verilog, Verilog VHDL, VHDL,CMOS, user interface design Design verification - Full chip simulation, simulation Behavioral models development and checking. Synthesis -HDL coding, Code Checking, Code coverage, Scan insertion and ATPG, Static Timing Analysis, SDF Back-Annotation, ATPG Timing closure, DFTtools, DFT BIST, JTAG boundary scan,SOFTWARE EDA tools. Simulation Cadence VerilogXL, NCVerilog, NCVHDL, Synopsis VCS, Modelsim Synthesis Synopsis Design Compiler, XilinxXilinx-Foundation, Foundation, embedded simulation tools Scan Insertion and ATPGATPG- Tetramax Code Checking Modelsim, specman (DUT, testbenches, randomm verification etc),schematic entry, circuit simulation tools Timing Closure Synopsis PrimeTimer Behavioral model checking - Nanosim Other professional trainings and tools: current mirrors in MIXED SIGNAL DESIGN , MEMS, sensors ,SPICE , cryptographic algorithms, RF circuit design, wireless applications(CDMA,GSM, GPRS,802.11) ,DIGITAL SIGNAL PROCESSING(DSP) (DSP) ,CAD software,ALGORITHM experience, QUARTUSII, PCB layout design, Physical Compiler, PSPICE, Cadence Opus, Power Compiler, CMOS, ADC,DAC,Antrim AMS, Mentor Graphics ELDO/ADMS, Cadence Assura, Mentro Graphics Calibre. GENERAL Scrpting languages: perl Programming languages C,C++ Operating systems: WindowsXP, UNIX PROFESSIONAL EXPERIENCE SR. design engineer 05/200505/2005-still continuing continuing Implemented a simplified real-time Fast Fourier transform and a Frequency encoding methodology for digital broad spectrum receiver. Converted portions of the preliminary ASIC design into a Xilinx Virtex family FPGA for use in a prototype. Investigated techniques to enhance performance of the Monobit receiver. Designed simulations to estimate the optimum number of bits required in various modules keeping in mind reduction of hardware overhead, flexibility with

reconfiguration, high speed performance and improvements in two-tone dynamic range. Performed functional / logic verification, synthesis, clock-tree generation, scan insertion, power analysis, place and route, static timing analysis and crosstalk analysis for the digital back end design of 2.5 GHz mixed signal Monobit receiver. Designed a Floating Point Multiplier (FPM) . Developed a 'C' code to test The functionality of the FPM over a UART. UART Designed and implemented a FIR bandpass filter using VHDL . Studied the effect of order of the filter on its performance and the hardware utilization on the FPGA. FPGA [Virtex 2 Pro]. Designed a 32 bit ALU and tested the same by designing a ROM with the test vectors. [Virtex Virtex 2]. 2 Implemented physical layer RTL implementation, designed various modules like equalizer and tap estimation block in receiver . working on system integration and preparing micro architectures for various design modules also. Front end processing by using VerilogVerilog-HDL language specification, design, implementation, simulation and debugging of multiple FPGA (Xilinx Virtex II Pro/ProX)designs for their flagship Network Packet Pro/ProX) Processing / Network security product CS2000. Data converters can be thought of as the central cores of wireless-infrastructure systems. Complex signals must be digitized upon reception and converted to analog form for transmission(mixed signal design work). To meet the needs of present and future-generation(RF RF design) design wireless-infrastructure systems, analog-to-digital converters (ADC ADCs) DACs) ADC and digital-to-analog converters (DACs DACs must therefore perform at RF rates and with outstanding linearity. The AD9444 ADC and AD9779 DAC from Analog Devices are examples of high-speed data converters that are making both third-generation (3G) 3G) wireless systems and future-looking broadband wireless applications possible written testbenches / implementation code using Verilog and simulation/implementation scripts debugging and correction of third party code (Verilog) with insufficient and contradicting documentation available PCB DESIGN,board bring-up and lab debugging in close interaction with firmware DESIGN, and board designers CAD/EDA tool support, license administration / configuration and consulting

tools used: ModelSim SE, Synplify Pro, Mentor Precision Synthesis, Xilinx Foundation tool flow, Synopsys VirSim/VCS,

Senior Design Engineer 05/200405/2004-04/2005 Project title : RF/channel coding/carrier recovery/timing recovery/design on WiWi-Fi

The module providing network security ( encryption) part by using DES algorithm on VHDL VHDL, DL working on carrier recovery and timing recovery at the moment, with FPGA exp. Knowledge of Receiver Circuit System, Oscillator and PLL and Synthesis design over the frequency range 2.4GHz,Knowledge of RF Test methods and test equipments used in Receiver Circuit ,including mixed signal and analog design System design Principles of Digital modulation schemes such as QAM, QPSK and OFDM

Project title : SOFTWARE DESIGNED RADIO(SDR) project work is based on SOFTWARE DESIGNED RADIO .this innovative product has a transmitter and receiver which follows the SDR design approach .at the transmitter, the base band processing is performed on a xilinx Spartan 3 processor. Implemented using Verilog front end processing .perl perl scripting has been also done. Modified FPGA designs on altera and quartus and FIFO HW for professional MPEG-2 digital-video archiving system Modified C++ firmware to upgrade performance of remote sanitation control system Design of isolated temperature monitor PCB for HV environment (medical equipment)

Design engineer aug2003 aug2003-april2004 Project title: DEVELOPMENT of a new 3D range camera system for application in driver assistance system Transceiver algorithm Developed RTL model for the Serial Transmission Protocol (STP STP) STP and Serial Receiver Protocol (SRP) using VHDL. VHDL Developed controller module for the AD9826 Signal processor using VHDL. VHDL Image Processing Calculate the distance from the source (3D camera) to the object and to determine the gray value of the pixel using TMS320C6201 DSP Controller. Developed RTL model for data transmission module from the DPDP-RAM to the Frame grabber (FG). (FG) Control algorithm is performed using LabVIEW. Implemented VI that generates a Pseudo-noise sequence with phase shifting algorithm and transmits the PN-sequence to the FPGA chip using LabVIEW. PN

Synthesized modules using Xilinx XST. XST Performed functional verification for the RTL core using ModelSim. Team member in the design of PMD (Photonic Mixer Device) camera. Leadership Qualities: Planned and organized various discussions and meetings Transferrable Skills: Hardware Oriented Software programming, Analytical skills, Decision making strategy, Time awareness skills. Project title : IMPLEMENTAION OF AES algorithms Project work is based on VLSI implementation of AES (Advanced encryption standard) cryptographic algorithms. It is basically an 8-bit field programmable gate array (FPGA) (FPGA implementation of 128 bit block and 128 bit key advanced encryption standard, and the basic algorithms used are Rij ijndal and Serpent. Language used is Verilog HDL ij Engineering Consultant (July 2002 2002 july2003 july2003) FPGA, digital, and analog video hardware design for avionics display systems (VHDL, Synplicity, ModelSim, Actel Designer)

Project title ee-ASICimplementation (eASIC is a new type of ASIC. ASIC It is an array in which each cell resembles an FPGA cell (a LUT and a flip-flop), but the interconnections are fixed at manufacturing. Developed embedded IP cores and studied the ECO problem. Complete Hardware design of interfaces to Linotype Hell / Heidelberg Reprograhic Scanner/Recorder using INMOS Transputer and XILINX technology (XC3090, XC4010), XACT, XACT Dash, Workview Project management of the schematic-converter Dash2View (Dash -> Workview) Developing test programs using Pascal Pascal Project title :Multipurpose programmable device by using VHDL Objective of project work is based on VHDL as programmable multipurpose device , it is designed especially to be compatible with the 8085 micro processor. This device consists of two sections : the first is 256 bytes of R/W memory and the second is a programmable I/O .Functionally these two sections can be viewed as two independent chip the I/O section includes two 8-bit parallel ports(A and B),one 6-bit port C and a timer. . Tools Used: Verilog, Verilog, Xilinx, Virtuoso and Cadence tools. High-level design, physical design and simulation of various digital ASIC's ASIC using Cadence tools.

3232 Register file Design: A 3232, 4-port register file was designed, 4 simulated and tested. 5:32 bit decoders, write data drivers were added to the design. SRAM: SRAM Designed a 4-port static ram cell which was used in the 3232 Register file design. SRAM is capable of 8 simultaneous reads or 4 simultaneous writes. Ring Oscillator Design: This project involves the design of a CMOS ring oscillator which was used to drive a load of 100 inverters with sized drivers. 8-bit Adder -- Designed an 8-bit adder using automatic layout generation 8 with silicon ensemble, cadence synthesizer, Irsim and standard cells). 6:64 Decoder Decoder -- 6:64 bit decoder was designed using NAND and NOR gates as a tree structure to increase the speed. Duration : sep2001 sep20012001-july:2002 july:2002 Project title : CENTRAL PROCESSINF UNIT &memory design Object To design 16 bit microprocessor contains register array of 8 ,16-bit registers, an ALU, ALU a shifter, a program counter, an instruction register, a comparator, an address register, and a control unit. VLSI implementation of whole design by using VHDL ,modelsim verification Study of various IEEE based research documents for utilization purpose Duration : feb2001 feb20012001-aug:2001 aug:2001 Project title : simulation of correlator by using VHDL Object Correlation is a computational technique in which an incoming signal is compared to a previously calculated reference which is known as filter filter, ilter correlation is sometimes known as matched filtering. It is an important function in processing video images in radars , receivers etc. Implemented by using VHDL simulation done by using Xilinx tools Duration: june2000-jan2001