Microprocessors and Computer Systems

Part 7 8088 Pin Assignment

(*Brey: ch9; Hall: ch7; Triebel: ch7)
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Pin Layout of the 8088 Microprocessor

Min Mode
GND A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc A15 A16/S3 A17/S4 A18/S5 A19/S6 SS0 MN/ MX

(Max Mode)

Nine pins have functions which depend on the state of MN/MX :

MN/MX =high -- 8088 operates in MINIMUM MODE

(High)

8088 CPU

RD HOLD
HLDA WR IO/ M DT/R

MN/MX =low -- 8088 operates in MAXIMUM MODE

Minimum mode: - 8088 directly generates the control signals necessary for accessing memory and IO ports. Maximum mode:- external support chips are used to generate control signals; the processor can work in a system containing other processors
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(RQ / GT0 ) (RQ / GT1) (LOCK ) (S2) (S1 )

DEN ALE
INTA
TEST READY RESET

(S0 ) (QS0) (QS1)

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Signals Common to Both Minimum and Maximum Modes

Name AD7 AD0 A15 A8 A19/S6 A16/S3 MN/MX RD TEST READY RESET NMI INTR CLK VCC GND Common signals Function Address/data bus Address bus Address/status Minimum/maximum Mode control Read control Wait on test control Wait state control System reset Nomaskable Interrupt request Interrupt request System clock +5V Ground
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Type Bidirectional, 3-state Output, 3-state Output, 3-state Input Output, 3-state Input Input Input Input Input Input Input Input
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8088

Unique Minimum-mode Signals

Minimum mode signals (MN/ MX = VCC ) Name Function Type HOLD Hold request Input HLDA Hold acknowledge Output

WR
IO/M DT/R DEN SSO

Write control IO/memory control Data transmit/receive Data enable Status line Address latch enable Interrupt acknowledge
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Output, 3-state Output, 3-state Output, 3-state Output, 3-state Output, 3-state Output Output
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ALE
INTA

Unique Maximum-mode Signals

Maximum mode signals (MN/ MX = GND) Name Function Type Request/grant bus Bidirectional RQ/ GT1, 0 access control Bus priority lock Output, LOCK control 3-state Output, S2 - S0 Bus cycle status 3-state Instruction queue Output QS1, QS2 status

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Maximum-Mode of 8088
INIT S0 S1 S2 CLK Vcc GND Interrupt interface INTR TEST NMI RESET LOCK
S0 S1 S2

Multibus BUSY CBRQ BPRO BPRN BREQ BCLK IOB

CRQLCK RESB
SYSB/RESB

8289 LOCK Bus arbiter CLK AEN IOB

CLK

ANYREQ AEN

CLK AEN IOB S0 8288 S1 S2 Bus DEN controller DT/R ALE

8088 CPU

MRDC MWTC AMWC IORC IOWC AIOWC INTA MCE/PDEN ALE DT/R DEN A0-A15, A16/S3-A19/S6 D0-D7 RD READY QS1,QS0

MN/MX

Local bus control RQ/GT1 RQ/GT0 ELEG 3230 - Part 7 6

Maximum-Mode of 8088
a 8288 Bus Controller
` In maximum-mode, the signal to control memory, I/O, and interrupt interface is produced by 8288. ` WR, IO/ M, DT/R , DEN, ALE, and INTA are no longer produced by 8088, instead 8288 generates the following signals
MRDC -- memory read command MWTC -- memory write command AMWC -- advanced memory write command IORC IOWC

-- I/O read command -- I/O write command -- interrupt acknowledge command

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AIOWC -- advanced I/O write command INTA

Bus Status Codes

a 8288 produces the commands according to the output bits S 2 S1 S 0 from 8088.
Status Inputs S2 S1 S0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 8288 Command Interrupt Acknowledge INTA Read I/O Port IORC Write I/O Port IOWC, AIOWC Halt None Instruction Fetch MRDC Read Memory MRDC Write Memory MWTC , AMWC Passive None CPU Cycle
(In maximum-mode)

CPU 8088
S0 S1 S2

Bus Controller 8288

command

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Queue Status Codes

a Two new signals are produced by 8088 in maximum-mode : QS0 and QS1. The two-bit code tells the external circuitry what type of information was removed from the Instruction queue in the previous cycle.
QS1 0 (low) QS0 Queue Status 0 No Operation. During the last clock cycle, nothing was taken from the queue. 1 First Byte. The byte taken from the queue was the first byte of the instruction. Queue Empty. The queue has been reinitialized as a result of the execution of a transfer instruction. Subsequent Byte. The byte taken from the queue was a subsequent byte of the instruction.
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1 (high)

(In maximum-mode)

Pin Diagram

386DX processor view from pin side

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Top view for 386SX processor

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Vcc

Minimum Mode System Block Diagram and Pin Connections

8284A RES clock generator CLK MN/ MX READY IO/ M RESET RD WR 8088 INTA CPU DT/ R DEN ALE AD0-AD7 A8-A19 INTR

Vcc

GND

GND

STB OE

Address /data 8282 Latch

(1, 2 or 3)

Address

T OE 8286 Transceiver

Data

EN 8259A Interrupt controller

WEOE

OE 27162 PROM

CS

RD WR Peripheral

2142 RAM (2)

IR0-7

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INT

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8088 Pin Functions

The 8088 pins may be grouped into the following nine categories: 1. Power Supply and Clock (VCC, GND and CLK) a VCC=5 volts (5 or 10% tolerance) a Maximum current needed is 340 mA (10 mA for CMOS version) a BOTH ground (GND) pins must be connected to 0V. a CLK input needs a periodic rectangular waveform with rise and fall times of less than 10ns. Clock frequency must be between 2 and 5 MHz. (see ch06, clock chip 8284). 2. Minimum/Maximum Mode pin a Minimum mode selected when (MN/MX) is connected to +5V

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8088 Pin Functions

3. Status Pins ( S0, S1 , and S2 ) - in maximum mode only The status pins are outputs which are used by the 8288 bus controller to generate control signals according to the following table:

S2 0 0 0 0 1 1 1 1

S1 0 0 1 1 0 0 1 1

S0 0 1 0 1 0 1 0 1

Meaning Interrupt acknowledge (INTA) I/O read I/O write HALT Code access (fetching instruction) Memory read Memory write Passive state (not used)

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8088 Pin Functions

4. Bus Master pins (HOLD, HLDA, RQ/GT0, RQ/GT1 and LOCK) Control of the local bus is transferred to other devices with the aid of the following signals: Minimum Mode - HOLD and HLDA (hold acknowledge) Maximum Mode - request/grant (RQ/ GT0 , RQ/ GT1) and LOCK a HOLD is an input (in minimum mode only) which tells the processor to suspend operations and allow other devices to access the system bus. Program execution only resumes when HOLD=0. a HLDA (hold acknowledge) is an output which informs other devices in the system that the 8088 is in a HOLD state. When another device wants to access the bus, it waits for HLDA=1.

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8088 Pin Functions

4. Bus Master pins (cont.) (HOLD, HLDA, RQ/GT0, RQ/GT1 and LOCK) a Request and Grant pins (RQ/ GT0 and RQ/ GT1) are used only in maximum mode and they function both as inputs (to accept requests) and outputs (to grant requests). When another device wants to become the BUS MASTER (i.e. take control of the local bus) it issues a request by pulling one of the request pins to a low logic state for one clock cycle. After a request is received, the 8088 enters a HOLD state and sends a grant signal on the same pin. RQ/ GT0 has a higher priority over RQ/ GT1. a _ LOCK is an output pin in maximum mode and informs other devices that they cannot takeover the local bus

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8088 Pin Functions

5. Interrupt pins (NMI, INTR and INTA) Interrupt acknowledge pin (INTA ) is available only in minimum mode. NMI (non-maskable interrupt) and INTR (interrupt request) are present in both modes. a The NMI (non-maskable interrupt) is an input which accepts a rising edge to trigger the interrupt. It cannot be disabled by software. Interrupt number 2 is generated by an NMI. a INTR is an input which accepts a high logic level as an interrupt request. Provided the interrupt flag in the FLAGS register is enabled, the processor will respond to the interrupt request in the same way as it processes an software INT instruction. a _ INTA acknowledges an interrupt request and indicates to the interrupting device that it should place an 8-bit interrupt number on the data bus
(Refer to Part 10-Interrupt for details)
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8088 Pin Functions

6. RESET An input which resets and initializes the processor. After a RESET the processor reads memory location FFFF0h for an instruction. 7. Bus control pins A group of 7 pins that generate the control signals for data transfer to and from the data and address bus in minimum mode. In maximum mode only two (RD and READY) of these 7 functions are available directly (the other bus protocol signals are generated from the status pins). The seven pins in this group include: a READY - an input to tell the processor that the selected memory or I/O port is ready to complete a read or write operation. If READY is not asserted, wait states are added (e.g. For slow memory).

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8088 Pin Functions

7. Bus control pins (cont.) a RD __ (read) - an output indicating that the processor is performing read operation from memory or an I/O port. a ALE (addressing latch enable) - an output to demultiplex the address/data pins. When ALE is high, address information is being sent. a DEN __ (data enable) - an output used with an external tristate buffer to disconnect the processor data pins from the data bus. (When DEN is low the processor data pins should be connected to the data bus) a __ DT/R (data transmit/receive) - an output indicates direction of data flow a __ WR (write) - an output to indicate when the processor is putting data into memory or I/O port a IO/M - an output indicates whether access is to memory or I/O ports ` The logic is different for 8086 & 8088 (8086: M/IO )

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8088 Pin Functions

8. Address, data pins and address status pins
a AD0-AD7 (address/data bus pins) - these pins output both address and data information and input data at different times of the bus cycle. Usually an external latch stores the address information form these pins before the pins are switched to carry data. Both the low and high order bytes of a 16-bit data word must be transferred via these pins. a A8-A15 (address bus pins) - used solely for specifying the address of a memory location or IO port. a A16/S3-A19/S6 (address bus or status pins) - these either carry memory addressing information or status information. S6 is always at logic 0. S5 describes the state of the interrupt flag in the FLAGS register. S4 and S3 describe the segment register being used to generate the physical address that was output on the address during the current bus cycle.
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8088 Pin Functions

8. Address, data pins and address status pins (cont.)
S4 0 0 1 1 S3 0 1 0 1 Segment register ES SS CS or no segment DS

a The address pins A0-A15 specify either a 16-bit I/O port number or the first 16 bits of a 20-bit address of a memory location.

9. Coprocessor interaction pins Three pins (TEST, QS0 and QS1) are used for interactions between the 8088 and 8087 arithmetic co-processor to synchronize MPU with external hardware.
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8088 Pin Functions

9. Coprocessor interaction pins (cont.) a __ TEST is an input pin that is tested by the WAIT instruction. If TEST is low, the WAIT instruction functions as a NOP. If TEST is at logic 1 then the WAIT instruction waits until it goes to logic 0 (MPU enters idle state). The TEST pin is often connected directly to a 8087 coprocessor (it must be connect to logic 0 if the 8087 is not present) (NOP: an instruction that does nothing) a QS0 and QS1 (queue status) pins provide the information of the 8088 internal instruction queue. The information is used by the 8087 coprocessor. The queue status bits indicate the contents of the internal instruction queue according to the following table:

QS1 QS0 instruction queue contents 0 0 No operation (queue is idle) 0 1 First byte of an opcode 1 0 Queue is empty 1 1 Subsequent byte of an opcode
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DC characteristics of Pin
a It is important to know the input and output characteristics which are required for hardware designer to select proper components. a Input characteristics: Output characteristics:
Logic Level 0 1 Voltage 0.8 V max 2.0 V min Current 10A max 10A max
Logic Level 0 1 Voltage 0.45 V max 2.4 V min Current 2.0mA max -400A max

Logic 1
Undetermined Range Input voltage range VIH(min) VIL(max)

Logic 1
VOH(min) Disallowed Range VOL(max)

Logic 0

Logic 0
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Output voltage range

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DC characteristics of Pin
a Noise immunity :
VNL [Low-level (Logic 0) noise immunity] = Vin_low (max)- Vout_low(max) VNH [High-level (Logic 1) noise immunity] = Vout_high(min)-Vin_high(min)

a For 8088, VNL is 350mV (=0.8V-0.45V). Typical logic circuit has noise immunity 400mV (=0.8V-0.4V). a Smaller noise immunity means 8088 and 8086 would encounter problem with longer wire or larger load. recommendation : no more than 10 loads a Recommended fan out: Family Fanout Sink Current Source Current
TTL (74XX) TTL (74LSXX) TTL (74SXX) TTL (74ALSXX) CMOS (74HCXX) CMOS (CD4XXX) NMOS
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1 5 1 10 10 10 10

-1.6 mA -0.4 mA -2.0 mA -0.2 mA -1.0 A -1.0 A -10 A

40 A 20 A 50 A 20 A 1.0 A 1.0 A 10 A
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FAQ
a What are sink and source current, and the sign of the current for a component?
` The component source current is the current that it will output to the next stage device when the component's output pin is high. ` The component sink current is the current that it will take in from its output pin when its output is at its logic low state. ` The minus sign for sink current is to denote that the current is flowing back to the component.

a What is Noise immunity?

` The noise immunity for logic low and high are defined in p.22 of part04. Pls use these definitions for the noise immunity. Please note that noise immunity is the difference between the INPUT and OUTPUT, not difference between logic 0 and logic 1.

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FAQ
a Why the difference between input and output is used for noise immunity calculation?
` Let's take a look of the noise immunity for logic 0. If you look at the figure in p.22, the output disallowed range is bigger than the undetermined range for the input, and V_IL (max)> V_OL(max). So if the output of logic 0 from a chip is corrupted with noise N, the aggregated signal into the other chip will have a max. value of V_OL(max)+N. This value should be less than V_IL so that the total amplitude will not fall in the undetermined range. So noise immunity for logic 0 is defined as V_IL(max)-V_OL(max). By the same token, the noise immunity for logic 1 can be defined.

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