Chapter - 1 Introduction

To achieve higher density and performance and lower power consumption, CMOS devices has been scaled down for more than 40 years. Transistor delay times decrease by more than 30% per technology. The rapid increase in the number of transistors on chips has enabled a dramatic increase in the performance of computing systems. However, due to this, power dissipation also increased, so cooling mechanism and expensive packaging is required. Also, supply voltage (Vdd) has been scaled down in order to keep power consumption under control. Hence, the transistor threshold voltage (Vth) has to be scaled down to maintain a drive current and achieve performance improvement. MOSFETs are fabricated with high overall doing concentration, lowered source/drain junction depths, high-mobility channel materials, etc. Furthermore, the reduction of the gate oxide thickness (tox) causes a drastic increase in the gate tunneling leakage current due to carrier tunneling through the gate oxide, which is strong exponential function of voltage magnitude across the gate oxide. [1], [2]

Figure1.1 Variation of Vth, performance and leakage

1.1 Sources of leakage current

Leakage current is the current flowing through transistors when it isnt switching. There are five main source of leakage currents in CMOS transistors 1. Sub threshold leakage (ISUB) 2. Gate oxide tunneling leakage (Ig) 3. Reverse-bias junction leakage ( IREV) 4. Gate Induced Drain Leakage (IGIDL) 5. Gate current due to hot-carrier injection (IH)

Figure 1.2 major leakage mechanism in MOS transistor[4] 1.1.1 Subthreshold leakage Supply voltage has been scaled down to keep dynamic power consumption under control. To maintain a high drive current capability, the threshold voltage (Vth) has to be scaled too. However, the Vth scaling results in increasing subthreshold leakage currents. Subthreshold current occurs between drain and source when transistor is operating in weak inversion region, i.e., the gate voltage is lower than the Vth. The drain-to-source current is composed by drift current and diffusion current. The drift current is the dominant mechanism in strong inversion regime, when the gate-tosource voltage exceeds the Vth. In weak inversion, the minority carrier concentration is almost zero, and the channel has no horizontal electric field, but a small longitudinal electric field appears due the drain-to-source voltage. In this situation, the carriers move by diffusion between the source and the drain of MOS transistor. Therefore, the subthreshold current is dominated by diffusion current and it depends exponentially on both gate-to-source and threshold voltage. The subthreshold leakage current can be expressed as:

= 0
Where 0 =
2 1.8 0

[1

voltage, Vgs and Vds are gate-to-source voltage and drain-to-source voltage. W and L
2

, =

is the thermal voltage, Vth is the threshold

are the effective transistor width and length. Cox is gate oxide capacitance, o is the carrier mobility, and n is the subthreshold swing coefficient. In short channel devices, source and drain depletion regions advances significantly into the channel influencing the field and potential profile inside that. These are known as short channel effects (SCE). Such effects reduce transistor threshold voltage due to the channel length reduction (Vth roll-off) and the DIBL increasing. This results in significant subthreshold current in short channel devices. Subthreshold leakage current occurs only in turned-off transistors.

Figure 1.3 Subthreshold leakage in NMOS transistor [2] 1.1.2 Gate oxide tunneling leakage To control the short channel effects, oxide thickness must also become thinner in each technology. Due to scaling of the oxide thickness, electric field increases, resulting in high direct-tunneling current through transistor insulator. The tunneling of electrons (or holes) from the bulk and source/drain overlap region through the gate oxide potential barrier into the gate (or vice-versa) is referred as gate oxide tunneling current. Direct tunneling is a function of the electric field across the gate oxide. The leakage of gate can be expressed as
2 0 =

Where Igate is gate leakage and Eox is the electric field across gate oxide and A and B are the parameter taking into account the related physics parameters, such as barrier height of conduction band and mass of electrons.

1.1.3

Band to band tunneling current Band to band tunneling current is the tunneling current between valance band and the conduction band in the depletion region of the junctions due to high electric field (>1016 V/m) across reverse-biased p-n junction. For tunneling to occur, the total voltage drop across the junction has to be more than the band gap.

Figure 1.4 BTBT in reverse-biased PN junction [2] 1.1.4 Reverse bias source/drain junction leakage The PN junction between the source/drain and the substrate are reversebiased, yet a small amount of current flows causing these junction to leak. This current is called reverse biased junction leakage current. The magnitude of this current depends on the area of source/drain diffusion and the current density, which is in turn determined by the doping concentration. Gate induced drain leakage The leakage current is caused by high electric field effect in the drain junction of MOS transistor. Over the years, transistor scaling has led to increasingly steep halo implants, where the substrate doping is low. This steep doping profile that results at drain edge increases the band-to-band tunneling currents there, as drain-bulk voltage (Vdb) increased. Thinner oxide and higher supply voltage increases GIDL current. Controlling the doping concentration in the drain of the transistor is the way to control GIDL. Gate current due to hot-carrier injection (IH) The leakage current is due to drift over time to the threshold voltage in short channel devices. The high electric field near Si-SiO2 interface can cause electrons or holes to gain sufficient energy to overcome the interface potential and enter into the oxide layer. This phenomenon is known as hot-carrier effect, which is more prominent with electrons than holes, as electrons has lower effective mass and barrier height than hole. These carriers trapped in the oxide layer change the threshold voltage of the device and consequently the subthreshold current. Proportionate scaling down of the supply voltage with the device dimension is the way of controlling this leakage.
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1.1.5

1.1.6

Chapter - 2 Circuit techniques for leakage current reduction

In CMOS circuit, total power dissipation includes both dynamic and static component during the active mode of operation. In case of standby mode, the power dissipation is related to only leakage currents. To suppress power consumption in low-voltage circuits, it is necessary to reduce leakage power in both active and standby mode. At process level, leakage reduction can be controlled by controlling the dimensions (length, oxide thickness, junction depth, etc.) and doping profile in transistor. To reduce leakage currents, following techniques are proposed: 2.1 Dual Threshold CMOS It is a static technique that uses a delay slack in non-critical paths to reduce leakage power. It provides both high and low threshold voltage (Vth) transistors in a single chip. High Vth transistors suppress the subthreshold current, while low Vth transistors are used to achieve high performance. But with the increase in Vth variation and supply voltage scaling, it is difficult to maintain sufficient gap among low Vth, high Vth and supply voltage required for dual Vth design. Also dual Vth design increases the number of critical paths in a die, decreasing both mean and standard deviation of die frequency distribution, so reduced performance.

Figure 2.1 Dual Vth CMOS circuit [4] 2.2 Supply voltage scaling This technique is used to reduce dynamic and leakage power. It is an effective method of consumption reduction due to the quadratic dependence of the switching power in relation to supply voltage. Lowering supply voltage provides an exponential reduction in subthreshold current.
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Gate oxide leakage also reduced by lowering Vdd even faster than subthreshold leakage. The optimal point for power savings using this technique is the lowest voltage which the circuit retains its logic states and same performance.

Figure 2.2 Gate oxide leakage current versus power supply [4] 2.3 Static supply scaling In static supply scaling, multiple supply voltages are used. First critical and noncritical paths of design are clustered and powered by higher and lower voltages, respectively. When circuit is in idle mode then combinational logic can fall to zero, hence power saving. Whenever output from a low Vdd unit has to drive an input of a high Vdd unit, a level conversion is needed.

Figure 2.3 Two-level multiple static supply voltage scheme [4] 2.4 Dynamic supply scaling In static supply scaling multiple supply is used, this problem can overcome by adapting the single supply voltage to performance demand. When performance demand is low, supply voltage and clock frequency are lowered, delivering reduced performance with substantial power reduction.
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However, this technique also having some problem like: Circuit has to operate over a wide voltage range. Operating system to intelligently determine the processor speed. Regulator to generate the minimum voltage for specific speed.

2.5 Transistor Stack effect Subthreshold leakage current flowing through a stack of series connected transistors reduces when more than one transistor in the stack is turned off. This effect is known as Stacking effect.

Figure 2.4 Two NMOS off-transistor stack [4] In above figure, when M1 and M2 are turned off, the voltage at the intermediate node (Vx) is positive due to a small drain current. This has three effect: With Vx positive, Vgs1 become negative; hence, the subthreshold current reduces subthreshold leakage. With Vx>0, Vbs1 <0 increasing the threshold voltage (Vth) of M1, and thus reducing subthreshold current. With Vx>0, Vds1 decreases, thus subthreshold current reduces. For a circuit having n inputs, there are 2n combinations for input states. Due to exponential complexity, method is limited to a small number of primary inputs. This technique can effectively reduce the leakage current using singlethreshold voltage.

2.6 Stacking Single Switch In CMOS complex circuits, there are more than one transistor branches, between supply voltage or ground node and output node. Such branches have different number of transistors. This basic idea of this technique is that duplicate transistors without increasing the longest transistor path, keep worst case delay to be same in both Pull-up and Pull-down separately.

Figure 2.5 (a) Original and (b) modified topology for leakage optimization CMOS gate [4] 2.7 Power Gating This technique uses the power supply voltage as the primary source for reducing leakage current. It using a MOSFET switch (sleep transistor) to cut off a circuit from the power rails (Vdd and/or gnd) during standby mode. During active operation, the power gating switch remains on, supplying the current that the circuit uses to operate. During standby mode, turning off the power gating switch reduces the current dissipated through circuit. Turning off the sleep transistor provides leakage current reduction for two primary reasons. First, the width of sleep transistor is usually less than total width of transistor being gated, which provides a linear reduction in total current drawn from supply node during standby mode. Second, leakage currents diminish when stacks or transistors are off. But during active mode, circuit performance reduces, because of a small positive voltage at virtual node. Hence, this technique is typically used for paths that are non-critical.
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2.8 MTCMOS Multi-threshold CMOS (MTCMOS) reduces the leakage by inserting highthreshold devices in series to low-threshold circuitry. Figure 2.6 shows a schematic of a MTCMOS circuit. A sleep control scheme is introduced for efficient power management. In the active mode, SL is set low and sleep control high transistors (MP and MN) are turned on. Since their on-resistances are small, the virtual supply voltages (VDDV and VSSV) almost function as real power lines. In the standby mode, SL is set high, MN and MP are turned off, and the leakage current id low. In fact, only one type of high-threshold is enough for leakage control. Fig. (b) and (c) shows the PMOS insertion and NMOS insertion scheme, respectively. The NMOS insertion scheme is preferable, since the NMOS on-resistance is smaller at same width; therefore, it can be sized smaller than corresponding PMOS.

Figure 2.6 Schematic of MTCMOS circuit [4] However, MTCMOS can only reduce leakage power in standby mode and a large insertion of sleep transistor can increase significantly area and delay. 2.9 Dynamic Vth Scaling All time, it is not required to require a fast circuit to operate at highest performance level. Active leakage techniques exploit this idea to slow down fast circuitry and reduce both leakage power and dynamic power consumption when maximum performance is not required. Dynamic Vth scaling (DVTS) scheme uses body biasing to adjust V th based on performance demand [42]. VTCMOS changes Vth in both active and standby mode, while DVTS modifies it based on circuit demand.

When highest performance is required, then Vth is lowest. For low performance demand, the clock frequency is lowered and Vth is raised via reverse body bias to reduce the run-time leakage power dissipation. When there is no workload, the Vth can be increased to its upper limit to significantly reduce the standby leakage power.

Figure 2.7 Schematic of DVTS hardware [4]

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Chapter -3 Conventional Full Subtractor design and its simulation results

A full subtractor is a combinational circuits that performs a subtraction between two bits taking into account that a 1 may have been borrowed by a lower significant stage. This circuit has three inputs and two outputs. The three inputs A, B and C denote the minuend, subtrahend and previous borrow respectively.

Figure 3.1 gate level design of a conventional Full subtractor [3] A 0 0 0 0 1 1 1 1 B C Difference 0 0 0 0 1 1 1 0 1 1 1 0 0 0 1 0 1 0 1 0 0 1 1 1 Table 3.1 Truth table of Full Subtractor [3] Borrow 0 1 1 1 0 0 0 1

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Simplified Boolean function: Difference= ABC + ABC + ABC + ABC Borrow= C (AB + AB) + AB

The output waveform for full subtractor using HSPICE as simulation tool:

Figure 3.2 Output waveform for Full subtractor

Where V(100), V(101), V(105) are A, B and C inputs of full Subtractor, respectively V(108) and V(109) is difference and borrow outputs, respectively

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Leakage Current Waveform for Full subtractor:

Figure 3.3 Leakage current waveform for Full subtractor

Using 32nm technology: The leakage current value comes out to be 21.285nA for conventional Full subtractor. Total voltage source power dissipation= 158.8487n watts Total Propagation delay = 1.001X10-5 Seconds

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Chapter 4 Full subtractor design using MTCMOS technique and its simulation results
The low power and high performance design requirements of modern VLSI technology can be achieved by using MTCMOS technology. This technique uses two different threshold voltage (Vth) for designing a CMOS circuit. Lowering the threshold voltages leads to an exponential increase in the subthreshold leakage current [5]. The low-threshold voltage transistors which have high performance is used to reduce the propagation delay time in the critical path. The high-threshold voltage transistors which have less power consumption are used to reduce the power consumption in the shortest path [6], [7].

The schematic of power gating technique using MTCMOS on full subtractor:

Figure 4.1 MTCMOS technique on full subtractor [3]

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The output waveform for modified full subtractor circuitry with MTCMOS technique using HSPICE as simulation tool:

Figure 4.2 Output waveform for Full subtractor using MTCMOS technique

Where V(200), V(201), V(202) are A, B and C inputs of full Subtractor, respectively V(203), V(204) are sleep and sleepbar inputs for sleep transistors, respectively V(207) and V(208) is difference and borrow outputs, respectively

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Leakage Current Waveform for Full subtractor using MTCMOS technique:

Figure 4.4 Leakage current waveform for full subtractor using MTCMOS technique

Using 32nm technology for full subtractor and 90nm for sleep transistor: The leakage current value comes out to be 1.5967nA. Total voltage source power dissipation= 49.5489n watts. Total Propagation delay = 8.006X10-6 Seconds

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Conclusion
Due to scaling of the CMOS devices, leakage current (mainly subthreshold and gate leakage current) have become a major contributor to total power consumption. So, to reduce this leakage current many techniques like transistor stacking, power gating, MTCMOS, dynamic Vth scaling have been proposed. In this work a modified full subtractor design have been proposed using MTCMOS technique for reduction of total leakage current. Conventional CMOS full subtractor and modified full subtractor have been implemented using HSPICE simulator and its leakage current reduced by 92.53%.

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Refrences
[1] D. A. Antoniadis, I. Aberg, C. N. Chlirigh, O. M. Nayfeh,A. Khakifirooz, and J. L. Hoyt, Continuous MOSFET performance increase with device scaling: The role of strain and channel materialinnovations, IBM J. Res. Develop., vol. 50, no. 4, pp. 363376, Jul. 2006. [2] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, Leakage current mechanisms and leakage reduction techniques in deep submicrometer CMOS circuits, Proc. IEEE, vol. 91, no. 2, pp. 305327, Feb. 2003. [3] Milind Gautam and shyam akashe, Reduction of leakage current and power in full subtractor using MTCMOS technique 2013 International Conference on Computer Communication and Informatics (ICCCI -2013), Jan. 04 06, 2013, Coimbatore, INDIA. [4] Paulo Francisco Butzen and Renato Perez Ribas, Leakage Current in Sub-Micrometer CMOS Gates [5] Hemantha S, Dhawan A and Kar H, Multi-threshold CMOS design for low power digital circuits, TENCON 2008-2008 IEEE Region 10 Conference, pp.1-5, 2008. .. [6] Dong Whee Kim, Jeong Beom Kee, Low-Power Carry Look-Ahead Adder With MultiThreshold Voltage CMOS Technology, in Proceeding of ICSICT International Conference on Solid-State and Integrated-Circuit Technology, pp. 2160-2163, 2008. [7] H. Thapliyal and N. Ranganathan, "Conservative QCAGate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits", Proc. of the 22nd Intl. Conf. on VLSI Design, New Delhi, India, pp. 511-516, 2009.

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