AMITY UNIVERSITY RAJASTHAN

Name of School: Amity School of Engineering and Technology

ODD SEMESTER 2013-2014

Course Handout
Program Course Code Course Title Faculty-in-charge Credits Course Details (a) Course Objectives: 1) To get familiar with the basic concepts computer architecture as well as organization and design. 2) To know the structure and behavior of various functional modules of a computer. 3) To know the way the functional modules interact with each other. 4) To understand the basic computer arithmetic. 5) To get introduced to the basic concepts of parallel computing. (b) Learning Outcomes: Upon successful completion, students will be able to: 1. 2. 3. 4. 5. 6. Operate logical components and relate them. Explain the various components of computer and relate them. Discuss general organization of the central processing unit. Describe hardwired and microprogammed control. Explain computer memory and intra system communication. Identify various parallel processing architectures. : : : : : B.Tech.-CSE/IT BTC/BTI 503 Computer Architecture Dr. Jitendra Kumawat 4

(c) Prerequisites: Students are supposed to have the introduction of basic logical elements like gates, adders, multiplexer and de-multiplexer along with the basics of computer memory and stack.

(d) Pedagogy/ Instruction Methodology: Lecture/Tutorial/Tests/Quizzes/ Home Assignments (e) Suggested Text and Reference Books Text Books: Computer System Architecture by Mano M. M., 3rd Edition. 2006, Prentice Hall of India. 2. Advanced Computer Architecture by Hwang K., 2008, Tata McGraw-Hill.
1.

Reference Books: 1. Computer Architecture and Organization by Hayes J. P., 3rd Ed.,1998, McGrawHill Inc. 2. Logic and Computer Design Fundamentals by Mano M. M. and Kime C. R., 2nd edition (Updated),2007, Pearson Education. 3. Computer Organization and Architecture by Stallings W., 4th edition, 2000, Prentice-Hall of India Private Limited. (f) Tentative Delivery Schedule:
Lecture No. Learning Outcome Suggested reading from Text Book (Section/Chapter No.)

Topics to be covered

Module No

1 2 3 4 5 6 7 8 9 10

Introduction to computer registers, Bus and memory transfer using MUXs and three state buffers Arithmetic microoperations Logic micro-operations Shift micro-operations Arithmetic logic shift unit Tutorial 1 Instruction codes-stored program organization, Basic computer registers and their organization Computer instructionstiming & control and instruction cycle

I I I I I I

II II II

11

Input-output, interrupt and design of accumulator logic

II

12

Introduction to hardwired control and control memory Introduction to micro programmed control and control memory
Address sequencing and design of control unit Tutorial 2 Introduction to CPU & general register organization Stack organization-register stack Stack organizationmemory stack Instruction formats-three address, two address, one address and zero address instructions

II

13

II

14 15 16 17 18 19

II

III III III III

20 21 22 23 24 25 26 27 28 29 30

Addressing modes Data transfer and manipulation Program control RISC and CISC Multiplication algorithmsBinary Multiplier Multiplication algorithmsBooths algorithm Array multiplier Division algorithms floating point arithmetic operations Tutorial 3 Memory- Introduction and memory hierarchy, main memory(RAM & ROM chips)

III III III III III III III III III

IV

31 32 33 34

Auxiliary memory & associative memory Cache memory Virtual memory Memory management hardware- segmented page mapping

IV IV IV IV

35 36 37 38 39

Peripheral devices and I/O interface Tutorial 4 IDE for hard disk, I/O port and Bus concept Bus cycle, synchronous and asynchronous transfer Interrupt handling in PC, parallel port, RS 232 interface & serial port in PC

IV

IV IV IV

40

41

Serial I/O interface, universal serial bus IEEE 1394, bus arbitration techniques Uni-bus and multi-bus architectures EISA bus, VESA bus

IV

IV

42

Parallel processing, pipelining & arithmetic pipeline

43 44 45 46 47

Instruction pipeline & RISC pipeline Vector processing & array processors Characteristics of multiprocessors, interconnection structures Interprocessor arbitration Interprocessor communication and

V V V V V

synchronization

48 49 50

Pentium and Pentium Pro Power PC architecture Quiz

V V

Evaluation Scheme:
S. N. 1 2 3 4 Evaluation Component Mid Term/Class Test Continuous Evaluation (Quizzes/Assignments) Attendance Final Examination Total Weightage % 15 10 05 70 100 Remarks Closed Book

Name of Faculty-in-charge Mobile Email Chamber Consultation Hours

: : : :

Dr. Jitendra Kumawat 9928091449 jkumawat@jpr.amity.edu To be announced

(Signature of the Faculty-in-charge)