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AMD FX 8350 Cache After the crushing disappointment that was the Bulldozer architecture and its line

of FX-CPUs last year, AMDs new CPUs now face an even sterner test. Since the release of the FX-8150 and the subsequent line of FX-branded CPUs, Intel has compounded its woes with its Ivy Bridge architectures 22nm die-shrink, increasing performance while dropping power consumption. AMDs response is its new line of FX-CPUs (codenamed Vishera), led by the flagship chip, the FX-8350 and based on its new Piledriver architecture. The updated 2nd generation FX series processors have been built upon what you guys know as the Vishera architecture, all managed on the very same 32nm fabrication node. Each Vishera processor will have Piledriver units, or segmented modules. This is very simple, one Piledriver module basically has two logical AMD64 CPU cores tied together. With four Piledriver modules you thus get eight logical CPU cores. The roughly 1.2 Billion transistor count FX-8350 processor tested today thus has four Piledriver modules, each of which contains two AMD64 cores, and an integrated memory controller. We do need to get a little deeper into the processors cores as there have been significant changes. The 2nd generation Bulldozer cores are Piledriver, as such Piledriver cores are used inside the new Trinity APUs and not the FX series as well. AMD claims that they have tweaked the logical CPU cores a little to make them perform the way they are intended to be. Inside the processor you'll spot the clusters as explained. Per module we see two integer CPU-cores which both share a floating point unit. Each module has a 2MB L2 cache and the L3 cache. The processor cores have been tweaked, the average instruction per clock-cycle has improved by a another say 10%. One more improvement for Vishera is AMD Turbo Core 3.0, the technology has been enhanced. The Turbo mode can clock the processor cores up and down real fast when the power usage and temperature allow for it. The CPU tested today can turbo towards 4200 MHz. Caches then, there are no significant changes opposed to the last gen Bulldozer FX processor, however opposed to say Phenom II and Athlon II there are big differences alright.

Here again it's all quite simply. Each separate CPU core has 128 KB of Level 1 Cache, 16 KB/Core x8 Data cache 64-byte cacheline, 4-way associative, write-through. Then a L1 Instruction cache of 64KB is available, 2-way associative with a 64-byte cacheline x4. For the eight-core SKUs there is 8 MB of Level 2 Cache in total, 2 MB per module and this 1MB per core next to a 64-byte cacheline, 16-way associative. There is a third cache. AMD has designed a shared 8 MB L3 cache with 64 way associatively for both cores in a Piledriver module. Each Piledriver unit (per two cores) will have 2 MB L3 cache. Each module can access the entirety of the 8MB L3, although cache partitioning happens on a core & thread generation basis so its virtually impossible for one core to get allocated the full 8MB of L3. The one exception is that the four core FX4300 processor will have a 4MB L3 cache assigned to it. The FX 8350/8320 and 6300 will all have access to that large 8MB L3 cache.

Vishera processor die

For the 2nd generation of FX series processors will see four new processors being launched today. Two of them featuring eight processing cores while the two other include six and respectively four cores.

The fastest of the upcoming chips is called the FX-8350 and it supports a base frequency of 4.0 GHz with a maximum Turbo frequency of 4.2GHz, 8MB of Level 2 cache memory, and has a TDP of 125W. The FX 8320 will be the same yet with lower clock frequencies, 3.5 GHz on the core and 4 Ghz on the turbo. Dropping down from eight to six cores we find the FX-6300 which will be clocked at a base frequency of 3.5 GHz with Turbo's towards 4.1 GHz. An 6MB L2 cache here as each core has 1 MB of L2. The fourth and final processor released today is the FX-4300 which will have four CPU cores that are clocked at 3.8 GHz with a 4 GHz Turbo and a 4 MB cache.

INTERNATIONAL ISLAMIC UNIVERSITY MALAYSIA

ECE 3244 COMPUTER ORGANIZATION AND ARCHITECTURE

ASSIGNMENT 4 CACHE

Matric No: 1021513

Name : MUHAMMAD HUSAINI BIN BAHARIN SECTION 1

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