EECS 366: Computer Architecture Lecture Notes # 8

Shantanu Dutt
Department of Electrical $ Computer Engineering University of Illinois, Chicago Phone: (312) 355-1314 e-mail: dutt@ece.uic.edu URL: http://www.ece.uic.edu/~dutt

Processor Design : Myth8 Datapath and Control Unit

Shantanu Dutt

UIC

MEMORY SYSTEM Memory Data Bus

write 8 read

Memory Address Bus IR0 MAR

Clk mar_sel
rj rk 4-8 sign ext.

CPU IR1
opcode ir0_sel dr_enb
ri

Clk

dr_sel[0..1] Clk MDR

ir1_sel result_sel[0..1]
rj rk ri

opcode

r0write r7write

Fetch & Load IR (> 1cc) Decode & Incr PC (1cc) Read, Exe. (in ALU) & Write (>= 1cc) (b) A Simple Instruction Flow

Mux

Control Unit (CU)

control signals

ri_sel rj_sel rk_sel

Register File
Clk

control signals

a_sel[0..2] b_sel[0..2] cout, m7, v

cin

Clk

8 8 Read Bus A Read Bus B 8

alu_sel[0..2]

ALU

(a) The Myth8 Processor

Write Bus

Main di erences between Myth8 and Edu32

1. Myth8 has 8-bit wide datapaths, including memory bus width, vs. 32 bits for the Edu32 2. Word sizes are similarly di erent 3. There is no explicit PC in the Myth8. The PC resides in r7 in the register le|this makes loading the instruction address to the memory address bus more complex 4. Instruction size is 16 bits for the Myth8 its is 32 bits for the Edu32. So two memory fetches are required to get a single instruction in the Myth8 vs. only one for the Edu32 (the instruction size and the data bus widths are equal in the Edu32). 5. The Myth8 does not have any ALU input and output registers. This could potentially cause a (multiple cc) race condition for multiple cc ALU operations as the ALU o/p can write to the destination register before the operation is complete (if the CU is not properly designed). If the dest. reg. is the same as any source reg. the i/p to the ALU changes before the operation is completed potentially causing an incorrect result.

SIMPLE CONTROL UNIT FSM FOR MYTH8 -- Instr. Fetch & Arithmetic Instruction Execution
Reset result_sel=00 (select write bus) alusel=ADD, cin=0 ri_sel=1rj_sel=1rk_sel=1 (READ & EXECUTE & WRITE) [ri <- rj+rk]

r7=initial value

asel=7, bsel=7 alusel=OR mar_sel=1 r6_write=1 (FETCH0) [r6 <- r7, MAR <- r7]

[r7 <- r6+1, ir0 <- mem[mar]] asel=6 alusel=ADDA r7_write=1 ir0_sel=1; read=1 (FETCH1) wait=0 asel=7, bsel=7 alusel=OR mar_sel=1 r6_write=1 (FETCH2) [r6 <- r7, MAR <- r7] [r7 <- r6+1, ir1 <- mem[mar]] asel=6 alusel=ADDA wait=0 r7_write=1 ir1_sel=1; read=1 (FETCH3)

opcode=ADD

(DECODE)

opcode=MUL

[rj -> ReadBusA rk -> ReadBusB counter ,- m-1]

cntr0=0

wait=1

rj_sel=1 rk_sel=1 c_sel =1, count=m-2 (READ & EXECUTE) rj_sel=1 rk_sel=1

wait=1

NOTE: There is actually no multiplier and no counter in the myth8; we assume the existence of these units to illustrate multiple cc arithmetic operations.

alusel=MUL (Cont. EXECUTE) cntr0=1 result_sel=00 (MUL DONE) [rj -> ReadBusA (select write bus) rk -> ReadBusB] ri_sel=1 (EXECUTE & WRITE) [ri <- rj x rk]

MEMORY SYSTEM Memory Data Bus

write 8 read

Memory Address Bus IR0 MAR

Clk mar_sel
rj rk 4-8 sign ext.

CPU IR1
opcode ir0_sel dr_enb
ri

Clk

MDR

dr_sel[0..1] Clk

ir1_sel result_sel[0..1]
rj rk ri

opcode
Control Unit (CU)

r0write r7write
ri_sel rj_sel rk_sel

Fetch & Load IR (> 1cc) Decode & Incr PC (1cc) Read, Exe. (in ALU) & Write (>= 1cc) (b) A Simple Instruction Flow

Mux

control signals

Register File
Clk

control signals

a_sel[0..2] b_sel[0..2] cout, m7, v

cin

Clk

8 8 Read Bus A Read Bus B 8

alu_sel[0..2]

ALU

(a) The Myth8 Processor

Write Bus

Programming language-type representation of above Moore FSM. Note that mythsim microcode language syntax is slightly di erent.

1. // r7 =initial value (set by a reset signal) 2. // Load r7 into MAR and r6 Fetch0: a sel = 7 b sel = 7 mar sel = 1 r 6 write = 1 3. // Fetch higher-order byte of 16-bit instruction note that the memory is byte addressable Fetch1: ir 0 sel = 1 read = 1, a sel = 6 alu sel = ADDA r 7 write = 1 // control signals not speci ed are 0 r6 + 1]

4. // Load r7 into MAR and r6 Fetch2: a sel = 7 b sel = 7 mar sel = 1 r 6 write = 1 5. // Fetch lower-order byte of 16-bit instruction Fetch3: ir 1 sel = 1 read = 1, a sel = 6 alu sel = ADDA r 7 write = 1 // control signals not speci ed are 0

if wait then goto Fetch1 endif

r7

if wait then goto Fetch3 endif 6. Decode: if (opcode==ADD) then goto Add else if (opcode==MUL) then goto Mul endif // ADD and MUL are prede ned constants corresponding to the opcode values for these instructions

7.
Add:

rj sel = 1 rk sel = 1 alu sel = ADD c in = 0 result sel = ALU ri sel = 1, // 1 cc Add operation, select register speci ed in ri eld of IR for writing

8. Mul: rj sel = 1 rk sel = 1 c sel = 1 count = m ; 2, // Multiplication takes m cc's. After this cc, 1 cc will have elapsed since register reads and m ; 2 will be loaded into the counter. Note that the myth8 does not have either a multiplier in its ALU nor a counter. These are being assumed here to illustrate the CU design for multiple cc ALU execution phase. 9. Mul Wait: rj sel=1, rk sel=1, if (cntr0 == 0) then goto Mul Wait endif 10. alu sel = MUL result sel = ALU ri sel = 1,

goto Fetch0

goto Fetch0 endif

MEMORY SYSTEM Memory Data Bus

write 8 read

Memory Address Bus IR0 MAR

Clk mar_sel
rj rk 4-8 sign ext.

CPU IR1
opcode ir0_sel dr_enb
ri Clk

dr_sel[0..1]

MDR

Clk

ir1_sel result_sel[0..1]
rj rk ri

opcode
Control Unit (CU)

r0write r7write
ri_sel rj_sel rk_sel

Mux

control signals

Register File
Clk

control signals

a_sel[0..2] b_sel[0..2] cout, m7, v

cin

Clk

8 8 Read Bus A Read Bus B 8

alu_sel[0..2]

ALU

The Myth8 Processor

Write Bus

MEMORY SYSTEM Memory Data Bus

write 8 read

Memory Address Bus IR0 MAR

Clk mar_sel
rj rk 4-8 sign ext.

CPU IR1
opcode ir0_sel dr_enb
ri Clk

dr_sel[0..1]

MDR

Clk

ir1_sel result_sel[0..1]
rj rk ri

opcode
Control Unit (CU)

r0write r7write
ri_sel rj_sel rk_sel

Mux

control signals

Register File
Clk

control signals

a_sel[0..2] b_sel[0..2] cout, m7, v

cin

Clk

8 8 Read Bus A Read Bus B 8

alu_sel[0..2]

ALU

The Myth8 Processor

Write Bus

CU FSM Design Strategies: Design Correctness

1. For a major operation (e.g., fetch & decode), trace the datapath through the computer system (processor, memory, I/O, etc.) needed for executing this operation. 2. Break up the datapath into subpaths s.t. each subpath starts from a register read (explicit or implicit), has an optional operation, and, except possibly the last subpath, ends with a register write. 3. Each subpath needs to be implemented by a single state (control signals to implement the subpath are set in the corresponding state). 4. A subpath is dependent on the data produced as a register write in the previous subpath. This data dependency is re ected by their corresponding states following each other in the same order as the subpaths.
Major Operation
Register Register Register Register

[operation] Subpath 1

[operation] Subpath 2

[operation]

[operation] Subpath n

CU FSM Design Strategies: Design Correctness (contd.)

1. The subpath determination for the fetch-into-IR1-&-decode and increment pc = r7 operations is illustrated in the gure below subpaths are #'ed in italics
MEMORY SYSTEM Memory Data Bus
write 8 read

Memory Address Bus 2

ir0_sel r0write r0write

8 dr_enb O1 O2 ir1_sel
result_sel[0..1]

MAR 1

O1 O2 mar_sel

IR0

IR1

dr_sel[0..1] O1 MDR O2

CPU

opcode 3

Mux

ri_sel rj_sel rk_sel

Register File 1 r6 r7 2
O1 O2

a_sel[0..2] b_sel[0..2] cout, m7, v

cin

8 8 Read Bus A Read Bus B 8

alu_sel[0..2] "Datapath" for increment pc=r7

ADDA AND ALU

Write Bus

Datapath for fetch (to IR1) and decode

Myth8 and "datapaths" for fetch-decode & increment pc

CU FSM Design Strategies: Design Correctness{Other Issues

1. Connections to the input of the ALU (or any combinational logic) need to be maintained for the entire period of the required operation. For e.g., if there is a multiplier in the ALU, and multiplication takes 10cc to nish, the read control signals ( a sel b sel] or rj sel rk sel]) in the Myth8) have to be maintained for the entire 10 cc's so that the operand registers remain connected to the multiplier's inputs for the entire 10 cc's. 2. In multiple-cc operations, the write control signal for writing to the destination register should only be valid in the last cc of the operation to avoid mutiple-cc race conditions. So if M U L r1 r2 r3] is the multiplication instruction (r1 r2 r3) and takes 10 cc, a sel = 2 b sel = 3 (or rj sel = 1 rk sel = 1) should be maintained for the entire 10 cc's, while r 1 write = 1 (or ri sel = 1) should only be active in the 10'th cc. 3. Be careful not to keep on loading data into a register over multiple cc's while its content is supposed to be changing over those cc's (e.g., loading the initial count value in the counter in the hypotehtical Myth8).

CU FSM Design Strategies: Design E ciency

1. While subpaths of one operation need to be implemented in separate states, subpaths of 2 or more operations (at most one subpath from each operation) may be combined into one state if: (a) there is no data dependency between them (data produced by one is not needed by the other), and (b) there are no resource con icts|the same resource is not needed for more than one purpose in any clock cycle. Resources include registers, ALU, buses and other connections, memory. 2. Implementing subpaths of di erent operations simultaneously in one state, speeds up the overall speed over all operations and reduces the number of states required in the Control Unit.
MEMORY SYSTEM Memory Data Bus
write 8 read

Memory Address Bus 2

ir0_sel r0write r0write

8 dr_enb O1 O2 ir1_sel
result_sel[0..1]

MAR 1

O1 O2 mar_sel

IR0

IR1

dr_sel[0..1] O1 MDR O2

CPU

opcode 3

Mux

ri_sel rj_sel rk_sel

Register File 1 r6 r7 2
O1 O2

a_sel[0..2] b_sel[0..2] cout, m7, v

cin

8 8 Read Bus A Read Bus B 8

alu_sel[0..2] "Datapath" for increment pc=r7

ADDA AND ALU

Write Bus

Datapath for fetch (to IR1) and decode

Myth8 and "datapaths" for fetch-decode & increment pc

CU FSM Design Strategies: Design E ciency (contd.)

1. In the gure below, subpaths 1 of fetch-into-IR1-&-decode and increment pc = r7 operations can be combined into one state, as can subpaths 2 of these operations|note no resource con ict.
MEMORY SYSTEM Memory Data Bus
write 8 read

Memory Address Bus 2

ir0_sel r0write r0write

8 dr_enb O1 O2 ir1_sel
result_sel[0..1]

MAR 1

O1 O2 mar_sel

IR0

IR1

dr_sel[0..1] O1 MDR O2

CPU

opcode 3

Mux

ri_sel rj_sel rk_sel

Register File 1 r6 r7 2
O1 O2

a_sel[0..2] b_sel[0..2] cout, m7, v

cin

8 8 Read Bus A Read Bus B 8

alu_sel[0..2] "Datapath" for increment pc=r7

ADDA AND ALU

Write Bus

Datapath for fetch (to IR1) and decode

Myth8 and "datapaths" for fetch-decode & increment pc

Pipelined Myth8 Processor

MEMORY SYSTEM Memory Data Bus
write 8 read

Memory Address Bus

8 dr_enb O1 O2 ir0_sel
result_sel[0..1]

MAR

O1 O2 mar_sel

IR1
ir1_sel r0write r0write
ri_sel rj_sel rk_sel

IR0

dr_sel[0..1] O1 MDR O2

CPU

Fetch Stage

Fetch CU

opcode

Mux

Register File
O1 O2 8 8 Read Bus B

Read CU

a_sel[0..2] b_sel[0..2]
Read Bus A

Decode & Read Stage

Opcode register

Reg. file 8 o/p regs

ALU CU

cout, m7, v
cin

Decode & ALU Stage

ALU
Write Bus

alu_sel[0..2]

Write CU

ALU o/p register

Decode & Write Stage

The Myth8 Pipelined Processor